Optimization of Continuous-Time Pipeline ADC Architectures for Wideband Medium-Resolution Applications

Optimization of Continuous-Time Pipeline ADC Architectures for Wideband Medium-Resolution Applications Iván Ramírez Lechuga A Master’s Thesis Submitted to the Faculty of the Escola Tècnica d’Enginyeria de Telecomunicació de Barcelona Universitat Politècnica de Catalunya In partial fulfilment of the requirements for the degree of MASTER IN ELECTRONIC ENGINEERING Supervisors: Prof. Georges Gielen Prof. Xavier Aragonès Cervera Assistant-supervisor: Xinfa Zheng Academic year 2024 – 2025 ©Copyright KU Leuven Without written permission of the supervisors and the author it is forbidden to reproduce or adapt in any form or by any means any part of this publication. Requests for obtaining the right to reproduce or utilize parts of this publication should be addressed to Departement Elektrotechniek, Kasteelpark Arenberg 10 postbus 2440, B-3001 Leuven, +32-16-321130 or by email [email protected]. A written permission of the supervisors is also required to use the methods, products, schematics and programmes described in this work for industrial or commercial use, and for submitting this publication in scientific contests. Preface I would like to start by thanking everyone in the Erasmus program who has made my stay in Leuven possible. I would also like to thank my promotor, Professor Georges Gielen, for suggesting such an interesting topic for my thesis. And to show my deepest appreciation to my assistant supervisor, Xinfa Zheng, for leading me through every step of this project. I also thank the jury for reading and evaluating this text. My sincere gratitude also goes to my family and friends, especially those who kept me company on long working nights at the library. Iván Ramírez Lechuga i Contents Preface i Abstract iv List of Figures and Tables v List of Abbreviations and Symbols vii 1 Introduction 1 1.1 Motivation ................................ 1 1.2 Statement of purpose ........................... 3 1.3 Methodology and procedure ....................... 3 1.4 Thesis outline ............................... 3 2 Wideband Medium-Resolution ADCs 5 2.1 Gain-Centric ADC Model ........................ 5 2.2 Discrete-time Nyquist ADCs ...................... 6 2.3 Continuous-time Σ∆ ADCs ....................... 7 2.4 Continuous-time Pipeline ADCs ..................... 8 2.5 Conclusion ................................ 9 3 Continuous-Time Pipeline ADC: Architecture Definition 11 3.1 From DT to CT Pipeline ........................ 11 3.2 Design Challenges ............................ 19 3.3 Conclusion ................................ 22 4 Continuous-Time Pipeline ADC: Architecture Design Exploration 23 4.1 MATLAB Model Overview ....................... 23 4.2 Model of non-idealities .......................... 33 4.3 Conclusion ................................ 37 5 Continuous-Time Pipeline ADC: Architecture Optimization Results 39 5.1 Parameter optimization ......................... 39 5.2 Digital signal reconstruction filter .................... 40 5.3 Signal Transfer Function ......................... 43 5.4 Non-idealities ............................... 45 5.5 Conclusion ................................ 48 6 Conclusion 49 ii Contents A Sustainability Analysis and Ethical Implications 51 A.1 Sustainability Analysis .......................... 51 A.2 Ethical implications ........................... 53 Bibliography 55 iii Abstract Continuous-time pipeline (CT-Pipeline) ADCs are an emerging analog-to-digital medium-resolution converter architecture. Recently demonstrated examples prove that they are capable of achieving larger bandwidths than those of state-of-the-art continuous-time Σ∆ ADCs, which until now were the preferred wideband mediumresolution ADC choice. In this work, this type of converter is demonstrated through a MATLAB Simulink model. Throughout these pages, a detailed analysis and explanation of this topology is provided, while proposing solutions to some of the recurring design challenges. With regard to the implementation, the use of power-efficient VCO quantizers has been evaluated. A comparison is also conducted between two alternatives for the digital reconstruction filter. In addition, the most common non-idealities and their effects are also introduced and validated by simulation. The developed model of a 4-stage continuous-time pipeline ADC achieves a SNDR of 80 dB over a 400-MHz bandwidth. It is intended to serve as an initial step towards the implementation of a CT-Pipeline that achieves an SNDR of 70 dB. iv List of Figures and Tables List of Figures 1.1 Performance of relevant recently demonstrated ADCs, presented in ISSCC and VLSI [16]. The plot highlights DT-Pipeline, CT-Σ∆ and CT-Pipeline architectures. The performance objective of this project is also marked .................................. 2 2.1 Gain Centric ADC Model [25]........................ 6 2.2 DT Nyquist ADCl [22]............................ 7 3.1 1-stage DT pipeline with back-end ADC with its anti-aliasing filter and buffer ..................................... 12 3.2 Result of removing the sample and hold and buffer and pushing the filter into the ADC ................................. 13 3.3 Current signals examples from a residue generator. IV I represents the signal from the analog path, IDAC the one from the DAC and IRES the output residue. The difference between signals with and without delay alignment is showcased [25]......................... 14 3.4 Effect of adding a half clock cycle compensation delay for the DAC output. Signals in grey have no compensation, in black after adding a half cycle delay. Residue signal r(t) is considerably minimized [22]. . . 14 3.5 N-stage pipeline ADC [26].......................... 17 3.6 1-stage CT pipeline followed by a back-end ADC ............. 18 3.7 Driving current waveform of a DT and a CT pipeline ADC of the same SNR [26]................................... 19 3.8 Double sampling quantizer and its effect on an input at sampling frequency [19]................................. 21 4.1 MATLAB Simulink CT Pipeline ADC model ............... 24 4.2 Frequency-type VCO quantizer circuit, model and frequency spectrum in various nodes [28]............................... 26 4.3 Digital reconstruction filter ......................... 28 4.4 Noise minimization algorithm block diagram ............... 29 4.5 Frequency spectrum before (red) and after (blue) applying the frequency mask operation ................................ 30 v List of Figures and Tables 4.6 Static and delay errors caused by mismatch in DAC [18]......... 34 4.7 Maximum SNR of the CT Pipeline ADC due to the NRZ DAC jitter limitation. OSR = 4 and fin =BW = 400MHz ............. 36 5.1 Output frequency spectrum for flash quantizer version, impulse calibration (left) vs noise cancellation (right) reconstruction techniques . 41 5.2 Output frequency spectrum for VCO quantizer version, impulse calibration (left) vs noise cancellation (right) reconstruction techniques . 41 5.3 SNDR vs number of taps for flash quantizer version, impulse calibration vs noise cancellation reconstruction techniques .............. 42 5.4 SNDR vs number of taps for VCO quantizer version, impulse calibration vs noise cancellation reconstruction techniques .............. 42 5.5 Comparison of STF: ideal, same filter per stage design, different filter with specific Q design ............................ 44 5.6 Comparison of STF: Flash vs VCO quantizers ............... 44 5.7 STF with different reconstruction filter implementations ......... 45 5.8 DAC Mismatch static, delay, rise and fall time errors ........... 46 5.9 Maximum SNR due to different jitter levels for three separate input frequencies .................................. 47 5.10 First stage third-order nonlinearity effect on SNDR ............ 47 List of Tables 5.1 Parameter optimization for the flash sub-ADC version of the CT Pipeline. 40 vi List of Abbreviations and Symbols Abbreviations ADC Analog-to-Digital Converter BW Bandwidth CT Continuous-Time DAC Digital-to-Analog Converter DEM Dynamic Element Matching DR Dynamic Range DT Discrete-Time FF Flip-Flop FFT Fast Fourier Transform FIR Finite Impulse Response IIR Infinite Impulse Response ISG Inter-Stage Gain ISI Inter-Symbol Interference LS Least Squares LSB Least Significant Bit LTI Linear Time Invariant MSB Most Significant Bit NRZ Non-Return-to-Zero NSD Noise Spectral Density NTF Noise Transfer Function OSR OverSampling Ratio PRBS Pseudo-Random Bit Source QTZ Quantizer S&H Sample & Hold SNR Signal-to-Noise Ratio SNDR Signal-to-Noise-and-Distortion Ratio STF Signal Transfer Function VCO Voltage Controlled Oscillator vii 2. Wideband Medium-Resolution ADCs Figure 2.1: Gain Centric ADC Model [25] the case, the digital block would not be able to properly reconstruct the signal, and the output noise would be much greater than the quantization one. 2.2 Discrete-time Nyquist ADCs According to the model presented in the previous section, different types of ADC could be distinguished. For example, by overseeing the quantization noise distribution over the frequency spectrum, a distinction can be made between Nyquist ADCs, in which the noise is uniformly distributed over the Nyquist bandwidth, and noiseshaping ADCs, with shaped quantization noise. If we were to look at the architecture of the analog gain block, we could separate discrete-time ADCs, those that use switched capacitor filters, from continuous-time ADCs, which employ active-RC or gm-C filters. Discrete-time (DT) Nyquist converters have been the default choice for most ADC applications. The wideband medium-resolution case is not different. Discrete-time pipeline ADCs have historically been used to achieve the desired bandwidth [ 21 ] [ 11 ] [1]. The first element present in a discrete-time pipeline ADC chain is a sample and hold (S&H) circuit. Because of this, an anti-aliasing filter is needed upfront. Its purpose is to attenuate all out-of-band components, so that when sampling occurs, no images appear in-band that might interfere with the signal bins. The design of this filter is not easy since the bandwidth will be close to the Nyquist frequency. Ideally, a steep roll-off out of the signal bandwidth would be desired, to ensure a better suppression of out-of-band components. To achieve this, a high-order filter would be needed, which would come at the cost of high area occupancy and high power consumption. An alternative approach which has been commonly used is to increase the oversampling ratio (OSR), defined as the quotient between the Nyquist frequency and the signal bandwidth. If the Nyquist frequency is pushed away from the filter cutoff, then steep attenuation is not as important. But this technique 6 2.3. Continuous-time Σ∆ ADCs Figure 2.2: DT Nyquist ADCl [22] also has some penalties. The possibility of increasing the sampling frequency is technology limited and employing time-interleaving strategies might be required. A higher sampling frequency will also increment the power consumption of the digital stage and the decimation filter. Another issue with discrete-time converters in general is related to the driving capabilities of these circuits. Since the input is a switched capacitance, it will require a specific buffer on-chip to feed a high peak current. Designing such buffer is complex and is carried out with class-A or class-AB amplifier architectures [ 26 ]. It is usually a relevant source of noise and distortion, with an important power consumption, and it may require a higher supply voltage than the ADC [22]. According to the given description, a typical discrete-time Nyquist ADC signal chain is presented in Figure 2.2. It starts with an anti-aliasing filter. As was previously discussed, this block is power-hungry and complex to design, which justifies why it is often implemented off-chip. Then, a driving buffer is needed, which adds considerably to the power demand. It drives a sample and hold circuit, that requires a decently sized capacitor to satisfy the noise performance of the given application. The ADC then performs the conversion and transforms the signal into the digital domain. Lastly, a decimation filter is employed, to remove the effects of aliasing during the downsampling operation. 2.3 Continuous-time Σ∆ ADCs As the limitations of the discrete-time converters became apparent, new continuoustime architectures appeared as candidates. The most successful was the continuoustime Σ∆ ADC. It solved most of the problems the discrete-time pipeline variation had by moving the sampling quantizer to the end of the analog chain. In this type of converter, the analog gain block consists of a cascade of integrators. With this structure, an attenuation of the signal bins multiples of the sampling frequency is achieved before the last sampling quantizer. That means that the anti-aliasing filter that previously preceded the ADC can be relaxed or even removed, as its function is inherited in the converter’s architecture. 7 2. Wideband Medium-Resolution ADCs Another block whose requirements are eased is the input buffer, as the input is no longer capacitive but instead resistive. In order to obtain the same kT/C noise in a discrete-time architecture as thermal noise in a continuous-time one, the peak driving current should be much higher [ 25 ][ 26 ]. Consequently, power and area consumption are greatly reduced. Relaxing both the anti-aliasing filter and the driving buffer requirements means that continuous-time Σ∆ ADCs are much easier to integrate than discrete-time ones. Not only do less circuit blocks need to be designed, but it is much easier to achieve certain specifications (such as signal distortion) with a single ADC block than with a whole signal chain. The main limitation of this type of converter is revealed as higher bandwidths are needed. To achieve a high SNDR, Σ∆ ADCs employ noise-shaping, a technique which consists in moving the quantization noise in the signal band to higher out-ofband frequencies. Its effectiveness depends on the order of the modulator. For that modulation to be possible and to achieve better noise shaping, it is necessary for the sampling frequency to be much greater than the bandwidth. For these reasons, a high OSR > 20 [ 25 ] is often used. As bandwidth requirements become more demanding, the sampling rate needed is excessively high. Closing the feedback loop with such frequencies is both power-hungry and complex, rendering this architecture not feasible for certain applications. Another less important problem found in these types of converters is related to their signal transfer function (STF). Due to the nature of the modulation applied to achieve noise shaping, some power efficient structures present a peak outside of the signal bandwidth. If high-amplitude out-of-band signals were present at the input, saturation could occur, effectively limiting the dynamic range (DR) of the ADC. [ 19 ] Regarding the power consumption, the continuous-time Σ∆ achieves notable savings with respect to Nyquist ADC architectures, because of the removal or relaxation of the filter, buffer and sample and hold blocks. However, for wideband converters, the clock distribution and the decimation filter of the Σ∆ will consume more due to the higher frequency. [23] 2.4 Continuous-time Pipeline ADCs A novel architecture has been recently demonstrated that addresses most of the concerns discussed in this chapter: the continuous-time pipelined ADC. In brief, its design mimics a discrete-time pipeline while removing the sample and hold circuitry and combining the filter and ADC in the same block. Returning to the gain-centric ADC model presented in Section 2.1, it is as if the analog gain block of the pipeline was replaced by a continuous-time one (some additional architecture modifications are required). It promises to bridge the gap between the two previous types of converters by combining its individual advantages without many of the drawbacks. First, since it is a continuous-time ADC, it does not employ a S&H at the input. The resistive behavior makes it easily driven without the need of a specific buffer. Also, integrating the filter inside the ADC means that inherent anti-aliasing is present while 8 2.5. Conclusion allowing a much simpler filter design than in its discrete-time counterpart. Therefore, the continuous-time pipeline retains the main advantages that the continuous-time Σ∆ had over discrete-time Nyquist ADCs. The CT pipeline ADC is similar to the discrete-time one in the sense that it can achieve a wide bandwidth without having to adopt extreme oversampling (typically, OSR = 4). It could even achieve higher sampling frequencies than discrete-time pipelines [ 26 ] (if time-interleaving techniques are not considered) because settling time requirements for amplifiers are no longer a necessity. That makes it easier to design, less power-demanding and more robust to clock jitter than continuous-time Σ∆ converters for wideband applications, although Σ∆s are more power efficient at lower bandwidths. Furthermore, its signal transfer function presents a steeper roll-off. As will be further developed in the next chapter, this architecture can achieve an improvement in power and area, for the same levels of noise and distortion, when compared to discrete-time Nyquist ADCs, while also providing the benefit of continuous-time architectures. It can reach greater bandwidths than continuous-time Σ∆ converters with a lower oversampling ratio. Hence, the continuous-time pipeline ADC presents itself as the most promising option for wideband medium-resolution analog-to-digital converter applications. 2.5 Conclusion In this chapter, the main types of ADC historically used in wideband mediumresolution applications have been presented. It has been explained how the discretetime Nyquist ADCs, although suitable, show some design complications due to their input driveability and anti-aliasing filter requirements. Later, it has been shown that continuous-time Σ∆ converters have been employed to overcome these issues. However, it has been stated that their oversampling demands prevent them from being used in wideband scenarios. Finally, the continuous-time pipeline ADC has been introduced, which avoids the disadvantages of discrete-time converters while being able to achieve wide bandwidths, essentially turning them into the theoretically preferred architecture. 9 Chapter 3 Continuous-Time Pipeline ADC: Architecture Definition In this chapter, the architecture of the continuous-time pipeline ADC is introduced. First, an in-depth explanation will be given, so that the reader can understand the function of each subblock and its importance to the overall system. Then, an analysis will be provided of different performance parameters, such as noise, linearity and power. Finally, the main design difficulties of the continuous-time pipeline are presented, as well as the most relevant state-of-the-art solutions. 3.1 From DT to CT Pipeline 3.1.1 The DT Pipeline ADC The continuous-time pipeline ADC is a novel architecture that has its origins in several modifications applied to a discrete-time pipeline converter to benefit from the advantages of continuous-time operation. Because of that, the following explanation will start from the discrete-time architecture. Consider the discrete-time pipeline ADC shown in Figure 3.1. It consists of one stage of pipelining followed by a back-end ADC. In this example, both the quantizers and DACs are multi-bit. The block diagram also displays both the anti-aliasing filter and the buffer used to drive the sample and hold circuit. The operating principle of a discrete-time pipeline ADC is the following. In the first substage, the most significant bits N1 (MSBs) are converted to the digital domain by the quantizer QTZ1. Since this information has already been acquired, the next pipeline stages only need to obtain the remaining N−N1 bits, N being the total bit resolution of the ADC. This means that the component associated with the first digital value can be simply removed from the signal. To achieve this, DAC1 is used. This block converts the output of the quantizer back into the analog domain. The difference between this signal and the stage input is then calculated. The result is a residue containing the information of the N−N1 least significant bits. As the obtained signal has a peak value that corresponds to the 11 3. Continuous-Time Pipeline ADC: Architecture Definition Figure 3.1: 1-stage DT pipeline with back-end ADC with its anti-aliasing filter and buffer weight of the N−N1 bit, it can be amplified to take full advantage of the dynamic range of the quantizer in the next stage. If both QTZ1 and QTZ2 use the same reference voltage, this gain G1 can be 2 N1 , although a fraction of it is usually selected to account for potential conversion errors. This operation of amplifying a residue signal is the core mechanism of pipelining converters. As the signal is multiplied by a gain Gi> 1, so is the step size of the next quantizer. This translates into a relaxation of the input and resolution requirements of each of the sub-ADCs. The converted values of all stages add up to the ADC output. It is also necessary to compensate for the different gains between stages. In this example, it means dividing the output of QTZ2 by G1. Both of these operations are performed in the digital domain. In the previous chapter, the fundamental changes needed to transition from a discrete-time to a continuous-time pipeline ADC were briefly introduced. These consist of removing the sample and hold circuit, also eliminating the driving buffer as a consequence, and pushing the anti-aliasing filter inside the ADC. The results of these modifications are displayed in Figure 3.2. If a converter with the architecture presented in Figure 3.2 was designed, it would not work properly. Due to various effects related to the continuous-time operation, some signals would cause saturation. Therefore, several corrections must be made. The different causes and their respective solutions will be presented in the next subsections. 3.1.2 Delay alignment Since the sample and hold circuit at the ADC input has been eliminated, the signal from the analog path that produces the residue is now identical to the input. The removal of the discretization artifact implies that it will be continuous instead of holding the value for the duration of a clock period. However, the sub-ADC-DAC 12 3.1. From DT to CT Pipeline Figure 3.2: Result of removing the sample and hold and buffer and pushing the filter into the ADC path still operates over time steps. This difference will become evident once the residue between the two signals is calculated. An example of the signals from the input and output nodes of a residue generating block is shown in Figure 3.3. The waveforms specified as w/o delay are the ones corresponding to the architecture presented in Figure 3.2. As can be seen, there is a delay between the arrival of the signal from the analog path and the DAC, causing a greater peak-to-peak swing in the residue than expected. The goal of the ADC-DAC coarse approximation is to minimize the difference signal as much as possible, so that the interstage gain can be increased and the overall conversion can benefit from it. Hence, this misalignment must be corrected. The apparent delay has two components: • One clock period, accounting for the ADC conversion, data propagation and settling time. • An additional half-clock period of effective delay for the DAC, which is the one that causes the best possible residue minimization, as can be seen in Figure 3.4. Pioneer continuous-time pipeline work [ 8 ] proposed to implement these oneand a half-cycle delay corrections using a predictive filter on the sub-ADC-DAC path. Functionally, it is as if a negative delay had been introduced. However, this approach is not very practical. To make value predictions, this filter would require a positive phase. However, for high frequencies, the response must turn into a negative phase. Otherwise, the filter would not respect causality, meaning that the output would not only depend on past and present inputs. For this to be accomplished, a wide-bandwidth operational amplifier would be needed, which is very complex to implement at high frequencies. 13 3. Continuous-Time Pipeline ADC: Architecture Definition Figure 3.3: Current signals examples from a residue generator. IV I represents the signal from the analog path, IDAC the one from the DAC and IRES the output residue. The difference between signals with and without delay alignment is showcased [25] Figure 3.4: Effect of adding a half clock cycle compensation delay for the DAC output. Signals in grey have no compensation, in black after adding a half cycle delay. Residue signal r(t) is considerably minimized [22] 14 3.1. From DT to CT Pipeline The adopted solution has been to instead introduce a positive delay in the analog signal path. It can be realized by using passive delay elements, which have a simpler implementation. LCor RC-lattice delay lines are employed [ 26 ] [ 19 ] [ 15 ]. Although the first can achieve better residue cancellation over a wider bandwidth, the latter occupies less silicon area. Another disadvantage of the RC-lattice variant is that its input impedance decreases at higher frequencies, demanding a higher driving current. A more in-depth comparison can be found in [25] and [26]. 3.1.3 Residue amplifying filters The next relevant aspect to discuss is related to the interstage block architecture. As was anticipated before, in Figure 3.2, when the anti-aliasing filter is pushed inside the ADC it is placed next to the different gain blocks. Implementation-wise, the two functionalities are combined in the same circuit block: the residue-amplifying filter. In previous discrete-time architectures, the magnitude of the residue signal had a confined value. In particular, its range was ±VF S/M , where VF S refers to the full-scale voltage of the M-level ADC and DAC pair. However, in practice, larger values can appear due to certain implementation errors, such as comparator offsets. As the input is now continuous, its value is no longer bounded. It still depends on the sub-ADC and DAC resolution, but also on the sampling rate. If the signal presents very fast changes, there will be no advantage in utilizing a larger number of quantizer levels. Some typical established values for these circuits are a first-stage resolution between 3 and 5 bits and an oversampling ratio OSR = 4. [15] As the residue presents higher peaks, the interstage gain must be reduced accordingly. A predetermined value, as was the number of quantizer levels in discrete time, no longer exists. Instead, a smaller gain should be selected so that the peak-to-peak of the residue signal does not saturate the next stage. The output of the residueamplifying filter should be a fraction of the next quantizer dynamic range (a swing of half the dynamic range is recommended in [21]). With respect to the filtering section, inherit anti-aliasing is now part of the architecture. As the filter that previously preceded the converter is broken down and distributed over the various pipeline stages, and the signal is restored with a digital reconstruction filter, an equivalent functionality is achieved to that of an anti-aliasing filter followed by a Nyquist ADC (detailed in Section 3.2.3). For example, sixth-order filtering could be achieved with three second-order stages. This implementation choice offers several advantages that will be discussed later in this chapter. The filter can also be used to provide some attenuation for the leakage signal. Achieving a perfect cancelation is very complex, since mismatches will exist between the sub-ADC-DAC and the delay paths. For instance, the temperature effect can affect the voltage reference of the ADC and DAC or the value of the resistances and capacitances responsible for the delay. Interstage filtering also has the duty of reducing the value of these leakage components. Since the input of the first quantizer has not received a proper anti-aliasing treatment, image signals will appear at the output of the sub-DAC. These components will increase the magnitude of the residue signal, limiting the maximum selectable 15 3. Continuous-Time Pipeline ADC: Architecture Definition As was already discussed in Section 3.1.3, a reasonable agreed-upon criterion is to use second-order filter stages, as they provide a good trade-off between the relevant parameters. The general transfer function of a second-order filter is recalled in the following equation: G(s) = ω2 0 s2+ω0 Qs+ω2 0 (3.3) If the filters were designed without giving major importance to their parameters and f0 was selected as the desired ADC bandwidth, the performance will not be as expected. A significant dB droop will be observed in the STF at the edge of the band (f0), resulting from the product of many stages. Some recommendations to avoid encountering this problem are suggested in [ 19 ]. For example, the article proposes a f0 that is 10% higher than the required bandwidth. Another parameter to consider is the quality factor Q. A greater Qprovides a narrower resonance and less droop at f0 . However, a higher noise floor will also be obtained. A good strategy consists of selecting stages with different quality factors [ 19 ]. The last stage can use the greater Q, as at that point the noise is already significantly attenuated when referring to the input. 3.3 Conclusion In this third chapter, an in-depth review of the continuous-time pipeline ADC architecture was performed. The most relevant building blocks, as well as the main design challenges of this type of converter, have been discussed. After this chapter, the reader should have a better understanding of the core advantages of this architecture and the justifications behind them. However, throughout these pages, it has also been evidenced that the implementation of this novel ADC presents various complexities that are currently being addressed at the forefront of research centers. 22 Chapter 4 Continuous-Time Pipeline ADC: Architecture Design Exploration In the previous chapter, the reader was able to learn not only about the continuoustime pipeline ADC architecture, but also about the discussion topics around it in current state-of-the-art research. In the following sections, the main work that encompasses this project is presented. An exploration of the architectural design options for the converter is performed. This task has been carried out employing circuit modeling techniques and simulation software. This chapter is going to focus on the demonstration of the developed models. 4.1 MATLAB Model Overview To explore and optimize different design choices, a MATLAB Simulink model of a continuous-time pipeline ADC has been developed. Its base form is shown in Figure 4.1. It consists of a 3-stage CT pipeline followed by a back-end ADC. In this first section, the main blocks that make up this model are presented. They are designed and optimized with the goal of obtaining 80 dB SNDR over a 400 MHz bandwidth with an OSR = 4 and an input dynamic range of ± 1 V . Different options and architecture considerations complement each of the explanations. 4.1.1 Substage ADCs and DACs The first element that will be discussed are the substage ADCs and DACs. As could be expected, their relevance is crucial for the pipeline performance. Quantizer Quantizers play an important role in the converter, since they are the ones that transform the analog input into the digital domain, which is the sole purpose of the ADC. When it comes to quantizer architectures, two of them were modeled and tested in this work: flash ADCs and VCO(Voltage Controlled Oscillator)-based ADCs. 23 4. Continuous-Time Pipeline ADC: Architecture Design Exploration Figure 4.1: MATLAB Simulink CT Pipeline ADC model 24 4.1. MATLAB Model Overview The operation of a flash ADC is relatively straightforward: a resistive ladder is used to generate Nvoltage references, the difference of which with the input is amplified and fed into Ncomparators. The resulting Nsignals constitute the converted digital value [12]. Due to its design simplicity, this ADC topology is the one that can achieve the highest bandwidth. The maximum sampling rate is only limited by the preamplifier latency and the settling time of the comparators [28]. Its main drawback is its limited scalability. As the number of quantization levels Nincreases, so does proportionally the number of comparators, amplifiers and resistors that must be integrated. This implies a substantial increment in area, power and input capacitance. Therefore, flash ADC resolution is typically limited to around 6 or 7 bits [ 23 ] [ 28 ]. However, this is not an issue when trying to select a quantizer for the pipeline substages, as the maximum resolution is already limited to around 4 or 5 bits [21]. Another concern with flash quantizers is their potential inaccuracies caused by mismatches between the different elements. This issue is technology-dependent and its effect could only be reduced by increasing the area of the converter elements. A model of a flash ADC was added to Simulink, to be simulated in different configurations. It consists of a sample and hold followed by a block that implements the comparison with the array of reference voltages. The model has two outputs: an integer value in the range [0 , N − 1], where Nis the number of quantizer levels, and a normalized voltage in the range [−Vref , Vref ]. The other type of sub-ADC proposed for this work is the VCO-based quantizer. These converters have been growing in popularity in recent years, as they are compatible with digital implementation techniques and are therefore easily scalable with technology. VCO quantizers usually employ a ring oscillator whose input voltage is the one that needs to be converted and that controls the oscillation frequency. The different phases of the ring are fed into a block that counts the total number of transitions per clock period. This quantity ends up being the converted digital value. The particular quantizer modeled in this work is a frequency-type VCO quantizer [ 28 ]. In this case, a single flip-flop (FF) counts the transitions of each phase. This implies that the maximum number of transitions per clock period is one or, in other words, that the VCO frequency is limited to half of the sampling rate. The output of this FF goes through a first-order difference block. It is implemented with an additional FF and an XOR gate and its output is a logical 1each time a transition has been detected (see Figure 4.2) [28]. A VCO-based quantizer presents several advantages over a flash ADC. It has improved noise performance because it contains an integrating function in the chain. Although the STF has a gain of unity, the noise transfer function is NTF = 1 −z−1 [24], which means that noise is first-order shaped. VCO quantizers are also more robust to mismatch-based errors. The reason is that the output changes by sequential transitions instead of requiring precise voltage comparisons. The errors originating from mismatch are, therefore, spread over time, which reduces their effects. 25 4. Continuous-Time Pipeline ADC: Architecture Design Exploration Figure 4.2: Frequency-type VCO quantizer circuit, model and frequency spectrum in various nodes [28] The VCO quantizer model in Simulink was based on the one shown in Figure 4.2. It consists of an integrator, a sample-and-hold block and a differentiator. The integrator models the function of voltage-to-phase conversion, while the sampling and differentiator are equivalent to the digital transformation blocks [28]. Although VCO-based ADCs offer several advantages, they are still inferior to flash when it comes to providing an accurate low-latency quantization. They are also more prone to introduce signal distortion. Since in the first pipeline stage conversion speed and linearity are critical, a hybrid architecture was adopted: using a flash ADC in the first stage and a VCO-based quantizer in the rest [ 27 ]. Throughout this document, each instance that refers to the VCO quantizer implementation will imply that this mixed approach is being applied. NRZ DAC The design of the sub-DAC, particularly the first stage one, is critical because it introduces most of the non-idealities that degrade the performance of the converter, as will be discussed in the second section of this chapter. Therefore, proper architecture selection must be a priority. A criterion for distinguishing different types of DAC is the shape of the output signal. For this application, a Non-Return-to-Zero (NRZ) pulse, in which the output is maintained at the same level throughout the duration of the whole clock period, is desired. Alternative options that switch between zero and non-zero values during a period cause large currents at the input of the residue amplifier and compromise its nonlinearity [20]. 26 4.1. MATLAB Model Overview Regarding its implementation, examples of resistive [ 19 ] [ 15 ] and current steering DACs [ 26 ] [ 27 ] are found in the literature. On the one hand, resistive DACs add the least amount of thermal noise possible [ 20 ] and are more power efficient. They can also benefit from an easier implementation, as they are simpler circuits and can take advantage of the virtual ground provided by the input of the next-stage amplifier [ 19 ]. In contrast, the current-steering DAC has a faster response and better precision. The model for the NRZ DAC is quite simple. It is based on a function that contains a vector with the values of each DAC level and outputs the correct voltage for the given digital input. After this function, a sample-and-hold operation takes place. An extra term can also be added to the output that models the jitter error of the DAC, which will be further explained in section 4.2.2. 4.1.2 Reconstruction filter Some reconstruction filter techniques were already explored in section 3.2.1. The key takeaway from those explanations is that the implementation of this block is complex (sometimes being off-chip), requires foreground calibration and is often susceptible to variations stemming from sources such as temperature. For this work, two alternatives were tested: a noise cancellation filter and a foreground impulse response calibration. Digital Noise Cancellation Filter The first technique consists of applying a Least Squares (LS) algorithm to the frequency spectrum of the signal at the inputs of the reconstruction filter. The purpose of this algorithm is to achieve in-band noise minimization. While interesting because it allows control of the full in-band response, its computation-heavy nature demands to be implemented outside of the chip, and prior calibration will be needed. This method is based on the noise cancelation presented in [ 4 ]. The analysis shown in the article demonstrates that the LS algorithm can restore the input signal while removing almost all noise contributions. The blocks that compose the filter are shown in Figure 4.3. It consists of three FIR stages, each from one of the outputs of the sub-ADCs. The back-end ADC output is treated as a reference for the algorithm. As can be observed from Figure 4.3, the signals get compensated for both interstage gain and delay in advance to achieve a proper cancellation. In order to estimate the FIR coefficients, the LS algorithm for noise minimization is applied over the nodes requiring cancelation. However, some signal processing is required beforehand, as the operations need to be performed in the frequency domain. Each of the steps of this processing chain is detailed in the next list and can be appreciated in Figure 4.4: 1. FIR input construction. For each of the processed nodes, an array of signals is constructed such that each one is delayed by one sample from the next one, as in the input of a FIR filter. The width of this array equals the number of FIR coefficients of each stage (Nin Figure 4.4). 27 4. Continuous-Time Pipeline ADC: Architecture Design Exploration Figure 4.3: Digital reconstruction filter 2. Signal windowing. To prevent image components from appearing in-band, the signal is multiplied by a window. The selected one was the Hanning type. 3. FFT calculation, to move into the frequency domain prior to the LS algorithm. 4. Frequency masking. The purpose of this operation is to eliminate all frequency components whose noise minimization is not required. This includes the dc, input signal 1 , and out-of-band bins (see Figure 4.5). Originally, it was intended to keep only the components inside the converter bandwidth. However, with this restriction, a sharp noise floor rise out of the cutoff frequency of 400 MHz was observed, and the output signal was visibly contaminated. Full-band noise cancellation was also considered, but achieving good performance over such a wide bandwidth proved difficult for the algorithm and the results were not as desired. A compromise was reached between both options, since the final spectrum selected after masking occupied half of the full range, up to fs/2=1.6GHz. All signals resulting from these processing operations will be referred to as Fs,i (Figure 4.4), where sis the stage number within the pipeline and iindicates a specific vector. The data coming from the back-end quantizer, vb [ n ]in Figure 4.4, does not undergo the same process, since it does not require any filter coefficients. It is used instead as a reference value for the LS algorithm. Therefore, it still needs to be converted to the same FFT domain. Operations 2 to 4 of the previous item list are applied to vb[n]to generate the vector Fref . 1 Since a Hanning window is used, the signal is composed by a total of three bins; five were removed for safety 28 4.1. MATLAB Model Overview Figure 4.4: Noise minimization algorithm block diagram 29 4. Continuous-Time Pipeline ADC: Architecture Design Exploration Figure 4.5: Frequency spectrum before (red) and after (blue) applying the frequency mask operation The LS algorithm for noise minimization can now be applied to the obtained data. Considering the notation given above, it could be expressed as: N1 X i=1 F1i·b1i+ N2 X i=1 F2i·b2i+ N3 X i=1 F3i·b3i+Fref = 0 (4.1) The different summations can be compacted into matrix form for simplicity. By defining F i = [Fi1Fi2...FiN ] and b i = [bi1bi2...biN ]T the equation can be rewritten as F1·b1+F2·b2+F3·b3+Fref = 0 (4.2) The terms of each stage are concatenated together, as in F b = [F1F2F3] and b= [b1b2b3]T, producing: Fb·b=−Fref (4.3) The expression above is the same as the one presented in [ 4 ]. Applying some algebra, the optimal value of the coefficients bis reached: b=−hRe(FH bFb)i−1 Re(FH bFref )(4.4) Where b is a vector containing the concatenation of the coefficients of stages 1 to 3, Fband Fref are as defined previously and FH bis the Hermitian transpose of Fb. 30 4.1. MATLAB Model Overview After this initial calculation step, the coefficients bare introduced in the digital noise cancellation filter and the reconstruction during normal pipeline operation can proceed. Foreground impulse response calibration The other method tested for digital reconstruction consists of a foreground calibration to find the coefficients of each of the stages based on their respective impulse responses. It is based on the strategy used in [ 19 ]. The main advantage it introduces when compared to the previous one is that it is possible to implement it on-chip. However, calibration is still required. A detailed explanation of its working principle is provided below. Recall the results of equation 3.1. The input can be reconstructed by a filter that processes each of the ADC outputs with the various residue-amplifying filter transfer functions. In this case, a similar but different approach is used to restore the signal. Consider the voltages Vi to be the output of the different quantizers and Vb the output of the back-end ADC. Transfer functions can be defined that relate the voltage of each node with the back-end as: Vb(s) Vi(s)=Hi(s)(4.5) With this expression, the output voltage of the back-end stage could be expressed as: Vb= N Y i=1 Gi(s)·X0− N X i=1 Hi(s)·Vi(4.6) Where X0 is the input to the pipeline, Gi ( s )is the transfer function of the residueamplifying filter in stage iand Vi , Vb and Hi ( s )are as defined for equation 4.5. It is, then, possible to develop a reconstruction mechanism if the transfer functions Hi ( s ) are known: Vb+ N X i=1 Hi(s)·Vi= N Y i=1 Gi(s)·X0(4.7) The result of this operation is the input signal X0 filtered by the totality of the stages. The reconstruction would be completed by dividing by the cumulative interstage dc gain. 1 QN i=1 Gi(0) · Vb+ N X i=1 Hi(s)·Vi!=1 QN i=1 Gi(0) · N Y i=1 Gi(s)·X0!(4.8) The implemented technique is based on obtaining a digital approximation of the transfer functions Hi ( s )[ 19 ]. Consider now the 3-stage + back-end CT pipeline from the model being discussed. If the input was left as an open circuit and an impulse was applied to the node V3, the output of the back-end would be: 31 Chapter 5 Continuous-Time Pipeline ADC: Architecture Optimization Results In the last chapter, the main work of this project was presented, consisting in the exploration, analysis and modeling of various blocks and effects that appear in continuous-time pipeline ADCs. The task will end with several simulations performed with the developed models. The results and conclusions reached from these tests make up the content of this chapter. 5.1 Parameter optimization Once the model was constructed, the next step was to select the optimal combination of parameters that define the architecture. Over several simulations, different values were tested, and a final decision was made based on the performance results. For a given sub-ADC-DAC architecture, the two main parameters that must be optimized are the sub-stage quantizer resolution and interstage gain. As was first mentioned in Chapters 2and 3, it should be the goal of the designer to maximize the gain between stages, since the input-referred noise level depends on this variable. However, this gain cannot be arbitrarily large, as that will provoke saturation at the input of the quantizers. According to these guidelines, the parameter optimization process undertaken goes through the following steps. First, a resolution combination for each substage is selected from the range of suitable realistic values. The architecture is then simulated. By observing the intermediate waveforms, a gain for each pipeline stage is chosen. A rule of thumb was given in previous chapters, which consists in choosing a value that guarantees that the output swing of each filter is within half of the next quantizer dynamic range. To evaluate the performance of ADC systems, several figures of merit (FoM), such as the Schreier FoM [ 23 ], can be employed. However, these figures require the knowledge of the converter power consumption for their calculation. This information 39 5. Continuous-Time Pipeline ADC: Architecture Optimization Results N◦of levels Stage gain Stage 1 Stage 2 Stage 3 Stage 4 G1 G2 G3 SNDR 7 7 7 63 3 6 2 71.6 7 7 7 127 3 6 2 74.1 7 15 15 63 3 8 5 74.3 7 15 15 127 3 8 5 74.6 15 15 15 31 5 8 5 77.4 15 15 15 63 5 8 5 79.9 15 15 15 127 5 8 5 80.6 15 31 31 31 6 11 8 80.7 15 31 31 63 6 11 8 80.9 15 31 31 127 6 11 8 81.0 Table 5.1: Parameter optimization for the flash sub-ADC version of the CT Pipeline. is simply not available due to the limited model being used. Therefore, the signalto-noise and distortion ratio (SNDR) will instead be assessed for architectural comparison. This procedure was first applied to the version of the model that uses flash ADCs in all substages. The results are shown in Table 5.1. The maximum number of bits for a flash quantizer was chosen to be 7 [ 23 ]. As can be seen from the results, increasing the sub-quantizers resolution past 4 bits does provide diminishing returns. Therefore, the architecture using 4-bit substage flash ADCs, a 7-bit back-end quantizer, and interstage gains of 5, 8 and 5, respectively, was deemed as the optimal solution. An equivalent method was used for the architecture using a flash ADC on the first stage and a VCO quantizer on the rest of them. The same solution (4-bit substages and 7-bit back-end) appeared as the preferred candidate. These parameter combinations are the ones selected for the rest of simulation results in this chapter. 5.2 Digital signal reconstruction filter The two implemented digital signal reconstruction alternatives will be compared in this section. To briefly summarize each of the advantages already discussed (Section 4.1.2), recall that the impulse calibration method can be supported on-chip, whereas the LS noise cancelation technique is more computationally demanding and necessitates off-chip implementation. However, the latter can offer better control over the frequency spectrum since it operates directly over it. Both alternatives require foreground calibration. The output frequency spectrum, as well as the noise performance parameters, for both techniques and both flash and VCO quantizer versions are shown in Figure 5.1 and Figure 5.2, for an input frequency of fin =BW/5 = 80MHz. The results were as expected. The noise cancelation filter can offer a lower noise floor over the frequency spectrum. This characteristic also translates to a considerable 40 5.2. Digital signal reconstruction filter Figure 5.1: Output frequency spectrum for flash quantizer version, impulse calibration (left) vs noise cancellation (right) reconstruction techniques Figure 5.2: Output frequency spectrum for VCO quantizer version, impulse calibration (left) vs noise cancellation (right) reconstruction techniques improvement over the SNR, SNDR and ENOB figures. The VCO quantizers are also able to outperform the flash ADCs. Another major difference is the number of taps needed for the filters. Recall that the impulse calibration technique aims to obtain an FIR approximation of an IIR response. As such, the selected number of taps directly affects the quality of this estimation. For the previous simulation results, 32, 28 and 26 taps were used for stages 1 to 3, respectively. The noise cancelation filter can obtain a similar or better response with a much more compact FIR stage. Figure 5.3 and Figure 5.4 show the performance achievable with both filter versions given a total number of taps for the reconstruction filter stages. It is evident that the noise cancelation technique can achieve similar performance with 20 or 30 less taps. The filter choice will then considerably impact the power consumption of 41 5. Continuous-Time Pipeline ADC: Architecture Optimization Results Figure 5.3: SNDR vs number of taps for flash quantizer version, impulse calibration vs noise cancellation reconstruction techniques Figure 5.4: SNDR vs number of taps for VCO quantizer version, impulse calibration vs noise cancellation reconstruction techniques 42 5.3. Signal Transfer Function the pipeline architecture. By the considerations above, it might seem as if the noise cancelation filter provides an overall performance improvement over the impulse-calibration method. However, a comparison of the STFs of both filters in the next section might suggest the opposite. 5.3 Signal Transfer Function The simulation results previously shown display the output performance for a specific frequency input (in particular, fin = 80 MHz ). However, it is necessary to evaluate the behavior over the full frequency band. The signal transfer function (STF) is the preferred method to assess this. As explained in Section 3.1.4, the ideal STF of a continuous-time pipeline ADC is the product of the transfer function of all residue-amplifying filter stages. In this case, a unity gain up to 400 MHz and a sixth-order roll-off afterwards would be expected. In order to achieve this, using a standard second-order filter with the desired cutoff frequency per stage is not enough, and careful consideration has to be given to the selection of the quality factor of the transfer function. The plot in Figure 5.5 shows the STF for different filter design approaches. First, an ideal sixth-order Butterworth is shown, to have a reference to compare to. Next, each of the filter stages has been built using the same standard second-order Butterworth response ( butter() function in Matlab) with a cutoff frequency of 400 MHz. Lastly, an alternative is displayed that implements different filter transfer functions with specifically selected quality factors (values in Section 4.1.3) and a filter cutoff frequency of 440 MHz. As can be observed, signal tones at 400 MHz will suffer a severe dB attenuation without the proper filter design. The next comparison shows the difference between the STF when using flashand VCO-based quantizers. As has been stated, VCO-based quantizers have a unity gain STF but a first-order NTF for quantization noise, which is shaped at the output. These dynamics can be appreciated at higher frequencies and are shown in Figure 5.6. The last comment is devoted to the digital signal reconstruction filter. All of the above STF plots have been obtained by using the impulse calibration method. When switching to the noise cancellation coefficients, the response is as in Figure 5.7 As can be observed, it is far from ideal and the filter will not achieve unity gain over the desired application bandwidth nor sixth-order attenuation of out-ofband components. The reason behind this is that the LS algorithm does not have information about the BW, only on the frequency mask. As revealed in Section 4.1.2, in-band or full-band masking did not provide the required noise performance. The hybrid approach of masking until f = 1 . 6 GHz obtains a remarkable SNDR, but cannot achieve a unity gain across the entire band. 43 5. Continuous-Time Pipeline ADC: Architecture Optimization Results Figure 5.5: Comparison of STF: ideal, same filter per stage design, different filter with specific Q design Figure 5.6: Comparison of STF: Flash vs VCO quantizers 44 5.4. Non-idealities Figure 5.7: STF with different reconstruction filter implementations 5.4 Non-idealities The effects of the non-idealities described in Section 4.2 on the performance of the ADC have been checked by several simulations. The results aim to set limits to the maximum tolerable errors that the converter can withstand. 5.4.1 DAC mismatch The modeling techniques for the different errors induced by the first DAC mismatch were elaborated in Section 4.2.1. In summary, static, delay, rise and fall times are added as a percentage of random variation following Equation 4.12. A Monte Carlo simulation in Cadence Virtuoso is performed where, for a specified standard deviation of the error, various randomized iterations evaluate the performance of the converter. The graphs in Figure 5.8 demonstrate the CT-pipeline SNDR for various levels of standard deviation of the static, delay, and rise and fall time variables. The Monte Carlo simulation was performed on 200 random iterations. In the plot, the mean SNDR value obtained for each deviation is marked with a dot symbol. The ± 3 σ variations are also displayed. It is not straightforward to define a tolerance boundary for each of these errors. In the physical implementation of the converter, these are mainly subject to process variations that are technology dependent. It is clear, for example, that a mismatch 45 5. Continuous-Time Pipeline ADC: Architecture Optimization Results Figure 5.8: DAC Mismatch static, delay, rise and fall time errors between unit elements causing static differences in the voltage level can have a detrimental effect on the converter performance. In these cases, the design of calibration and error compensation techniques [ 18 ][ 27 ] appears to be mandatory to achieve the SNDR required by the application. 5.4.2 Clock jitter The effect of clock jitter on the first DAC has also been tested. The details of how it has been introduced into the Simulink model were discussed in Section 4.2.2. The simulation carried out evaluates the SNR for different levels of clock jitter over three separate input frequencies. It used the flash quantizers and the impulse calibration reconstruction version of the model. In Figure 5.9, the jitter is specified with its root mean square (RMS) value in picoseconds. Note from the graph that, for the desired bandwidth of 400 MHz, a jitterrms = 0 . 1 ps would already set a limit SNRMAX = 75 dB . Even a low jitter level could hamper the performance figures of the converter. It is evident that high-speed ADCs must address this difficulty. Some discussion in this regard can be found in [3]. 5.4.3 Filter Nonlinearity With respect to the third-order nonlinearity expected from the residue-amplifying filter, it has been modeled following Equation 4.15. The simulation results are shown in Figure 5.10. The results do not seem as restrictive as for the other studied non-idealities. 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