Analysis and design of the second order delay-lock loop in a CDMA system

ANALYSIS AND DESIGN OF THE SECOND ORDER DELAY-LOCK LOOP IN A CDMA SYSTEM J.J.Olmas, R.Agus Dep . de Teo ia del Senyal i Comunicacions Uni e si a Poli hica de Ca alunya ( pc) A@. 30.002, OSOSO Ba celona, SPAIN ABSTRACT In CDMA sys ems a DLL is used o keep a ine alignmen be ween sequences. The di e en ial equa ion o an incohe en second-o de DLL has been p og ammed. By nume ical simula ion we ha e ob ained he Mean *e o Lose Lock o he DLL as a unc ion o he signal o noise a io in he da a bandwid h. This esul is impo an in a mobile en i onmen whe e a deep ading may esul in a p ac ically ins an aneous loss o lock. INTRODUCTION CDMA sys ems equi e synch oniza ion be ween he ecei ed sequence and he locally gene a ed sequence. Once he coa se alignmen o he codes has been achie ed, he ecei ed code phase has o be acked in o de o compensa e o he dopple e ec and (o ) clock a e misma ch. This is done by means o a Delay-Luck Loop (DLL). Second o de DLL's a e able o ack a equency e o wi hou a cons an phase e o . This capabili y is impo an in CDMA mobile communica ions, whe e a i s o de DLL would easily lose lock, [l]. The di e en ial equa ion o an incohe en second- o de DLL has been p og ammed. The p og am allows us o ob ain he maximum equency o se ha he DLL can abso b in e ms o he na u al equency o he loop. Knowing his we design he op imum loop il e . We ha e ound a o mula ha gi es he minimum achie able iming ji e in e ms o he signal o noise a io, he p oduc o he VCO equency s abili y imes he sys em p ocessing gain and he ime o se be ween he ea ly and la e codes in he DLL. The Mean Time o Lose Lock (MTLL) o he DLL is a e y impo au design pa ame e . By nume ical simula ion we ha e ob ained his pa ame e as a unc ion o he iming ji e . Fu he mo e, an exponen ial eg ession o mula has been ob ained om he sample poin s in o de o easily p edic he MTLL. Combining his o mula wi h he o mula o he ji e we a e able o plo he MTLL as a unc ion o he signal o noise a io in he da a bandwid h. This esul is again impo an in a mobile en i onmen whe e a deep ading may esul in a p ac ically ins an aneous loss o lock. DLL DESCRIPTION The block diag am o an incohe en DLL is shown in igu e 1. b BPSK signal F3gu e 1: Block diag am o an incohe en DLL whe e a( ) is he msmi ed PN sequence, b( ) is he da a sequence and oo and 8 a e, espec i ely, he ca ie pulsa ion and phase. a( ) akes on alues om he se 221 0-7803-0673-2192 $3.00 1992 IEEE {*I) each T, seumds (chip pe iod), and b( ) akes on alw om he se {*I) each T d (bi pe iod), whe eT,T,. Pis he~i sd~ig~lpowe md~is lse p opaga ion delay o which he DLL mus lock. n( ) is whi e gaussian noise wi h spec al densi y G, l =Nd2. In igu e 1, 26 is he o & be ween he ea ly and la e codes, and hebandwid ho heband-p~~ il e s, B=l/T allows he il e ing o he da a signal wi hou dis o ion. The beha io o he DU can be &sc ibed by a di e en ial equa ion, [2]: de- 1 d -- - - -KP l ) * ( s(e,;S) +N(z) ) a? T, d (2) In (2), en(s-+)/Tc is he &i ? be ween he Id and he ecei ed sequence in chips, ds/& is he ini ial clock equency o se , K is he VCO ums an , ( ) is he low- pass il e impulse esponse, S(e,b) is he .S"-cum and N( ) is noise wi h spec al densi y nea he o igin gi en by, PI: Y whe e y=P/N,-,B is he signal o noise a io in he da a bandwid h, and 1-26, (0S;SSO.S) g(b)= ( 0, (6>0.5) The loop W-cu e is shown in igu e 2. I can be shown ha i s slope a he o igin is 4(I-6). The second o de DLL pa ame e s: na u al equency, damping ac o and equi alen noise bandwid h axe, espec i ely: whe e s1 and s2 a e he ime cons an s o he i s o de ac i e loop il e . Using he bea model, which is alid o le1 -0, is easy o show ha he esidual ji e in e is 222 1.5 1 9.5 E -9.5 -1 -1.5 -2 -1.5 -I -8.5 E 8.5 1 1.5 2 E 2: "S" cu e o 6=0.25,0.50 and 0.75. gi en by: SIMULATION DESCRIPTION Assuming ac i e i s -o de loop il e , wi h a ans e unc ion gi en by: 0 1 72 F(s)= -+- S i 71 he di e en ial equa ion (2) can be w i en as: ( )= S( ( ),b) +N(Z) In o de o simula e by compu e equa ion (8), we can en isage a ecu si e me hod o upda e e e e y To seconds, whe e To is an a bi a y ime in e al much sho e hau Bil. So, he main loop in he simula ion p og am is equi alen o To seconds o eal ime. The ecu si e equa ion is: c(R+l)= (k) +To+ -- whe e k is he p esen upda e ins an and i is he clock equency o se . SIMULATION RESULTS To check he alidi y o ou p og am we ha e i s ob ained he simula ed DLL beha io du ing he acquisi ion p ocess. Fo example, aking =O. 7071, 6=0.5 and y=IOOdB, igu e 3 shows some ajec o ies o he alignmen e o and i s de i a i e in he phase plane. Fw e 3: DLL acquisi ion in he phase plane Simila plo s ha e been ob ained o di e en alues o 6. F om hese esul s we can s a e ha in he p esence o an ini ial clock equency o se i and in a noiseless si ua ion, he lock-in o he DLL is no gua an eed unless i/o,<26. This is qui e exac o 6<0.5 and somewha pessimis ic o 6>0.5. As he ini ial clock equency o se is mainly due o he VCO, we ha e ha wi h an ac i e loop il e and =O. 7071 he e is a lowe bound o he noise bandwid h o he loop gi en by: 0.53 *A cO*Rc= 0.53 *A co*B-PG (10) BL 1 26 26 whe e A co is he VCO s abili y and Rc=Ti' is he sequence chip a e. No ice ha R, can be exp essed as B imes he sys em p ocessing gain (PG). Now, aking (10) wi h equali y and subs i u ing BL/B in (6) we ge he exp essions o he minimum ji e . I 0.53 ; 7 PG [I+&] (6lO.5) 7 -+-I 1 1 (0.5 < 6 < 1) 26 4~6(1-6)~ (11) whe e X(O,6) and I-?@) ha e been e alua ed acco ding o (4). Exp ession (11) gi es he minimum achie able ji e unless some special ac ion is aken o educe he loop bandwid h once he DLL is locked. We ha e no conside ed his possibili y. Figu e 4 shows he ji e as a unc ion o y o di e en alues o 6 and o A co.PG=IU3. Dashed cu es a e o 6<0.5 and con inuous line means 620.5. The s ep in 6 is 0.05. 1.1 I 0.9 0.8 0.7 5 0.6 0.5 0.4 0.3 0.2 0.1 0 .A -7 -15 -I4 -13 -12 -11 -10 -9 -8 -7 d -5 I (dB) Fm 4: Ji e (in chips) o A co.PG= la3 As he loop "S"-cu e is no pe iodic, due o he p esence o noise he DLL will soone o la e lose lock. The Mean Time o Lose o Lock (MTLL) is a e y impo an design pa ame e . We ha e ob ained his magni ude, o he second o de DLL, by compu e simula ion. To ob ain he MTLL we un he p og am un il I E I lies ou side o he ange o alues o which he "S"cu e is no ze o. This is conside ed as an ou -o - lock condi ion and hen E is ese o ze o and he p og am is s a ed again. When 100 ou -o -lock si ua ions ha e been coun ed, he MTLL is app oxima ed by he o al p ocessed ime (in e ms o Bi') di ided by 100. Taking A co.PG=IU3 we need BL/B=5.3.104 ( o 6=0.5) o BL/B=3.533.104 ( o 6=0.75) in o de o gua an ee he lock o he DLL. Assuming hese da a in igu e 5 we plo he loga i hm o he ob ained MTLL (in e ms o Bi') e sus he ji e . The squa e and he iangle ma ks a e he poin s ob ained by simula ion. The CUNM p esen ed co espond o an exponen ial eg ession ha i s qui e well o he simula ion poin s. The eg ession equa ions a e: I 223 1 6 5 A' 53 d I- I- m 02 I d 9 -I 9.1 6.2 8.3 6.4 6.5 8.6 8.7 8.8 9.9 ji e Now, as BLD is known, combining (12) wi h he exp essions o he ji e (ll), we can plo he loga i hm o he kITLLu as a mc ion o 7. Figu e 6 shows bed ~ ob .io6d. In ip6 i csnbeno iced ha he h4TL.L is e y d i e o he signal o noim a io, since a chge o one dB is s d icigl o ha e he MTU di ided by ea. Ano he conclusion ha can be de i ed om igu e 6 is ha he DLL wi h b=0.75 has a be#e pe o maace ha he DLL wi h 8=0.5 only o y>-ladB. Thie is cluc o he c ha , al hough o he 8ullc ji e he DLL wi h 6-0.75 has highe MTU han he DLL wi h 6=0.5, o he 8pme signal o mise a io i also has a highe midud ji e . The xmsidemd alue o 4 m-~=1u3 may co mpod, o example, o a p ocessing gpin. sys em wi h m co s abili y o IUS and 2aiB o CONCLUSIONS p&lu~ 5: MTLJ-, in e ms o 4". U a unc ion o he ji e 19 : : : : : : : : : ......... ......... A simula ion p og am o he second o de DLL has been de eloped. The p og am allows an op imum design o he loop low-pass M e in o de o -& he igh clock equency acquisi ion and minimum esidual ji e . The MTLL o he DLL bas also been ob ained by compu e simula ion o wo di e en shi s be ween ea ly and la e codes. Resul s show a ema kable b i i y o he signal o noise a io in he da s bandwid h. ......... ......... d ......... ........ :, :::::::::I ......... , ACKNOWLEDGMENT ..... ..... This wo k has been suppo ed by ALCATEL .... .... .... .... SESA. REFERENCES [l] R.KARMY, B.Z.BOBROVSKY, Z.SCHUSS, "Loss o Lock Induced by Dopple o Code Ra e Misma ch in Code T acking Loops", MILCOM 1987. ......... ......... 3 .'.l*l*l*l.l*l.l '* -IS -I4 -13 -12 -11 -16 -9 -7 -6 5 7 (dB) p U e 6: MTLL, in e ms o E', as a unc ion o he signal o noise N iO iog( LBj - 9.34 (1.27 10-~)~* (b=O.5) iog( LBj= ii.m-(8.11 10-~p (64.75) (12) 224 [2] A.POLYDOROS, C.L.WEBER, "Analysis and Op imiza ion o Co ela i e Code-T acking Loops in Sp ead-Spec um Sys ems", IEEE T ans. on COIUIXI. Vol COM-33, NO.l, 1985.