EV hybrid battery with integrated multilevel neutral-point-clamped interfacing and lossless intermodule state-of-charge balancing

Received 19 November 2024; revised 23 December 2024; accepted 26 December 2024. Date of publication 3 January 2025; date of current version 17 January 2025. The review of this article was arranged by Associate Editor Hani Vahedi. Digital Object Identifier 10.1109/OJIES.2024.3525262 EV Hybrid Battery With Integrated Multilevel Neutral-Point-Clamped Interfacing and Lossless Intermodule State-of-Charge Balancing GABRIEL GARCIA-ROJAS 1(Graduate Student Member, IEEE), SERGIO BUSQUETS-MONGE 1(Senior Member, IEEE), ÀLBER FILBÀ-MARTÍNEZ 2, TUREV SARIKURT 3, SALVADOR ALEPUZ 4(Senior Member, IEEE), AND JOSEP BORDONAU 1(Member, IEEE) 1Department of Electronic Engineering, Universitat Politècnica de Catalunya, 08028 Barcelona, Spain 2Catalonia Energy Research Institute, 08930 Sant Adrià del Besòs, Spain 3Rail Transport Technologies Institute, Scientific and Technological Research Council of Türkiye, 41400 Kocaeli, Türkiye 4TecnoCampus Mataró-Maresme, Universitat Pompeu Fabra, 08302 Mataró, Spain CORRESPONDING AUTHOR: GABRIEL GARCIA-ROJAS (e-mail: [email protected]). This work was supported by European Union’s Horizon 2020 research and innovation program under Grant 963646. ABSTRACT The battery is at the heart of the electric vehicle and determines many of its key performance features. Therefore, an optimized design of the battery is critical. On the one hand, the design of batteries based on a single battery cell leads in many cases to oversized batteries in terms of energy or power, due to the diversity of requirements of the different electric vehicles. On the other hand, the use of a custom cell for each vehicle, optimized for its particular requirements, is not economically viable. Instead, hybrid batteries, combining only two battery cell chemistries, with distinct particular strengths, such as high specific energy or high specific power, offer an opportunity to cover a wide range of vehicle battery specifications while avoiding oversizing and dispersion in the cells to be employed. This work introduces a novel hybrid battery configuration, where the interfacing between the two sets of cells is accomplished through a bidirectional multilevel neutral-point-clamped dc–dc converter. The novel topology is presented, and a suitable power converter modulation and control strategy is developed. The feasibility and benefits of such configuration are demonstrated and illustrated. Particularly, the proposed battery system allows the balancing of the State-of-Charge (SoC) of the battery modules within both the sets of battery banks, which is achieved without introducing additional power losses. The SoC balancing is simply accomplished through the regulation of the power to be extracted/delivered from/to each battery module by the power converter during regular battery discharging and charging operations. The converter features enough regulation margin to correct substantial SoC imbalances. Overall, the proposed approach enables a modular and scalable design of the energy storage system for a wide range of electric vehicles, from only two different standard battery modules and a standard power semiconductor device, while optimizing the battery size for any given battery power and energy specification. Simulation and experimental results are provided in the case of a three-level internal battery interfacing to verify the good performance of the proposed novel hybrid battery configuration, modulation, and control. INDEX TERMS Hybrid battery, modulation, multilevel, neutral point clamped (NPC), State-of-Charge (SoC) balancing. © 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 130 VOLUME 6, 2025 NOMENCLATURE Cbk Tank dc-blocking capacitor value. E∗ bat Energy requirement for the battery. fsSwitching frequency. i2a Current flowing through the dc-link node 2 of side A. I2a Average current flowing through the dclink node 2 of side A. iA1,iA2 Currents flowing through the battery modules A1 and A2 and their parallel capacitors, respectively. IA1,IA2 Average currents flowing through the battery modules A1, A2 and their parallel capacitors, respectively. iTTank current. ITRMS value of the tank current. iT,1Fundamental component of the tank current. ip T,1In-phase and component of iT,1. iq T,1In-quadrature component of iT,1 . ka,kbControl effort of the state-of-charge closed-loop control of sides A and B, respectively. LTTank inductance. ma,mbModulation index of sides A and B, respectively. na,nbNumber of levels of sides A and B, respectively. Pa,PbActive power delivered by sides A and B, respectively. P∗ bat Power requirement for the battery. Qa,QbReactive power delivered by sides A and B, respectively. q(t) Stored battery module charge at time t. Qnom Nominal battery module capacity. RLLoad resistance. RTTank resistance. sa,sbNPC leg connection state of sides A and B, respectively. spa,spbSign of the active power delivered by sides A and B, respectively. sqa,sqbSign of the reactive power delivered by sides A and B, respectively. scA1,scA2 State of charge of battery modules A1 and A2, respectively. scB1,scB2 State of charge of battery modules B1 and B2, respectively. scimbA,scimbBState of charge imbalance of sides A and B, respectively. scimbA∗,scimbB∗Command for the state of charge imbalance of sides A and B, respectively. va,vbSynthetized instantaneous output voltage of sides A and B, respectively. Va,VbRMS value of the fundamental component of vaand vb, respectively. VA1,VA2 A1 and A2 battery module voltages, respectively. Vdca,Vdcb Total dc voltage of sides A and B, respectively. vTTank circuit voltage. αjModulation pattern switching angles, where j=a, b, c, d. βPhase shift of the fundamental component of the current flowing through the tank, IT, 1, with respect to the fundamental output voltage of side B. θa,θ bModulation angle of sides A and B, respectively. ϕPhase shift of the fundamental output voltage of side A, with respect to the fundamental output voltage of side B. I. INTRODUCTION Electric vehicles (EVs) are already playing an essential role in the transition toward a low-carbon global economy. Supported by the various initiatives of countries and institutions [1],[2], it is anticipated that the number of EVs will continue to grow in the coming years. Similar to internal combustion engine vehicles, there is a wide variety of EVs, ranging from small commuter cars to heavy-duty commercial vehicles. These EVs can greatly differ in their battery requirements, including energy, power [3], charging time [4], regenerative braking capacity, cost, and lifespan. In addition, these EV battery requirements must be met under different operating conditions, such as varying States of Charge (SoCs) and extreme temperatures. Since it is not viable to build the battery for each vehicle around an optimal battery cell designed specifically for this vehicle, the EV battery pack designs based on a single standard battery cell end up often being oversized in some aspects [5],[6]. Instead, a hybrid battery energy storage system (HBESS) is built from a combination of two types of battery cells, each one featuring different chemistries, with the intention of finding a more optimal solution. Each battery cell technology features a particular strength, such as high specific energy (SE) or high specific power (SP), and the hybrid battery takes advantage of this combination of strengths to meet all the system requirements with less battery volume and weight, and extending battery life. This is illustrated in the following through a simple example. Let us assume that in the design of a battery, SE and SP are of utmost importance. Let us also assume that only two cell types are available, depicted in Fig. 1. Cell type A is optimized to store energy and in contrast presents a moderate SP. Cell type B is optimized to provide power but presents a moderate SE. Fig. 2illustrates the energy (E) and power (P) achieved with 1 kg of each cell. Thus, the lengths of the blue and red lines, which are in this example approximately equal, correspond to 1 kg of each cell type. When a high-energy low-power VOLUME 6, 2025 131 GARCIA-ROJAS ET AL.: EV HYBRID BATTERY WITH INTEGRATED MULTILEVEL NPC INTERFACING AND LOSSLESS SOC BALANCING FIGURE 1. Characteristics of cells A and B. FIGURE 2. Power and energy of 1 kg of cells A and B. battery is to be designed, with the requirements depicted by point 1in Fig. 3(a), where E∗ bat represents the minimum required battery energy and P∗ bat represents the minimum required battery power, then it will be optimal to use cell type A. As can be observed in Fig. 3(a), using cell type A leads to a lower battery weight, since the blue line is shorter than the red line. Conversely, when a high-power low-energy battery is to be designed, with the requirements depicted by point 2in Fig. 3(b), the optimal cell to use will be cell B, as shown in Fig. 3(b). However, when a battery with a more balanced energy and power requirements is needed, such as the one represented by point 3in Fig. 3(c), both cell types, if used alone, lead to a heavy battery, as depicted in Fig. 3(c). In this case, instead, a combination of both cells allows fulfilling the battery requirements with a much lower overall weight, as shown in Fig. 3(d). Therefore, hybrid batteries offer the possibility of obtaining batteries with different ratios of energy and power in an optimal way. From a different perspective, hybridization is equivalent to employing a virtual cell with characteristics at any selected intermediate point along the straight line joining cells A and B in Fig. 1. Some examples in the literature propose the hybridization of different energy storage systems at cell level [7] and at system level [6],[8],[9],[10]. From the architectural point of view, two options are considered: passive and active systems. Passive systems do not contain any power converter to interface the storage elements, thereby lowering the total system cost but imposing significant restrictions, such as cell voltage curve compatibility [11],[12]. Alternatively, in active systems, the inclusion of a power converter interface increases the degrees of freedom of the system. The interface of the storage elements has been reported to be implemented through a single two-level power converter [9],[13],[14],[15],[16],a converter for each element [3],[17],[18], a three-level threephase neutral-point-clamped (NPC) dc–ac converter [19],a cascaded H-bridge (CHB) converter [10],[20],[21],[22], [23], or other converters [24],[25],[26]. The use of multilevel converters fed by several battery modules allows controlling the current of each battery module as a function of its individual SoC, which maximizes the energy delivered by the full battery pack [23],[27]. Therefore, these converters are well suited for the interfacing in active hybrid battery systems. However, their application has not been fully explored outside the CHB-based HBESS [10],[20],[21],[22], [23], and the configuration of hybrid batteries using other multilevel topologies still requires further investigation. In order to cover this gap, this article, developed under the European Union’s Horizon 2020 Helios project [28], with a consortium of 18 partners, proposes a novel active hybrid battery configuration employing a novel NPC multilevel converter as the interface between the two battery banks, with one of the banks being directly connected to the load. Compared to the existing State-of-the-Art HBESS configurations, the proposed design leverages the advantages of NPC converter topologies, such as the potential for the highest power density among multilevel topologies and the reduced number of passive components. When the converter legs are implemented with the active NPC topology, all the semiconductor devices feature the same voltage rating [29]. Compared to HBESS topologies employing two-level converters, the proposed system features intermodule nondissipative SoC balancing capability. Compared to CHB-converter-based topologies, where each battery module must be isolated [10], the proposed HBESS configuration interconnects the battery modules in series. This point is particularly important in EV applications, where space constraints and high-power-density requirements tend to favor topologies with reduced isolation and clearance distances. Furthermore, the proposed circuit topology is simple and only requires two NPC legs, an inductor, and a capacitor, thereby facilitating its implementation and scalability employing standard battery modules and a standard semiconductor device. Finally, it is assumed that the battery bank that directly connects to the load employs high-power battery cells, while the other side utilizes high-energy battery cells. The power exchanged between both battery banks through the converter is limited by the high-energy low-power battery bank. Thus, the 132 VOLUME 6, 2025 FIGURE 3. Different battery designs meeting the battery energy and power specifications (E∗ bat and P∗ bat). (a) High-energy battery. (b) High-power battery. (c) Battery with balanced power and energy specification. (d) Hybrid battery with balanced power and energy specification. FIGURE 4. Proposed generalized HBESS topology with nalevels on battery side A and nblevels on battery side B. converter power rating is not required to be sized according to the total power of the HBESS. These characteristics make the implementation of active HBESS particularly relevant for the standardization of vehicle design and manufacturing, regardless of the battery cell technologies employed. As depicted in Fig. 1, the proposed approach, by using only two different battery cell chemistries, allows the conception of a virtual battery cell with intermediate performance, which can be easily customized with tailored power and range, and with relevant battery weight reduction. EVs are subjected to frequent strong accelerations and decelerations, requiring a significant amount of power during this transient operation. High-power battery cells handle this kind of load more efficiently than high-energy battery cells, generating less heat and providing a longer life cycle [30].Onthe other hand, high-energy battery cells can provide increased range more efficiently. The main contributions of this article are as follows: 1) the conception of the topology, basic operation, and power flow control of a novel n-level active HBESS topology; 2) the development of a battery intermodule SoC balance control through a modification of the converter modulation and without introducing additional losses; that is, the SoC balance itself presents a lossless operation; 3) the verification of the suitability of the proposed topology and control through simulation and experiments. The rest of this article is organized as follows. Section II proposes the NPC-based active HBESS topology and operating principle. Section III presents the proposed modulation and charge balancing control. Sections IV and Vpresent simulation and experimental results to verify the good performance of the aforementioned systems, respectively. Finally, Section VI concludes this article. II. PROPOSED HBESS TOPOLOGY AND OPERATING PRINCIPLE The proposed generalized HBESS topology is presented in Fig. 4. It is formed by two battery banks. Battery bank A consists of na−1 modules connected in series, and battery bank B consists of nb−1 modules connected in series, each one coupled with a parallel capacitor C. The load is directly fed from battery bank B, while battery bank A is connected to battery bank B through a power electronics interfacing consisting of two NPC legs and a tank circuit. The NPC legs are here modeled as single-pole multiple-throw switches, with nathrows on side A and nbthrows on side B. Fig. 5 VOLUME 6, 2025 133 GARCIA-ROJAS ET AL.: EV HYBRID BATTERY WITH INTEGRATED MULTILEVEL NPC INTERFACING AND LOSSLESS SOC BALANCING FIGURE 5. Some examples of NPC leg topologies. (a) Three-level diode-clamped topology. (b) Three-level active-clamped topology. (c) Three-levels T-type topology. FIGURE 6. Two possible hybrid battery pack configurations depending on the connection of the tank current return path. (a) Parallel. (b) Series. shows some possible implementations of such NPC legs for the particular case of three levels. The tank circuit consists of an inductor LTand a capacitor Cbk. The capacitor Cbk blocks the dc component of the tank voltage vT. Thus, only ac current flows through the tank in the steady state. The return path for the tank current iTis indicated by the ground symbols on the middle dc-link point in both the battery banks, as shown in Fig. 4. However, notice that the return path can be connected to any dc-link point on both the sides, and these two dc-link points can differ. The location of these points only affects the value of the dc voltage on Cbk. This feature enables different hybrid battery pack configuration options, as those illustrated in Fig. 6.Figs.4and 6(a) correspond to the parallel configuration, where the return path would be typically connected to an analogous dc-link point on both the sides. Instead, Fig. 6(b) corresponds to a series connection, where the return path is connected to the bottom dc-link point in side A and to the top dc-link point in battery bank B. This last configuration provides higher load voltage. The discussion about the merits of each configuration is beyond the scope of this article. This work is developed with the parallel configuration of Figs. 4 and 6(a). The power flow between sides A and B is controlled by means of the voltages vaand vbgenerated by the NPC FIGURE 7. Phasor diagram illustrating the system operating principle. legs, with fundamental components of rms value Vaand Vb, respectively, phase shifted by ϕdegrees. The corresponding phasors are represented in Fig. 7. The tank rms voltage VT, computed as the difference between Vaand Vb, is essentially applied over the inductor impedance, generating the tank current with rms value ITand phase β. The synthesized voltages and the tank current define the active and reactive power exchanged between A and B. The 134 VOLUME 6, 2025 FIGURE 8. Normalized active and reactive power as a function of ϕ,forVa =Vb. active power transferred from A to B is Pa=−Pb=Va·IT·cos (β−ϕ)=Va·Vb·sin (ϕ) ωL(1) while the reactive power delivered from side A can be computed as Qa=Va·IT·sin (β−ϕ)=V2 a−VaVb·cos (ϕ) ωL(2) and the reactive power from side B can be expressed as Qb=−Vb·IT·sin (β)=−V2 b−VbVa·cos (ϕ) ωL.(3) The reactive power represents the energy that flows back and forth between the batteries and the tank without net energy transfer. Fig. 8shows the normalized active and reactive power as a function of ϕ, for the particular case Va=Vb. For a given amplitude Vaand Vb, the active power can be regulated adjusting the phase shift ϕbetween −π/2 and π/2. Pure reactive power with no active power can be exchanged if VaࣔVband ϕ=0, or if ϕ=π. The active power flow discussed in this section is illustrated in Fig. 9for the particular case of three levels on both the battery sides. The multilevel dc–dc converter extracts active power PA1 and PA2 from the side-A battery modules and delivers the aggregated power Pa=PA1 +PA2 to the side B: PX1 toward module B1 and PX2 toward module B2. Finally, a load consuming PLis fed from the side-B battery bank. In particular, Fig. 9illustrates the case where PA1 =PA2 =PX1 =PX2 =PL/4, which corresponds to an operating mode under balanced contribution of power to the load from each battery bank and balanced SoC conditions. In general, with the proposed operation principle, the system can adjust the amount of energy transferred from side-A battery bank to side B. FIGURE 9. Power flow across an HBESS with two battery modules on each side (na=nb=3) feeding a load, under balanced contribution of power to the load from each battery bank and balanced SoC conditions. The operation of the NPC legs demands high-frequency pulsating currents on the battery–capacitor pairs. The purpose of the parallel capacitors is to provide a low-impedance path for these high-frequency components, so that the battery modules supply only the dc component. However, there is a design tradeoff in the selection of this capacitance. A minimum capacitance value is necessary to provide the converter leg commutation currents through a path with a low leakage inductance. As the capacitance is increased above this minimum value, the high-frequency current ripple through the battery modules is reduced, at the expense of increasing the capacitor size. Given this, to select a suitable design tradeoff solution, it is important to assess the potential negative impact of a high-frequency current ripple on a battery module. First, this current ripple contributes to increase the battery rms current for a given power delivery, leading to an increase in the battery losses due to the Joule effect, which in turn raises the cell temperature and accelerates aging [31],[32]. According to this, several studies have proposed alternatives to minimize the battery rms current on multilevel topologies [33],[34]. However, experimental studies have found no evidence to demonstrate a measurable increase in aging caused by the high-frequency current ripple on different cell chemistries. Uno and Tanaka [35] found no significant difference in aging of LiNiCoO2/graphite cells when exposed to high-frequency sinusoidal currents, and only lower frequencies caused accelerated aging. Brand et al. [36] reported analogous findings on NiMnCoO2/graphite cells. More recently, Ghassemi et al. [37] have also concluded that high-frequency ac currents superimposed on a dc offset do not contribute to ageing on LiFePO4cells. One explanation for this phenomenon may be that the high-frequency currents flow through the double-layer capacitance of the cells, similar in structure and behavior to a supercapacitor, preventing any charge-transfer process, although they can cause a minor increase in temperature. Chang et al. [38] stated that the necessary condition for a current ripple to cause battery degradation is that it should feature low frequency and that it should cause the battery current to change direction. This thesis is further reinforced by VOLUME 6, 2025 135 GARCIA-ROJAS ET AL.: EV HYBRID BATTERY WITH INTEGRATED MULTILEVEL NPC INTERFACING AND LOSSLESS SOC BALANCING FIGURE 10. Example current profile of the battery A1 without parallel capacitor, under a three-level system (na=nb=3), ma=0.9, mb=0.9, and ϕ=45°. several studies showing increased aging when this condition is met [35],[39]. In addition, the cell temperature has to be significantly affected. When the cell temperature is tightly controlled, Bessman et al. [40] were not able to find any measurable difference in capacity fade or increase in internal resistance, in this case for LiNiMnCoO2/graphite cells. Fig. 10 shows an example profile of the A1 battery module current, iA1, in the absence of a parallel capacitor, during a discharge process of battery A1, for the system proposed in Fig. 4at three levels, side-A modulation index ma=0.9, side-B modulation index mb=0.9, and phase shift ϕ=45°. Under these operating conditions, the active power is much higher than the reactive power, and it can be observed that the current does not change direction at any instant of time. Furthermore, the current profile for any value of the modulation index and phase shift only contains high-frequency harmonics. The frequency spectrum is shown in Fig. 11.Even though the current may change direction when the system operates with large reactive values, the conditions reported in [38] are not met, and only a small increase in temperature is expected. In addition, the loss of total battery bank capacity due to different module aging (possibly generated by different temperature stress) can be significantly minimized thanks to an intermodule SoC balancing control [38]. During charging, the potential negative effects are even less concerning, as several authors have found that pulse charging can reduce ageing compared with constant current charging [37],[41],[42], [43],[44]. III. MODULATION AND SOC BALANCING CONTROL This section presents the NPC leg modulation and the battery intermodule SoC balancing. To help the reader understand the proposed operation, this work has been developed with the simplest case, using a three-level NPC leg on both the sides. However, it is important to highlight that the method described FIGURE 11. Frequency spectrum of the current delivered by battery A1 without a parallel capacitor, under a three-level system (na=nb=3), ma =0.9, mb=0.9, and ϕ=45°. here can be properly extended to any number of levels. Fig. 12 presents this simple case derived from the general topology, with two series-connected battery modules per side interfaced through a three-level converter, which is here implemented with the active NPC topology. Fig. 12 provides additional information necessary for the simulation and experimental sections that will be detailed in Sections IV and V. For the sake of simplicity, the analysis is carried out on side A in Fig. 12, although the analysis on side B is fully equivalent. Fig. 13 presents the voltage pattern vato be generated through the operation of the NPC leg. Typically, αa=αb=αc =αd=αto force quarter-wave symmetry, eliminating evenorder harmonics and providing waveform simplicity. In this case, the rms value of the fundamental component depends on αas follows: Va=√2Vdca π·sin (α)(4) where Vdca =VA1 +VA2 is the total side-A dc-link voltage. Likewise, the modulation index can then be defined as ma=Va Vdca/√6=2√3 π·sin (α)(5) where the modulation index varies from 0 to 2√3/π ≈1.1 for αvarying from 0 to π/2. Let us now analyze the effect of the NPC leg operation on the battery current balance. From Fig. 12, applying Kirchhoff current law at dc-link node 2, one has i2a −iT=iA1 −iA2 (6) where iAx(xࢠ{1, 2}) is the addition of the current that flows through the battery (iAx,bat) and the capacitor (iAx,cap). 136 VOLUME 6, 2025 FIGURE 12. HBESS circuit schematic with three levels on battery side A and three levels on battery side B (na=nb=3). Both the converter legs are implemented with the active NPC topology. Both the simulations and the hardware prototype follow this design. FIGURE 13. Three-level modulation pattern [45]. On average, over the switching cycle, one has I2a =IA1 −IA2 (7) which indicates that the average neutral-point current I2a is responsible for the imbalance of the two battery currents; that is, forcing I2a =0 keeps the two battery currents balanced. Fig. 13 includes the plot of the fundamental component of the tank current iT,1=ip T,1+iq T,1, decomposed into a component in phase with the fundamental component of va(ip T,1, responsible for the active power transfer) and a component in quadrature (iq T,1, responsible for the reactive power transfer). All the other harmonics of iTare neglected. In Fig. 13, with αa=αb=αc=αd=α, the blue and green solid areas, representing the charge drawn from (positive areas) or injected into (negative areas) the neutral point, cancel out in both ipT,1 and iqT,1. This results in I2a =0, and it means that both the battery modules feature the same current, ideal for a balanced charging and discharging of these two battery modules. However, it can be useful to introduce an imbalance in the battery currents. For instance, this imbalance can be applied to equalize the two battery modules SoCs when they are unequal. This can be done by modifying the width and/or position of the positive and negative pulses of vain correlation with ip T,1and/or iq T,1. An example is depicted in Fig. 14(a), where the width of the positive and negative pulses is reduced and increased, respectively. The green areas still cancel out in iq T,1, but they no longer cancel out in ip T,1, resulting in a positive average neutral-point current I2a >0 and imbalanced battery module currents IA1 >IA2. In Fig. 14(b), the position of the positive and negative pulses is moved right and left, respectively. The blue areas still cancel out in ip T,1, but they no longer cancel out in iq T,1, introducing an I2a >0 that will force IA1 >IA2. That is, the imbalance of the battery currents can be controlled through the tank current associated to the active and reactive power being transferred, by modifying the width and/or position of the positive and negative pulses of va. Fig. 15 shows a proper closed-loop control diagram based on this principle, where scimbA=scA1 −scA2 is the imbalance between the SoC of battery module 1 and battery module 2ofsideA,sc(t)=q(t)/Qnom,q(t) is the stored battery module charge at time t,Qnom is its nominal capacity, scimb∗ Ais the command for the SoC imbalance of side A, and sa(t)ࢠ{1,2,3} is a variable that indicates the dc-link point where the NPC leg is connected at each point in time. A proportional gain in the controller Gc(s) is sufficient for a successful system implementation. To determine sain the modulator block of Fig. 15,itis required to first determine the switching angles with αa=α·1+ka·(spa+sqa) αb=α·1+ka·(spa−sqa) αc=α·1+ka·(−spa−sqa) αd=α·1+ka·(−spa+sqa) (8) VOLUME 6, 2025 137 GARCIA-ROJAS ET AL.: EV HYBRID BATTERY WITH INTEGRATED MULTILEVEL NPC INTERFACING AND LOSSLESS SOC BALANCING FIGURE 14. Control action to correct imbalance. (a) Through the in-phase current component (active power). (b) Through the in-quadrature current component (reactive power). where αcan be obtained from (5),spais the sign of the active power delivered by side A (+1ifip T,1is as depicted in Fig. 13 and −1 if it is phase shifted by 180°), sqais the sign of the reactive power (+1ifiq T,1is as depicted in Fig. 13 and −1ifit is phase shifted by 180°), and kais the control effort variable. If it is desired to restrict the control action only to the active power, sqahas to be set to zero in (8). Alternatively, if it is desired to restrict the control action only to the reactive power, spahas to be set to zero in (8). The value of the control effort variable kamay need to be restricted to prevent the switching angles from going outside the feasible range [0, π/2]. Fig. 16 illustrates the power flow in the HBESS under this SoC balancing control in action. It is assumed that scimbA<0 and scimbB>0. The power delivered from side-A battery modules, PA1 and PA2, is unbalanced due to the control action on the converter side-A modulation. Similarly, the energy delivered from the converter to side-B battery modules, PX1 and PX2, is also unbalanced due to the control action on the converter side-B modulation. The SoCs of all the battery modules are regulated simply through the control of the individual power delivered/received by each battery module. It is very relevant to highlight that since the proposed charge balancing control does not introduce any additional commutations and since there is no charge transfer among modules of the same battery bank—all the charge transferred is directly delivered from one battery bank to the other—no additional losses are introduced due to this charge balancing control. Therefore, the system can balance each individual battery module SoC in a lossless manner. Fig. 17 illustrates this SoC lossless balancing control in comparison to the typical passive balancing control and active balancing controls. Two battery modules connected in series are considered (Bat1 and Bat2). Their charge/energy is represented by a solid bar. The energy of the two battery modules is initially unbalanced. In Fig. 17(a), a passive balancing circuit burns the excess energy of Bat1 to achieve SoC balance. This excess energy is, therefore, lost. In Fig. 17(b), an active balancing circuit delivers part of the excess energy of Bat1 to Bat2 to achieve SoC balance. However, the active balancing circuits incur in some losses. Therefore, part of the energy is lost in a power transfer exclusively undertaken to achieve SoC balance. Finally, in Fig. 17(c), the balancing is simply achieved by properly adjusting the power delivered by Bat1 and Bat2 to the load, or alternatively adjusting the power received by Bat1 and Bat2 from a source. This power transfer will obviously incur in some losses, but since the same overall power transfer has to be produced to power the load or to charge the battery bank, these losses would occur anyway and cannot be attributed to the SoC balancing process itself. Thus, this third balancing technique is regarded as being lossless. In addition, another advantage is that it does not require a specific balancing circuit. IV. SIMULATION RESULTS A switching model and a switching-cycle-averaged model of the system depicted in Fig. 12 have been implemented in MATLAB-Simulink to analyze the performance of the proposed HBESS system. For convenience and simplicity, the same battery module is used in sides A and B. The selected battery module model has been obtained from [27]. The converter legs are modeled as ideal single-pole multiple-throw switches. The load is modeled as a resistor with value RL. The system parameters and operating conditions presented in Tables 1and 2are the same for both the simulations and the experimental tests. The system operates with two battery modules and one three-level leg on each side (na=nb=3). For the sake of simplicity and due to symmetry, only side-A variables are reported. In the first test, the switching model is employed to verify the working principle in detail, as shown in Fig. 18 under open-loop control, i.e., forcing ka=0. Notice that kais the control effort variable of side A. The synthetized voltages vaand vbare phase shifted by 90°, leading to an operation 138 VOLUME 6, 2025