CMOS Current Feedback Operational Amplifier-Based Relaxation Generator for Capacity to Voltage Sensor Interface

sensors Article CMOS Current Feedback Operational Amplifier-Based Relaxation Generator for Capacity to Voltage Sensor Interface Ladislav Polak 1, Roman Sotner 1,* , Jiri Petrzela 1and Jan Jerabek 2 1Department of Radio Electronics, SIX Research Center, Brno University of Technology (BUT), Technicka 3082/12, 616 00 Brno, Czech Republic; [email protected].cz (L.P.); [email protected].cz (J.P.) 2Department of Telecommunications, SIX Research Center, Brno University of Technology (BUT), Technicka 3082/12, 616 00 Brno, Czech Republic; [email protected].cz *Correspondence: [email protected].cz; Tel.: +420-541-146-560 Received: 2 November 2018; Accepted: 16 December 2018; Published: 18 December 2018   Abstract: This paper presents a simple relaxation generator, suitable for a sensor interface, operating as a transducer of capacitance to frequency/period. The proposed circuit employs a current feedback operational amplifier, fabricated in I3T25 0.35 µ m ON Semiconductor CMOS process, and four passive elements including a grounded capacitor (the sensed parameter). It offers a low-impedance voltage output of the generated square wave. Additional frequency to DC voltage converter offers output information in the form of voltage. The experimental capacitance variation from 6.8 nF to 100 nF yields voltage change in the range from 21 mV to 106 mV with error below 5% and sensitivity 0.912 mV/nF evaluated over the full range of change. These values are in good agreement with simulation results obtained from the Mathcad model of frequency to DC voltage transducer passive circuit. Keywords: capacity sensor interface; capacity measurement; current feedback operational amplifier; relaxation generator; square wave generator 1. Introduction Electrical sensors form an important part of complex electronic systems, which are used in many fields (e.g., industry, healthcare, consumer electronics and wireless communications) [ 1 ]. They are required for transformation of various physical quantities to measurable information in the form of an electrical signal (voltage, current). Such physical quantities, for instance, can be temperature [ 2 ], mechanical pressure [ 3 ], acoustic pressure [ 4 , 5 ], electromagnetic field [ 6 , 7 ], humidity [ 8 ], gas [9,10] and biosignals [ 11 , 12 ]. Due to different operating conditions in the low-voltage (LV) design (e.g., supply voltage and requirement for the power consumption), specific methods and principles of the readout systems must be used. Especially, requirements regarding the LV supply cause restrictions for the implementation of standard methods that are focused on a direct application of quite high voltage levels. Capacitance sensors enable conversion of various physical changes, for instance, small distance and displacement variation [ 13 – 16 ] and water level detection [ 17 ], to measurable signals. Continuously operating analog interfaces for capacitance sensors use the following methods: (a) AC source-based measurements for sensing of voltage across unknown capacitance and current through unknown capacitance; (b) capacitance divider [ 18 ]; (c) resonance [ 18 , 19 ] and bridge circuits containing the measured capacitance [ 1 , 18 , 19 ]; (d) methods based on the transfer of charge (containing switches and their driving) [ 19 ]; (e) differential methods [ 13 – 16 ] ensuring high accuracy and linearity; and (f) methods based on the sensed capacity as a key part of signal generator [ 18 , 19 ] (sine wave oscillators and generators of other waveforms). Sensors 2018,18, 4488; doi:10.3390/s18124488 www.mdpi.com/journal/sensors Sensors 2018,18, 4488 2 of 15 The last method in the previous list can be suitable for LV supply cases, because the signal processing, in comparison with direct measurement of the capacity by applied DC/AC voltage or indirect measurements expecting high voltage levels [ 15 , 16 ], does not depend on the voltage space (voltage levels). Compared to Refs. [ 15 , 16 ], the concept proposed in this paper is simpler. Numerous works dealt with relaxation generators due to their advantages (e.g., low complexity, number of components and cost). Differential methods, in comparison with relaxation generator-based approaches, offer higher accuracy and low measurement error (units of percent). However, these solutions [ 15 , 16 ] are complex. In many cases, these methods evaluate the difference of capacities but not the absolute value of capacitance. Furthermore, various auxiliary components (e.g., control of switching, additional voltage or current sources) are necessary. The expected high output voltage levels [ 15 , 16 ] are not available in LV integrated solutions. Generator-based solutions of transducer are simple because enable direct transformation of capacity to frequency (C → f 0 ). However, their error is higher (up to 10%). Table 1gives an overview of recent works in the field of capacitance interfaces and transducers. Previously proposed concepts are evaluated based on their main features and parameters. Features and advantages of our proposed concept are highlighted in bold. As indicated in Table 1, a dominant part of the proposed solutions uses generator-based methods. In this work, we compared these solutions from the viewpoint of the direct relation to capacitance sensing and transduction. The analysis (see Table 1) led to the following conclusions: (a) the number of the used active elements in many proposed circuits is high [ 20 – 23 ]; (b) the active device concept employs many sub-parts (3 or 5 current conveyors) [ 20 ]; (c) lossless integrator increases the complexity of the proposed concept [ 20 – 22 ]; (d) declared measured ranges of “frequency vs. capacitance” dependence are not decisive for the quality evaluation—they always depend on the tested capacitance range (not identical); (e) the output information in the form of DC voltage is unavailable; and (f) the designs have similar inaccuracies (e.g., percentage error, where indicated) in similar ranges [23,24]. It is important to mention the methods that combine analog and digital ways of signal processing for capacitance sensor interfaces [ 25 – 29 ]. The method proposed in Ref. [ 25 ] employs controlled charging and discharging of the sensed capacitance and reference capacitance resulting in pulse generation with a variable width in accordance to the sensed capacity value. The methodology in Ref. [ 26 ] uses similar approach as Ref. [ 25 ], but the reference capacitor is not used here and the output information (the form of a digital word) about the capacity is covered by the changes in the period measured by a counter and processed by a microcontroller. The concept in Ref. [ 27 ] implements a phase locked loop evaluating interaction of two ring generators, based on a chain of digital inverters. The first one is controlled by the sensed capacity while the second one is driven digitally. Principle of the capacitance measurement, based on a pressure sensor, is described in Ref. [ 28 ]. This method modifies the principle that was previously presented in Ref. [ 25 ], but its overall complexity is simpler, because only current source, inverter and subtractor are used. Authors of the work [ 29 ] extended and improved a well-known principle that employs two current sources (charging and discharging), and two comparators controlling RS flip-flop. Their improvement consists in the implementation of “ramp and hold” circuit using current flowing through resistor in order to charge the measured capacitor and compare voltages at both elements. From the review of these works, it is evident that all the presented extremely low-power (LP) solutions [ 25 , 27 , 28 ] target quite a narrow range of the capacity measurement. Unfortunately, in many cases, these devices require an external source of clock or signal for their full operation that significantly increases the power consumption. In summary, principles in the above-discussed papers are totally different from our simple analog proposal (a circuit generates an autonomous waveform) and all the described methods require additional control logic, external clock signal, synchronism and switching accessory. Next, their overall complexity (mixed analog-digital design) and power consumption are significantly higher than our simple analog proposal. Sensors 2018,18, 4488 3 of 15 Table 1. Comparison of analog continuous-time operating capacitive sensor interfaces from recent literature (our work is indicated with bold fonts). References Number of Type of Principle of Number of Type of Waveform Range of Number of Range of Verification (Real Integrated Supply Error Sensitivity = ∆f0/∆capacity Active Active Operation Elements Parameter at CSensed Decades Read Parameter Implementation of Solution of the Voltage Sensitivity = ∆V/∆C Elements Elements (Grounded/Floating) Elements Parameter Active Device) Whole System Differential methods [14] (b) (b) (b) 6 (4/2) Absolute difference of Cap -−0.9 pF→+0.9 pF - −0.12 V→+0.12 V M (CMOS) Yes 2.5 V ±1.5% 1.33 ×1011 V/F [15] 4 CCII I (a) 5 (2/3) Relative difference of Cap -−30%→+30% - 2 V→11 V M (4×AD844) No ±10 V <3% 7.54 ×10−6V/m [15] 4 CCII I (a) 5 (2/3) Relative difference of Cap -−30%→+30% - 0.4 V→2 V S (CMOS) partially (f) ±1.65 V <0.23% 1.44 ×10−6V/m [16] 4 MLT, OA II (a) 8 (3/5) Relative difference of Cap -−100%→+100% - −10 V→+10 V M (AD844, AD633, INA128, LF411) No N/A ±0.8% N/A Square waveform generating circuit-based methods [30] 1 CCII III 3 (2/1) Cap E 100 pF→700 pF <1 441 kHz→346 kHz M (AD844) No ±10 V N/A 1.6 ×1014 Hz/F [20] 3 CCII III 6 (5/1) Cap T 500 pF→5µF 4 150 kHz→15 Hz B (CMOS, 3×AD844) No ±6 V N/A 3 ×1010 Hz/F [31] 1 DO-DVCC III 3 (3/0) Cap T 125 pF→10 nF <2 800 kHz→10 kHz M (5×AD844) No ±10 V N/A 8 ×1013 Hz/F [32] 1 DVCC III 3 (2/1) Cap E 1 nF→1µF 3 10 kHz→10 Hz M (3×AD844) No ±15 V N/A 1 ×1010 Hz/F [21] 2 CCII III 5 (4/1) (c) Cap T 10 nF→20 µF<4 410 kHz→260 Hz M (2×AD844) No N/A (e) N/A 2.1 ×1010 Hz/F [22] 2 CCII III 5 (1/4) Cap T 0.5 nF→10 µF<5 263 kHz→25 Hz M (2×AD844) No (±5–±15) V <5% 2.6 ×1010 Hz/F [24] 1 CCII III 4 (1/3) Cap E 100 pF→5.5 µF<5 6.9 kHz→0.14 Hz M (AD844) No N/A (e) ≤±10% 1.3 ×109Hz/F [24] 1 CCII III 4 (1/3) Cap E 22 pF→5.5 µF<6 232 kHz→1 Hz S (CMOS) partially (f) ±1.2 V ≤±10% 4.2 ×1010 Hz/F [23] 2 CCII III 4 (3/1) Cap T 500 pF→200 nF <3 39 kHz→98 Hz M (2×AD844) No ±9 V <7% 2 ×1011 Hz/F Proposed (C→f0conversion) This work 1 CFOA III 4 (2/2) Cap E 4.7 nF→470 nF 6.8 nF→100 nF 3 <2 89.3 kHz→1.1 kHz 74.8 kHz→4.8 kHz M (CMOS CCCII, buffer) partially (f) ±1.65 V <±11% <±6% 1.9 ×1011 Hz/F 7.5 ×1011 Hz/F Proposed (C→Vconversion) This work 1 CFOA III 10 (5/5) (d) Cap E 4.7 nF→470 nF 6.8 nF→100 nF 3 <2 0.134 V→0.019 V 0.106 V→0.021 V M (CMOS CCCII, buffer, diodes) partially (f) ±1.65 V <±12% <±5% 247 ×103V/F 912 ×103V/F Notes: I—differential measurement ( ∆ C → V), II—bridge balancing (differential measurement of capacity values; ∆ C → V), III—generator (C → f 0 ), IV—charging and discharging of C and reference capacity and pulse width evaluation, V—period-modulated method, VI—comparison of phases of digitally controlled oscillator and oscillator influenced by capacitance, VII—see discussion in Ref. [ 29 ], T—triangular, E—exponential, M—measured, S—simulated, B—both CCII—current conveyor of second generation, CCCII—current controlled current conveyor of second generation, CCII—current conveyor of second generation, CFOA—current feedback operational amplifier, DO-DVCC—differential output—DVCC, DVCC—differential voltage current conveyor of second generation, ENOB—effective number of bits, MLT—multiplier, OA—operational amplifier; (a) external sine wave source required; (b) 3 active devices (transconductance stage, differential and summing current amplifier, switches, buffer, additional DC current sources), sensed difference of switched DC bias currents; (c) 2 capacitors are required; (d) including diodes (Note that column “number of passive elements” includes C sens ); (e) supply voltage is not mentioned in the text, but results indicates ±(10–15 V); (f) simulated/measured only at cell level (layout prepared for active device but not shown for fully integrated system). Sensors 2018,18, 4488 4 of 15 In this paper, a novel concept of capacitance sensor interface is presented, which is based on the well known square wave generator principle. Compared to Ref. [ 18 ], where a method employing capacitance divider and calculation from known supplying voltage is used, we propose a solution for implementing two conversions: C sens→ f 0→ V sens . Topology of the whole circuitry is simpler than previously proposed concepts; see Refs. [ 18 , 20 – 23 , 31 , 32 ]. Note that all concepts presented in Refs. [20–24,30–32] need an additional f 0→ V sens converter. Thereby, solutions presented in Refs. [ 20 – 23 , 31 , 32 ] become more complex than concepts presented in Refs. [ 24 , 30 ]. The concept of a two-conversions-based transducer has not been studied and evaluated in these types of generator-based capacitance sensor interfaces. Compared to state-of-the-art and previously presented solutions (see Table 1), the originality and main contributions of this work are as follows: (a) a new simplified CMOS topology of the active element is proposed and utilized to create a square wave generator with a low impedance voltage mode output; (b) a new simple capacity to voltage sensing interface with low number of passive elements is realized; and (c) an appropriate method to combine of square-wave generator (a C sens→ f 0 converter) and frequency to DC voltage (f0→Vsens) converter is presented. Remaining parts of the paper are organized as follows. A new concept of the transducer/interface for the capacitance measurement, its counterparts and their theoretical analysis are described in Section 2. Experimental verification of the established Mathcad model of f 0→ V sens conversion and results from measurements of the proposed device are presented and compared with theory assumption in Section 3. This section also contains the evaluation of the obtained results. Finally, Section 4concludes this paper. 2. Readout Circuit for Capacity Measurement A block diagram of the capacity measurement, used in the proposed solution, is shown in Figure 1. The sensed capacitor directly determines the oscillation (repeating) frequency, marked as f 0 , of the square wave generator. After that, the frequency is transformed to the DC voltage (V sens ). Such a form of the output information is very useful because the capacitance can be measured by a low-cost magneto-electric analog voltmeter. The voltmeter has a scale calibrated as capacitance or the DC voltage can be easily processed by any analog-to-digital converter (ADC). Figure 1. Principle of the capacity measurement. The integrated square wave generator forms the core of the above briefly described capacity measurement. Its principle is as follows. The generator consists of a special type of Schmitt comparator with hysteresis and an RC network serving as a lossy integrator [ 1 , 33 ]. The RC section is supplied from the output of the comparator (see Figure 2) after impedance separation by a simple voltage follower (buffer). Thanks to this concept (a feedback including buffer), the proposed topology is different from the solution presented in Ref. [23]. Moreover, in Ref. [23], complex active devices are used. The comparator uses a single current controlled current conveyor of second generation (CCCII) [34,35] , a voltage buffer and two resistors. Such an arrangement of active devices is called a current feedback operational amplifier (CFOA) [ 33 ]. The principle of CCCII is described by the following inter-terminal relations: V Y = 0, V X =V Y (open X), V X =V Y +R X I X and I Z =I X . The V o =V z relation is added by the voltage buffer. Sensors 2018,18, 4488 5 of 15 Figure 2. Principle of the proposed comparator. The operation of the comparator especially employs the I Z =I X relation. The current, flowing to the X terminal, is directly copied to the Z terminal. It is valid that I R2 =V out /R 2 = ± V Zmax(sat) /R 2 . The saturation voltage of the output Z almost reaches the supply voltage, equals to ± 1.65 V. When we consider a postive feedback to the Y terminal and relation between Y and X terminals, where X terminal is terminated by the resistor R 1 =R Xext +R Xint and the voltage V inp is present at this node, then relation IZ=IXleads to the following expression: VZmax(sat) −Vinp(ref) R1 =VZmax(sat) R2 . (1) Rearrangement of (1) gives a direct relation for the input threshold symmetrical voltages: ±Vinp(ref) =∓VZmax(sat) ×1−R1 R2. (2) The complete circuitry of the capacity to voltage sensing readout is captured in Figure 3. This circuitry consists of two main blocks, namely Csens→f0and f0→Vsens converters. Figure 3. The complete circuitry of the proposed capacity to voltage sensing interface (readout). 2.1. The Csens→f0Converter The C sens→ f 0 converter (a square wave generator) is obtained, when the voltage buffer separates the high impedance output node of the comparator (see Figure 2) and an RC network (R 3 ,C sens ) is Sensors 2018,18, 4488 6 of 15 connected between the output node and V inp (to R Xext ) of the comparator. The square wave signal at the output of the buffer, marked as V SQ (t), and the signal in the node of C sens , marked as V EXP (t), are important for further explanation (see time diagram in Figure 4). Figure 4. Time diagram of transient responses for analysis of the generator operation. The time-constant of the C sens charging can be expressed as a parallel combination of resistors R 1 and R3:τ=[(R1R3)/(R1+R3)]×Csens. The half period of the charging interval is defined as: VEXP(0≤t≤T/2) = (VEXPmax +VSQmax)h1−e−t τi, (3) where V EXPmax =V inp(ref) (threshold voltage of the comparator) and V SQmax =V Zmax(sat) (saturation voltage of the comparator). According to V EXP (t=T/2) = 2V inp(ref) , where capacitor charges from −Vinp(ref) to +Vinp(ref), the following formula can be write for t=T/2: 2Vinp(ref) = (Vinp(ref) +VZmax(sat))h1−e−T 2τi. (4) After rearrangement of (4), the period can be expressed as: T=2τln VZmax(sat) +Vinp(ref) VZmax(sat) −Vinp(ref) !, (5) where voltages and the time-constant can be substituted by (2) and by the above introduced expressions, respectively. After that, the period and repeating frequency f0can be calculated as: T=1 f0 =2Csens R1R3 R1+R3ln 2R2−R1 R1. (6) The maximum current levels (magnitudes do not considering the current polarity), passing through the passive elements of the topology, are determined as follows: IR2max =VZmax(sat) R2 , (7) IR1,3max =VZmax(sat)+Vinp(ref) R1,3 , (8) |ICmax |=IR1,3max +IR2max . (9) Sensors 2018,18, 4488 7 of 15 2.2. The f0→Vsens Converter The f 0→ V sens converter (see Figure 3) consists of a diode doubler including two diodes, two capacitors and two resistors. In many standard applications [ 36 ], such a concept operates as a peak detector. However, from the viewpoint of time-constant values of the floating ( τA =R A C A ) and grounded ( τB =R B C B ) segments, our case is different. Description of the simplified operation of this block is presented in the following paragraph. The V SQ (t) voltage changes immediately between +V Zmax(sat) and − V Zmax(sat) . The negative polarity of V SQ (t) subsequently charges C A to − V Zmax(sat) . When the V SQ (t) turns to +V Zmax(sat) , then the maximal current through C A for T/2 can be obtained as I CAmax = (2V Zmax(sat) − V D )/R A . Here, V D marks the voltage drop across the diode ( ≈ 0.7 V) and R A is a resistor used to limit the charging current. The maximal voltage (a change across C A ) determines the overall charge through one period as follows: Q A = 2(V Zmax(sat) − V D ) × C A . Due to the change of the polarity of V Zmax(sat) , the charge is moved and accumulated by the grounded segment C B . The time-constant of the grounded segment is very high. In this case, it is supposed that τA<< τB . Consequently, slight discharging of C B in one period is influenced only by the resistor R B . It can be expressed as i RB (t) = dQB (t)/dt ∼ = Q B /T. In fact, i RB (t) is almost constant due to high τB , thereby, I RB =V sens /R B . In the case of Q A =Q B (charge conservation), the ideal relation between the frequency f0and voltage Vsens will be: Vsens ∼ =2VZmax(sat) −VDRBCA T∼ =2VZmax(sat) −VDRBCAf0. (10) Using (10) and (6), it is possible to obtain the relation between Vsens and Csens: Vsens =VZmax(sat) −VDRBCA Csens R1R3 R1+R3ln 2R2−R1 R1. (11) The limitation of validity of (11) concerns periods shorter than time required to accumulate a charge in the floating segment. Thereby, the output V sens voltage goes to zero. Restriction of the converter for very large periods, where the floating segment has faster response (short time-constant) than the processed signal, must be taken into account. In this case, the charge in the circuit for f 0→ V sens conversion is not subsequently accumulated (moved from C A to C B ) in each period of the input signal. The capacitor C B is charged directly by the input signal whereas, the discharge ( τB ) is not fast enough. Thereby, this approach cannot be used in the full frequency range of the signal generated by the relaxation generator circuit. This range of operation depends on the processed frequency and time-constants (τA,τB). 3. Experimental Verification The complete CMOS topology of the CFOA is shown in Figure 5a. Fabricated cells in ON Semiconductor C035 0.35 µ m I3T25 CMOS [ 37 ] were used for experimental verification of the proposed concept (see Figure 5b,c). The implementation of CCCII and BUFFER into CFOA element is depicted in Figure 2. The power supply is ± 1.65 V and I SETRXint = 100 µ A (R Xint ∼ = 440 Ω ). The rest of the external passive elements have the following values: R Xext = 560 Ω (R 1 =R Xext +R Xint = 1 k Ω ), R 2 = 4.7 k Ω and R3= 1 kΩ. Figure 5d depicts the realized and measured prototype. The proposed CFOA device has the following features: (a) − 3 dB bandwidts > 49 MHz (Y → X), − 3 dB bandwidth > 37 MHz (X → z) and − 3 dB bandwidth > 45 MHz (z → o); (b) transfers (DC analysis) offer linear processing between ± 1 V (for Y → X), ± 1.7 mA (for X → z) and ± 0.8 V (for z → o); (c) terminal resistances reaches 100 M Ω (Y terminal), >66 k Ω (z terminal), and 280 → 3400 Ω (X terminal) when internal R X is adjusted by DC bias current from 10 up to 350 µ A. Terminal resistance of the o terminal is 0.54 Ω . Parasitic terminal capacities reach values approximately from 2 pF up to 20 pF (it is depending on the design of PCB). The DC input offsets are below 2.5 mV for Y→X transfer, below 6 µA for X→z Sensors 2018,18, 4488 8 of 15 transfer and below 10 mV for z → o transfer. For the inindicated DC input range, the maximal THD is 1.5% for X→z transfer, 0.6% for Y→X transfer, and 0.5% for z→o transfer. (a) (b) (c) (d) Figure 5. ( a ) The complete CMOS topology of CFOA; layouts of CFOA cells (on a single IC package) fabricated in I3T25 process: ( b ) current controlled current conveyor of second generation (CCCII) and ( c ) voltage buffer; and ( d ) the realized and measured prototype of readout (CFOA and f 0→ V sens converter). The values of the passive elements in the f 0→ V sens converter are as follows: R A = 100 Ω , C A = 1 nF, R B = 1 k Ω and C B = 100 nF. Next, 1N4148 diodes were used. Such values of the passive Sensors 2018,18, 4488 9 of 15 elements, time-constants as well as parameters in the generator part of the C sens→ f 0 converter are intended to expect capacitance values from units to tens of nF. The value of V Zmax(sat) , equals to ± 1.5 V, was obtained from the experiments. We also suppose V D = 0.7 V (standard threshold value for the 1N4148 diode). According to the above considered values, there is predicted a numerical constant from (11) that allows ideal estimation of the relation between the produced DC voltage and the sensed capacity. It can be expressed as Vsens ∼ =8×10−10/Csens. The C sens was tested in the range from 100 pF to 470 nF. Dependencies of f 0 on C sens and output voltage levels (V SQ and V EXP ) on f 0 are shown in Figure 6a,b, respectively. A significant influence on the accuracy of the generated f 0 starts from C sens < 1 nF. Stability of the square wave output level is also an important feature for the correct operation of the f 0→ V sens converter. This response is almost constant in the whole operational range of the f 0 (see Figure 6b). Figure 7shows the overall system performance, namely V sens versus C sens . It contains curves obtained from theory, Mathcad calculations and experimental measurements. The complete model of the f 0→ V sens converter has been implemented in Mathcad in order to verify the correctness of the proposed design. A quite substantial difference is visible between the theory and experimental data. Nevertheless, simulation and measurement results well correlate because the error in the operational range from 6.8nF to 100 nF is only 5% (see Figure 8). For the case C sens < 6.8 nF, the difference between them is caused by the inaccuracy of f 0 (not considered in the Mathcad model). Thereby, theoretical value V sens ∼ = 8×10−10/Csens serves only for orientation purposes. 0.1 1.0 10.0 100.0 1000.0 1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 f0 [kHz] Csens [F] measured ideal theory (a) 1.0 1.5 2.0 2.5 3.0 3.5 1.0E+03 1.0E+04 1.0E+05 1.0E+06 VEXP, SQ [Vp-p] f0 [Hz] VEXP VSQ (b) Figure 6. Features of the proposed generator: (a)f0versus Csens; (b) output levels versus f0. 0.00 0.05 0.10 0.15 0.20 0.25 110 100 Vsens [V] Csens [nF] measured Mathcad analysis ideal theory Vsens  0.8/(Csens [nF]) Vsens  0.34∙(Csens [nF])-0.64 Vsens  0.42∙(Csens [nF])-0.7 Figure 7. Comparison of the Vsens versus Csens curves (theory, Mathcad simulations, measurements).