Versatile Chirp Sine Generator on Fix-point FPGA

DOI:10.14311/AP.2020.60.0462 Ac a Poly echnica 60(6):462–468, 2020 ©Czech Technical Uni e si y in P ague, 2020 a ailable online a h ps://ojs.c u .cz/ojs/index.php/ap VERSATILE CHIRP SINE GENERATOR ON FIXED-POINT FPGA Jan Kunz∗, Pe Beneš B no Uni e si y o Technology, Facul y o Elec ical Enginee ing and Communica ion, Depa men o Con ol and Ins umen a ion, Technická 3082/12, 61600 B no, Czech Republic ∗co esponding au ho : [email p o ec ed] Abs ac . This pape deals wi h a loga i hmic and a linea chi p sine gene a ion on a ixed-poin FPGA mainly o ib a ion es ing, ne e heless, he gene a o can also be used in o he a eas. A basic o e iew o he loga i hmic chi p sine signal is p o ided. Then, me hods o so wa e signal gene a ion as well as di e en ha dwa e pla o ms a e b ie ly desc ibed and hei p os and cons a e men ioned. A DDS gene a o on FPGA needs he phase di e ence be ween samples as an inpu . This gene a ion o he loga i hm chi p sine signal is p esen ed, and i s esolu ion, e o s and limi a ions on ixed-poin a i hme ic a e e ealed. Ou implemen a ion uns on Compac RIO 9067, uses 32-bi ixed-poin and is able o gene a e linea and loga i hm chi p signals om 10 Hz o 7 kHz wi h a minimum chi p speed o 1 oc /min. Keywo ds: Linea chi p sine, loga i hm chi p sine, FPGA, ixed-poin , gene a ion. 1. In oduc ion Sinusoidal signals and hei a ia ions a e, due o hei p ope ies, commonly used in enginee ing [ 1 ]. Thei usage a ies om basic, such as an impedance measu emen , a sys em iden i ica ion and a ib a ion analysis, o mo e sophis ica ed ones, such as a mo o con ol, a nuclea magne ic esonance o an elec on pa amagne ic esonance. Some imes, a chi p sine signal (CS), sinusoidal sig- nal wi h a con inuous equency change, is used. The mos common equency changes a e linea o log- a i hmic, howe e , he change can be desc ibed by o he means. In some applica ions, o ins ance he impedance measu emen , he knowledge o he ac- ual chi p sine equency is essen ial, whe eas o he applica ion do no equi e i . Fu he mo e, in dwell i- b a ion es ing [ 2 ], i is some imes necessa y o change he chi p speed in dependence on he p e ious s a e, he e o e, a small delay is necessa y. The change o he chi p speed o he ansi ion be ween he chi p sine and sine has o be done wi h a minimal phase noise. Nowadays, linea and loga i hmic chi p sine signals can be gene a ed e y easily using, o example, a di ec digi al syn hesis, a ol age con olled oscilla o , a look-up able o a phase gene a ion [ 1 , 3 , 4 ]. How- e e , hese me hods do no allow a as change o a chi p speed oge he wi h he knowledge o he ac ual equency a he same ime. This can be done by a so wa e gene a o based, o ins ance, on a di ec digi al syn hesis. Howe e , a poin - o-poin gene a ion, which allows a as esponse ime, needs as compu a ion. Fu he mo e, he algo- i hm is ela i ely simple, wi hou many b anches and condi ions, he e o e, i is mo e sui able o FPGAs han p ocesso s. To allow he as esponse ime, a poin - o-poin gene a ion is c ucial, o his ype o gene a ion he FPGA is mo e con enien han p ocesso s. FPGAs a e becoming mo e and mo e popula because hey allow ue pa allelism and he compu a ion powe is also su icien [5]. Un o una ely, mos o his powe is a ailable on a ixed-poin a i hme ic, howe e , mode n FPGAs also con ain some loa ing-poin co es. The e o e, hese co es should be used wisely o p ecise compu a ion. Fo his eason, we ha e decided o use he ixed-poin a i hme ic o he gene a o . LabVIEW 2018 was selec ed as he pla o m o p og amming and he gene a o is execu ed on Com- pac RIO 9067, which con ains Zynq xc7z020 equipped wi h ARM co ex-A9 p ocesso and a medium-sized FPGA. Compac RIO is a eal- ime embedded indus ial con olle , which allows p ecision iming, such as STC3, o TSN. Fu he mo e, i is compa ible wi h mo e han 100 di e en I/O ypes a ying om in- dus ial communica ion, ia digi al and analog signal inpu /ou pu , o speci ic senso condi ioning, o in- s ance, cha ge ou pu , IEPE, he mocouple, b idge, e c. This makes he Compac RIO a e sa ile ool o a ious applica ions [ 6 ]. This combina ion o com- pu a ion powe and a ious pe iphe als makes he pla o m ideal o de elopmen and as p o o yping as well as ad anced con ol and moni o ing. 2. Chi p sine signal Chi p sine signal is a sine signal, whose equency is changing wi h ime. Linea chi p sine signal is used, o example, in ada s. Speci ically, a F equency- Modula ed Con inuous-Wa e (FMCW) wi h equen- cies as high as possible is used because he highe equencies, he be e esolu ion. Fo his eason, he 462 ol. 60 no. 6/2020 Ve sa ile chi p sine gene a o on ixed-poin FPGA FMCW signal o ada s is o en gene a ed using he FPGA and he maximal equency o he signal is ens o GHz [7]. The gene a ion is explained in [8, 9]. Some o he pape s ocus on FPGA e sa ile chi p and sine signal gene a o s [ 8 , 10 ], ne e heless he chi p signal is also only linea . Fo his eason, his pape ocuses on gene a ion o loga i hmic chi p sine. The speed o he LCS is de ined by a cons an , which can be ei he (dec/s) o (oc /s) 1 . Because he sweep speed is usually low, he chi p cons an s a e o en de ined in di e en ime uni s, such as ( min−1 ) o e en (hou −1). The chi p speed can also be de ined by a s a and a s op equency and a du a ion o he sweep. F om hese, he speed o he loga i hmic chi p signal can easily be calcula ed (eq. 1) and ice e sa. In his pape , e e y hing is demons a ed, o simplici y, on he same LCS signal wi h pa ame e s s a = 10 Hz , s op = 100 Hz , k = 0 . 1 dec/s , so he du a ion is = 10 s. k= log10  s op s a  (1) whe e k ( dec/s )is he chi p speed cons an , s op ( Hz ) is he s op equency, s a ( Hz )is he s a equency and (s)is he sweep du a ion. 3. FPGA sine gene a o s The e a e se e al FPGA sine gene a o s, some a e desc ibed in he li e a u e [ 8 , 9 , 11 , 12 ] and some a e comme cially a ailable, o ins ance, he NCO IP Co e [ 13 ] om In el ( o me Al e a), o DDS [ 14 ] om Xilinx. Some o hem pu an emphasis on he gene a ion speed o maximal equency o he gen- e a ed signal, whe eas o he on spec al pu i y and maximal esolu ion. Ne e heless, all gene a o s use he phase di e ence be ween samples as an inpu , as shown on block diag am ( ig. 1). De e mining he phase di e ence o sine signal is easy, ne e heless, in he case o sweep sine signals, he phase di e ence changes o e e y sample. Mo eo e , he accu acy o he phase di e ence de ines he quali y o he sweep signal. Some FPGA sine gene a o implemen a ions [ 8 , 9 ] use a look-up able as a sou ce o he phase di e ence. O he implemen a ions [ 11 , 12 ] gene a e he phase o he linea chi p signal ia in eg a ion. Ne e heless, nei he o hese me hods can be e ec i ely used o he loga i hm chi p sine signal, as he phase di e ence changes non-linea ly in dependence o he chi p speed and equency ange. The calcula ion o he phase di e ence o he loga- i hm sweep signal as well as i s e o s and limi a ions caused by he ixed-poin a i hme ic is he aim o his pape . To gene a e an ac ual signal, a simple sine 11dec/s = log210 oc /s . = 3,32 oc /s Phase accumula o Signal gene a ion Phase inc emen Sine Cosine Figu e 1. P inciple o sine gene a ion on FPGA o comme cially a ailable modules. Ac ual equency Signal gene a ion Chi p speed Sine Cosine Sampling pe iod 10x Phase S Figu e 2. P inciple o loga i hm chi p sine gene a ion on FPGA. gene a o was c ea ed, howe e , i can be eplaced by, o ins ance, some o he a o emen ioned solu ion. 4. FPGA chi p signal gene a ion To achie e a poin - o-poin gene a ion o a phase, i is necessa y o in eg a e an angula eloci y, which is he same, excep he cons an 2 π , as a equency. Consequen ly, i is mo e con enien o in eg a e e- quencies, because he in o ma ion abou he ac ual equency can be use ul. Mo eo e , his way allows easie phase-w apping o achie e he bes a ailable phase esolu ion as shown in (sec. 5.2). The ac ual equency o each sample can be cal- cula ed (eq. 2) by a mul iplica ion o he p e ious equency. In he case o he linea sweep, he e is a simple addi ion o a equency di e ence ∆ and in he case o a pu e sine signal, he equency e- mains he same. This is he only a ia ion o signal gene a ion in ou me hod. The block diag am o he gene a o is shown in igu e ( ig. 2). (n) = (n−1) ·10 k s(2) whe e ( n )and ( n− 1) a e ac ual and p e ious equencies (no e ha (0) is a s a equency), k is a chi p speed cons an in ( dec/s ) and s is a sampling equency. The poin - o-poin phase gene a ion om a known equency can be done ei he by a nume ical in eg a- ion o by an in eg a ion om he analy ical p esc ip- ion. 4.1. Nume ical In eg a ion The apezoidal me hod appea s con enien o a nu- me ical in eg a ion, because his me hod needs only he cu en and he p e iously calcula ed equency. Equa ion (3) shows he calcula ion. Exac ly he same calcula ion can be used o he linea chi p sine and pu e sine signals as well. Howe e , his in eg a ion me hod gene a es an e o , which is isualized on ( ig. 3), whe e i is isible ha o sho e du a ions, he e o ades in o insigni icance compa ed wi h .e. he DAC quan iza ion e o o noise. 463 Jan Kunz, Pe Beneš Ac a Poly echnica Figu e 3. A phase e o be ween he loga i hmic chi p signal gene a ed by a nume ical in eg a ion using he apezoidal ule and a LabVIEW buil -in unc ion. Signal pa ame e s s = 10 kHz , s a = 10 Hz , s op = 100 Hz. ϕ(n) = ϕ(n−1) + 2π·T· (n) + (n−1) 2(3) whe e ϕ ( n )and ϕ ( n− 1) a e he cu en and p e ious phases, T is he sampling pe iod, ( n )and ( n− 1) a e he ac ual and p e ious equencies. 4.2. Analy ical In eg a ion To calcula e he phase om he angula eloci y (o equency) is analy ically simple (eq. 4) due o he i ial equency unc ion. The calcula ion is e y simple because he ln ( k )is a cons an so i can be calcula ed be o ehand. As he calcula ion ollows he analy ical ule, he me hod e o should be ze o. Howe e , he e is an e o ( ig. 4) be ween he ixed-poin implemen a ion o his me hod and he loa ing poin unc ion. This is due o he limi ed ixed-poin esolu ion. ϕ(n) = ϕ(n−1) + 2π· (n)− (n−1) ln(k)(4) whe e ϕ ( n )and ϕ ( n− 1) a e he cu en and p e ious phases, ( n )and ( n− 1) a e he ac ual and p e ious equencies and kis he chi p speed cons an . The nume ical in eg a ion is less accu a e, howe e , i is mo e sophis ica ed, as i can be used o he linea sweep and he sine gene a ion as well. Because he me hod e o in he p esen ed case is signi ican only o long sweep du a ions (hou s), i seems mo e p ac ical o use he nume ical in eg a ion me hod ins ead o he analy ical one. 5. Fixed-poin limi a ions FPGAs a e wo king wi h a ixed-poin numbe ep e- sen a ion o achie e he desi ed speed o compu a ion and pa allelism. This app oach p o ides se e al di e - ences compa ed o he loa ing-poin numbe s. On he Figu e 4. A phase e o be ween loga i hmic chi p signal gene a ed by an analy ical in eg a ion using ixed-poin and loa ing poin ep esen a ion. Signal pa ame e s s = 10 kHz , s a = 10 Hz , s op = 100 Hz. 10 kHz 50 kHz 24-bi 32-bi 24-bi 32-bi 0.0988832 0.0999955 0.0957778 0.0999843 0.0994009 0.0999975 0.0983664 0.0999944 0.0999186 0.0999995 0.1009550 0.1000045 0.1004363 0.1000016 0.1035436 0.1000147 0.1009541 0.1000036 0.1061322 0.1000248 0.1014718 0.1000056 0.1087208 0.1000349 Table 1. Possible alues o a chi p speed in ( dec/s ) closes o he p esen ed chi p speed k = 0 , 1 dec/s o ixed-poin bi leng hs 24 and 32 and sampling equencies 10 kHz and 50 kHz. one hand, he e a e some ad an ages such as nume ic o e low, and on he o he hand some disad an ages like a lowe esolu ion. 5.1. Resolu ion limi Since he esolu ion limi seems o be a g ea issue, i can be sol ed easily by inc easing he numbe bi leng h. Howe e , he highe he bi leng h, he highe he esou ces consump ion is, which limi s he amoun o code o i in he FPGA. Fo his eason, i is essen- ial o de e mine he necessa y bi leng h be o ehand. In his pape , wo di e en bi leng hs, 24 and 32, a e used o show he di e ences. As isible om (eq. 2), he ac ual equency is calcula ed om he p e ious one by mul iplica ion by a numbe , which is e y close o one 2 . The esolu ion o his mul iplie a ec s he possible chi p speeds and i is he main limi a ion o he ixed-poin gene a ion. This also limi s he possible chi p speeds o se e al disc e e alues ( ab. 1) and leads o a equency e o . The e o be ween he ideal ( loa -poin calcula ion) and ac ual ( ixed-poin calcula ion) equency is shown in ( ig. 5). 2in p esen ed case he numbe is 100,00001 . = 1.0000230261 464 ol. 60 no. 6/2020 Ve sa ile chi p sine gene a o on ixed-poin FPGA Figu e 5. A equency e o be ween a loga i hmic chi p signal gene a ed by 24 and 32-bi ixed-poin a i hme ic wi h ounding and a loa ing-poin gene a- ion. Signal pa ame e s s = 10 kHz , s a = 10 Hz , s op = 100 Hz. Howe e , i is usually enough o keep he chi p speed wi hin a ce ain limi . Fo example, he [ 2 ] limi s he equency e o o a ib a ion es ing o ± 5 %. This can also be easily achie ed wi h he ixed- poin compu a ion, whe e he e o s can be much smalle ( ab. 1). Mo e impo an is he accu acy o he ac ual cal- cula ed equency (phase). As he calcula ion i sel p oduces no e o , he esul has o be ounded o i in o he ixed-poin ange. The maximum ounding e o o one calcula ion is one leas signi ican bi (LSB), so i can be neglec ed. Howe e , he ounding e o is accumula ed h oughou he whole signal gen- e a ion, whe e i can cause a signi ican di e ences as shown in (sec. 5.3). Fo his eason, i is necessa y o handle he ounding p ope ly. In conclusion, he calcula ed equency is he ac ual equency o he gene a ed sample up o an e o o he sine unc ion, which is de ined by an ac ual implemen a ion. How- e e , he equency is di e en om he ideal one due o he ounding. 5.2. Numbe w apping To keep he phase accumula ion e o as low as pos- sible, i is necessa y o ha e a maximal ixed-poin esolu ion. Howe e , he phase o he loga i hm chi p signal is exponen ially ising, so i is necessa y o w ap i . Phase w apping is no mally done as a e- mainde a e di ision, howe e , his me hod equi es a ixed-poin di ision, which is inaccu a e and ime demanding. Fo his eason, i is be e o le he phase w ap when he ixed-poin o e lows. I we use modi ied uni s ( π· ad ) ins ead o no mal phase uni s ( ad ) modi ied uni s ( π· ad ), hen he phase can eas- ily be w apped, when i exceeds he alue 2, because i means 2 π ad , so one pe iod o a sine unc ion. Mo eo e , i is e y easy o w ap a ound his alue jus by igno ing he o e low s a us and keeping he es . Figu e 6. A equency e o be ween a loga i hmic chi p signal gene a ed by 24-bi ixed-poin a i hme ic wi h di e en coe cing op ions, unca e and ound and a loa ing-poin gene a ion. Signal pa ame e s s= 10 kHz, s a = 10 Hz, s op = 100 Hz. 5.3. Resul ounding A esul om he ixed-poin a i hme ic ope a ion has o be ounded o i in o he p ede ined bi leng h. The e a e wo possible ways how o p oceed. Unnec- essa y bi s can be ei he cu o ( unca e mode) o he numbe can be coe ced. This is done by adding hal o he LSB o he esul and hen he esul is unca ed. The unca e mode is e y as , howe e , i can p oduce e o o up o one LSB. Howe e , coe c- ing equi es a li le bi mo e esou ces and one mo e adding ope a ion, bu he e o is hal o he LSB maximum. Mo e in o ma ion is p o ided in [5]. Bo h me hods can be used in he chi p signal gen- e a ion wi h a di e en impac on he esul . The unca e me hod consumes less esou ces, bu p o- duces a bigge e o han he o he me hod, which is mo e esou ce demanding. The e o s o he 24-bi calcula ion a e shown in ( ig. 6). The e o o he ounded esul is clea ly isible in ( ig. 5). Mo eo e , he ac ual change o ounding om lowe o highe alue and ice e sa, which causes he non-mono ony o he e o cu e, is also isible . 6. Limi aions When conside ing app op ia e bi leng h o a ixed- poin ep esen a ion, i is necessa y o conside i s limi a ions. A maximal equency is de e mined by a decimal pa o he ixed-poin , whe eas he es , a ac ional pa , limi s a esolu ion, a chi p speed and a sampling equency. The maximal equency in he chi p signal has o be lowe han he maximum ep esen ed alue o he ixed-poin . O he wise, he equency will be coe ced o e en wo se, w apped. This will esul in a com- ple ely di e en signal. Fo una ely, he maximum equency can be easily calcula ed om he numbe o decimal bi s. The leng h o he ac ional pa indica es he e- quency esolu ion, which has o be lowe han he 465 Jan Kunz, Pe Beneš Ac a Poly echnica Figu e 7. A minimal leng h o a ac ional pa o a ixed-poin numbe in dependence on a minimal equency in a chi p signal o di e en chi p speeds and sampling equencies. di e ence be ween wo lowes equencies in he chi p signal. O he wise, he new equency will be coe ced o he p e ious one, which esul s in a sine signal ins ead o he chi p one. The di e ence is de e mined by he chi p speed and he sampling equency. The calcula ion o he necessa y ac ional esolu ion is p esen ed in (eq. 5) and i is isualized o he selec ed cases in ( ig. 7). es ≥log2  1 min ·10 k s−1 (5) whe e es ( bi )is a minimal numbe o ac ional bi s in ixed-poin numbe , min ( Hz )is a minimal equency in signal, k ( dec/s )is a chi p speed and s(Hz)is a sampling equency. The ampli ude o he signal is, when an app op ia e ixed-poin ep esen a ion is selec ed, de e mined by a used analog ou pu ca d. Howe e , especially small ampli udes can also be a ec ed by ounding in he sine e alua ion. Howe e , his possible issue should be sol ed in ad ance by selec ing necessa y p ecision o he unc ion used. Fo example, a e sa ile ixed-poin gene a o o a ib a ion es ing should be able o gene a e a chi p signal om 10 Hz o 7 kHz wi h a chi p speed 3 1 oc /min . In his case, a 50 kHz sampling equency is su icien . Then, he e sa ile gene a o equi es 13 bi s o he decimal pa and 19 bi s o he ac ional pa . So, in gene al, a 32-bi ixed-poin ep esen a ion o a equency is enough o his gene a o . 7. Implemen a ion The gene a o was implemen ed in LabVIEW 2018 and execu ed on Compac RIO 9067. The da a ype used o he implemen a ion was a 32-bi ixed-poin wi h ounding a e an a i hme ic ope a ion, because 31oc /min . = 0.005dec/s Figu e 8. Compa ison o he ac ual chi p speed equency gene a ed on 32-bi ixed-poin and loa ing poin a i hme ics. in ou case, his ep esen a ion can mee he a o e- men ioned c i e ia. The gene a o is able o gene a e a loga i hmic and a linea chi p signal as well as a sine signal. This is possible due o a di e en me hod o he ac ual equency calcula ion. I can be calcula ed by a mul- iplica ion o he loga i hmic sweep, an addi ion o he linea sweep o emain he same as a p e ious equency o he sine signal. Pa ame e s o he gene a ion a e sen o he FPGA om a supe io con ol sys em. The s a and s op equencies and he ampli ude a e ansmi ed un- changed, bu he chi p speed is ecalcula ed acco ding o he sampling equency o a mul iplie (eq. 2). Whe eas he sampling equency is de e mined by an analog ou pu ca d speed so i is no necessa y o ansmi i . The ac ual equency is coe ced o i be ween he s a and s op equencies. When he s op equency is eached, a lag abou he chi p comple ion is se . This is due o he unknown du a ion o he chi p caused by he disc e e chi p speeds ( ab. 1) and ounding. A e he comple ion, a sine signal wi h he same equency (s op equency) and ampli ude is gene a ed un il he supe io sys em does no change he pa ame e s o shu down he gene a ion. This algo i hm consumes 406 o al slices, 1317 slice LUTs and 8 DSP48, which a e used o he sine e al- ua ion. 7.1. Gene a ed signal The implemen a ion esul s a e shown on he loga- i hm chi p sine wi h a o emen ioned pa ame e s ( s a = 10 Hz, s op = 100 Hz,k= 0.1dec/s). Due o he esolu ion limi , he chi p speed is a li le bi highe han he selec ed alue (sec. 5.1), he e o e, he du a ion is sho e , as can be seen in he igu e (8). Unlike he chi p speed, whe e sligh di e ences a e usually ole able, he spec al pu i y is essen ial, es- pecially in he ansi ion be ween he chi p and sine 466 ol. 60 no. 6/2020 Ve sa ile chi p sine gene a o on ixed-poin FPGA Figu e 9. De ail o he ansi ion be ween he chi p and sine signal gene a ed by ou 32-bi ixed-poin gene a o . signal. In ou implemen a ion, he ansi ion seems smoo h, because i changes only he phase di e ence calcula ion. The ansi ion is shown in igu e ( ig. 9). Ne e heless, mo e sophis ica ed sine signal gene a o wi h his phase gene a o can be used o ensu e a be e signal pu i y. One can see ha he implemen a ion o he ixed- poin gene a o p o ides a us wo hy signal wi h only ew limi a ions. 8. Resul s This pape desc ibes he poin - o-poin gene a ion o a loga i hm and linea chi p as well as pu e sine signal using a ixed-poin numbe ep esen a ion o use he algo i hm on he FPGA. Main e o s and limi a ions a e also discussed. Fo he selec ed FPGA, he pla o m implemen a ion o he poin - o-poin signal gene a ion me hod is used. This me hod and i s e o s a e explained in (sec. 4), whe e i is shown ha he me hod e o s ade in o insigni icance when compa ed o o he s. T ans e ing he calcula ion om a loa ing-poin o a ixed-poin a i hme ic comes wi h o he limi a ions, such as disc e e chi p speeds ( ab. 1), and o cou se, accu acy e o s ( ig. 5). Mo eo e , he ixed-poin calcula ion su e s om addi ional issues, which ha e o be conside ed, such as esul s ounding ( ig. 6). Using a speci ic ixed-poin leng h also limi s he ange o possible equencies in dependence on he chi p speed and he sampling equency. These limi a ions a e explained and e alua ed ( ig. 7). The ac ual implemen a ion o he me hod is de- sc ibed in (sec. 7). The implemen a ion was done o mee he ib a ion es ing c i e ia acco ding o [ 2 ], so he pa ame e s a e selec ed acco dingly. The gene a- o is able o gene a e no only he loga i hmic chi p sine signal, bu also he linea chi p and sine signal and is able o swi ch be ween hem ins an aneously and wi h minimal phase noise. Fu he mo e, he ac- ual equency o he sample is always known. The implemen a ion also deals wi h some ixed-poin gen- e a ed issues, such as he disc e e alues o he chi p speed o he equency ou side limi s, which makes i a e sa ile ool o di e en enginee ing a eas. 9. Conclusion This pape p esen s an uni e sal poin - o-poin me hod o chi p sine signal gene a ion on a ixed- poin FPGA. Di e ences be ween he loa ing and he ixed-poin gene a ion as well as he mos signi ican e o sou ces a e desc ibed. Mo eo e , he e alua ion o he minimal ixed-poin esolu ion and o e all e o o he me hod a e p esen ed. The gene a o is able o ins an aneously swi ch be ween chi p sine and sine signal wi hou any addi ional phase noise. The gene - a o has been ealized on Compac RIO 9067 and is used o ib a ion es ing om 10 Hz o 7 kHz wi h a minimal chi p speed o 1 oc /min . Ne e heless, he gene a o is e sa ile, he e o e i can be used in o he a eas wi h a di e en equency and speed ange. In he u u e, we would like o implemen a ib a ion con ol o he ixed-poin a i hme ic, so he whole p ocess will be on FPGA. Acknowledgemen s The comple ion o his pape was made possible by he g an No. FEKT-S-17-4234 - “Indus y 4.0 in au oma ion and cybe ne ics” inancially suppo ed by he In e nal science und o B no Uni e si y o Technology. Re e ences [1] R. L. Allen, D. W. Mills. Time, F equency, Scale and S uc u e. John Wiley & Sons, Inc., 2004. [2] IEC:60068-2-6. En i onmen al es ing: Tes s – Tes Fc: Vib a ion (sinusoidal), 2nd edn., 2007. [3] J. Vankka, K. A. Halonen. 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