Mem-Elements Emulator Design With Experimental Validation and Its Application

Received April 21, 2021, accepted May 4, 2021, date of publication May 7, 2021, date of current version May 17, 2021. Digital Object Identifier 10.1109/ACCESS.2021.3078189 Mem-Elements Emulator Design With Experimental Validation and Its Application NIRANJAN RAJ 1, (Graduate Student Member, IEEE), RAJEEV KUMAR RANJAN 1, (Member, IEEE), FABIAN KHATEB 2,3, AND MONTREE KUMNGERN 4 1Department of Electronics Engineering, Indian Institute of Technology (ISM) Dhanbad, Dhanbad 826004, India 2Department of Microelectronics, Brno University of Technology, 60190 Brno, Czech Republic 3Faculty of Biomedical Engineering, Czech Technical University in Prague, 3105 Kladno, Czech Republic 4School of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand Corresponding authors: Fabian Khateb ([email protected].cz) and Rajeev Kumar Ranjan (rajee[email protected]) This work was supported in part by the King Mongkut’s Institute of Technology Ladkrabang under Grant KREF026201, and in part by the Shastri Institutional Collaborative Research Grant (SICRG) under Grant MHRD (SICRG)/2020-2021/740/ECE. ABSTRACT An emulator circuit of Memristor, Memcapacitor, and Meminductor commonly termed as mem-elements has been demonstrated in this article. The circuit has been realized using the technique of current mode, which provides better performance over voltage mode counterparts. The current mode analog building blocks, along with a few passive components, have been used in the presented circuit implementation. The fingerprint characteristics have been observed in both simulation and experimental results, validating the theoretical analysis. The robustness of the presented design has been supported by performing different types of analysis like process corner, temperature, and non-volatility behavior. The mem-elements emulator design has been simulated using 0.18 µm TSMC process parameter, and ±1.2 V power supply has been used. The commercial ICs AD844 and CA3080 are used for the experimental demonstration of the proposed mem-elements design by making a prototype on a breadboard. A layout area of 4829 µm2, 8098 µm2, and 8061 µm2respectively is required for the Memristor, Memcapacitor, and meminductor circuit. The power consumed by the mem-elements circuit is also provided. A chaotic has been implemented using mem-elements to show the usefulness of the emulator design. INDEX TERMS Memristor, memcapacitor, meminductor, pinched hysteresis loop, Chua’s circuit. I. INTRODUCTION Memristor was originally postulated by Leon Chua in 1971 as the fourth passive circuit element describing the missing relationship between the magnetic flux (ϕ) and electric charge (q). The unique non-linear feature of the Memristor [1]–[6] was not observed in the existing basic passive elements. Chua’s paper caught the attention of worldwide researchers after the announcement of memristor fabrication in HewlettPackard (HP) laboratories using TiO2[1] by Williams et al. in 2008. The ideal characteristics of the memristive system [3]–[5] were postulated and derived by Kang. Memristor possesses three main characteristics [6], which can be stated as (a) pinched hysteresis loop in the current-voltage plane (b) an inverse relationship between the hysteresis curve area and frequency (c) memristor behaves like a linear resistor at The associate editor coordinating the review of this manuscript and approving it for publication was Di He . high frequency. Non-volatility is an important characteristic of an ideal memristor defined by preserving the memristance value when no input signal is applied. The emulator corresponds to a circuit that imitates the mem-element characteristics. Memcapacitor and Meminductor [4] have been derived from the concept of Memristor and possess similar properties of storing energy by virtue of its capacitance and inductance without power source requirement. The analog memory field finds newer technology advancements with the introduction of these mem-elements having wide application areas such as chaotic signal generators [7], [8], and many more. The relation of the time integral of charge (σ(t)) against the time integral of voltage (ϕ(t)) is the nature of memcapacitive elements. Meminductor has been put under the special category of memory element wherein the flux is taken as the time integral of induced voltage across the inductor. The memristor [9]–[14] emulator design in literature consists of several analog building blocks. In [9], the memristor circuit consists 69860 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ VOLUME 9, 2021 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application of 1 CBTA and 1 multiplier with few passive components which can work in only grounded conditions. The memristor circuit in [10] has been designed using MO-OTA having 3 ended outputs with few passive components, but it can only be configured in decremental configurations. In [11], the memristor design has been implemented using CCTA and CCII as an active block with few passive components which can work in only floating conditions. The memristor circuit using 2 CFOAs and 1 OTA with few passive components has been designed in [12], but it can only be configured in incremental configuration. In [13], BJT-based implementation of the memristor circuit has been done using 2 AD844 and 1 multiplier. The memristor design in [14] consists of CCII and OTA, but it can work in only grounded conditions. In this article, a memristor circuit has been proposed, which can be configured in both grounded as well as floating conditions and can be made to operate in both incremental as well as decremental configurations. The memcapacitor emulator [15]–[22] circuit in literature has been designed using different active blocks such as DXCCDITA [15], 4 CCIIs and 1 Op-amp [16], 3 CCIIs, 3 TOAs and 1 MR [17], 2 CCIIs, and 1 multiplier [18], 2 CCIIs and 1 MR [19], first design with 2 CCIIs, 1 multiplier and second design with CCII, OTA, multiplier [20] and 2 MO-OTAs and 1 multiplier [21]. The existing circuit in literature comprises either more number of active block or contains a multiplier, which makes the design complex, and it supplies around 1/10th of the product term that eventually results in a reduced loop area of the hysteresis curve. The memcapacitor design proposed in this article consists of 2 CCII and 1 OTA with few passive components without using any mutator or multiplier circuit. The meminductor [22]–[26] emulator circuit in literature has been designed using different analog active building blocks. The meminductor circuit in [22]–[25] consists of either a BJT-based circuit using more than one type of active block or a mutator-based design. In [26], the meminductor emulator has been designed using two OTAs out of which one simple output and one multi-output, one grounded capacitor and one floating capacitor, one grounded and one floating resistor, an analog multiplier. The circuit uses more commercial ICs to perform the experimental validation. The presented mem-elements circuit in [32] is complex due to the presence of more ICs and discrete components. The meminductor emulator design proposed in this article comprises 2 CCII and 1 OTA with few passive components and experimentally validated. Memristor (MR), memcapacitor (MC), and meminductor (MI) are commonly known as memelements. The design and implementation difficulty in fabricating these nanoscale devices is the main hurdle in the path of the emergence of these mem-elements in the near future. Hence, the study of simulation models and emulator circuits is necessary for exploring the application of these three mem elements. The application of mem-elements to chaotic [7], [8] circuits is an important research topic. Various chaotic oscillations have been generated by introducing a memristor emulator to different chaotic circuits. The characteristics of Memcapacitor and Meminductor supported by the simulation results indicate the potential of these memelements in chaotic and hyperchaotic phenomena. The objective of this paper is to provide the circuit implementation of all three mem-elements and their simulation and experimental validation. The proposed mem-elements design can be used to explore the real-world application without the need for a mutator. Moreover, the layout of the emulator design has been laid out, and the consumed chip area has been provided. At the same time, the power consumed by these mem-elements has also been provided. The presented design has been used in the implementation of the chaotic circuit for secure communication in order to show the usefulness of the design. II. BUILDING BLOCK AND ITS PROPERTIES The current mode circuit provides better performance to rival its voltage mode counterparts in a wide range of applications. The technique of the current-mode circuit has been utilized in the implementation of the presented mem-elements emulator design. Unlike their voltage mode counterparts, current conveyors offer high linearity, have a wider dynamic operating range, high-frequency range, and have a unity gain magnitude response. A CCII [28]–[31] is a three-terminal active element whose port relationship is given as IY=0,VX=VY,IZ=IX(1) Ideally, Z and Y nodes show infinite impedance, whereas the X node has a zero impedance. The input stage is the translinear voltage follower and an important part of CCII to obtain a large dynamic range. The output Z copies the current flowing through port X and is realized in the conventional manner using two complementary mirrors as current follower. The OTA is a voltage-controlled current source whose differential input voltage yields an output current by means of its transconductance (gm). The port relationship and transconductance parameter of OTA is given by IO±= ±gm(VP−VN),gm=k √2(VB−Vss −2Vth)(2) where kis a parameter of MOS device given by k=µnCOX W L Here, µndenotes the carrier mobility in the channel region while W/Land COX are the aspect ratio and oxide capacitance per unit area of the MOSFET, respectively. The CMOS-based schematic structure of CCII [28]–[31] and M-OTA [27] has been shown in Figure. 1 and Figure. 2, which is used to design the mem-elements emulator circuits. The aspect ratio of the MOS transistors used in the implementation of CCII and M-OTA is given in Table-1. III. MATHEMATICAL MODEL OF MEM-ELEMENTS AND CIRCUIT DESCRIPTION In this section, mem-elements emulator circuit design has been proposed, which consists of CCII and OTA as an analog VOLUME 9, 2021 69861 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application FIGURE 1. CMOS schematic structure of CCII. FIGURE 2. CMOS schematic structure of M-OTA. TABLE 1. Aspect ratio of MOS transistors. active building block with few passive elements, and their mathematical model has been discussed. The connections at the input terminal of OTA are interchanged in order to operate the emulator circuit in incremental and decremental configurations. The Memcapacitor and Meminductor emulator design has been presented without using the mutator or multiplier in order to explore the follow-up application of these mem-elements such as compatible memory elements for real-time applications. A. MEMRISTOR The presented circuit of a memristor emulator circuit design can be configured to work in both floating and grounded types and can operate in both incremental and decremental modes by interchanging the switch connected at the input terminal of OTA. The grounded circuit of a memristor emulator [24] has been extended by replacing OTA with multiple output OTA, and thus the circuit works in both floating and grounded environments. The incremental and decremental configuration has been provided by connecting the switch S to N terminal for incremental and switch S to P terminal for decremental while another input terminal of OTA is grounded. The proposed design of the emulator has been shown in Figure. 3. Considering the ideal behavior of the circuit operating in the incremental mode, A and B is the floating terminal of the presented design, the routine analysis yields the potential developed at the Z terminal of CCII is equal to the biasing voltage of M-OTA [27]. The potential at these terminals can be written as VZ=VB=ϕin RC (3) Since the switch is connected at the N terminal of M-OTA, the current flowing through the output terminal (O+) of M-OTA is the same but opposite in polarity to that of the input current. Using the transconductance equation (2), the memductance offered by the floating type Memristor emulator circuit in its incremental mode of operation can be written as W(ϕm)=Iin Vin = − k √2(VSS +2Vth)+k √2 ϕin RC (4) The grounded memristor design can be obtained by shorting terminal B to the ground. It can be deduced from equation (4) that the voltage or current signal applied across the Memristor controls the memductance value. The memductance consists of time-invariant and time-variant parts. The time-variant part FIGURE 3. Flux-controlled memristor emulator circuit. 69862 VOLUME 9, 2021 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application depends on the flux (ϕin), so it is flux controlled memristor emulator. The general expression of memductance for both incremental/decremental configuration for floating/grounded type emulator can be written as W(ϕm)=Iin Vin = ∓ k √2(VSS +2Vth)±k √2 ϕin RC (5) Negative sign in time-invariant part and positive sign in time-variant part corresponds to incremental configuration while positive sign in time-invariant part and negative sign in time-variant part corresponds to decremental configuration. Frequency response analysis of the presented memristor design has been performed when a sinusoidal signal Vin(t)=Amsin(ωt) has been applied where Amis the amplitude of the input signal, and ω=2πf is taken as the frequency value so as to study the frequency characteristics of the proposed Memristor emulator design. The memductance equation becomes W(ϕm)= − k √2(VSS +2Vth)+kAmcos (ωt−π) 2√2πfRC (6) It can be observed from equation (6) that there is an inverse relation of the time-variant part with frequency and capacitor. Therefore, the time-invariant part dominates over the timevariant part when the frequency is increased i.e., the Memristor starts to act like a linear resistor. Considering nonidealities and parasitic impedances present at the terminal of the analog building block, the port relationship of these blocks can be written as IY=0,VX=αVY,IZ=βIX,IO±= ±gm(γ1VP−γ2VN) (7) Ideally, the parasitic capacitances and resistances present in parallel to the terminals of the CCII and OTA are approximately equal to zero and infinity, respectively. The parasitic impedance at the X terminal of CCII tends to zero ideally. The parasitic resistances, capacitances, and nonidealities due to mismatching of transistors will influence the overall performance of the design. Req=R+RXand Ceq=C+Cz+CVB represent the equivalent resistance and capacitance. The memductance equation considering these parameters can be written as W(ϕm) = αβϕin ReqCeq −VSS −2Vthkγ2+ √2(8) It can be observed from equation (8) that the value of memductance is more affected at higher frequencies due to these errors and least affected at a lower frequency. B. MEMCAPACITOR The presented charge-controlled Memcapacitor emulator circuit has been designed using 2 CCII and 1 OTA with few passive elements. The general form of the charge controlled memcapacitor emulator with initial value as βand incremental/decremental term as αapproximated as (β±ασ(t))q(t). OTA plays a crucial role as a multiplier by exploiting the transconductance stage to attain the general form. The proposed design of Memcapacitor has been shown in Figure. 4. The incremental and decremental configuration has been provided by connecting the switch S to P terminal for incremental and switch S to N terminal for decremental while another input terminal of OTA is grounded. FIGURE 4. Charge-controlled memcapacitor emulator circuit. Considering the ideal behavior of the circuit operating in the incremental mode, the routine analysis yields that the current at terminal X and Z of CCII-1 is the same using port relationship equation (1), and this current is equal but 180◦ out of phase with the input current Iin. The current at the Z terminal of CCII-1flows into the capacitor C1since the Y terminal of CCII-2 is at high impedance, and therefore a potential is developed across the capacitor C1. The voltage at terminal X and Y of CCII-2 is equal to the voltage produced across capacitor C1since the Z terminal of CCII-1 is sorted with the Y terminal of CCII-2. The potential at these terminals can be written as VZ1=VY2=VX2= − 1 C1∫Iindt = −q(t) C1 (9) The current at terminal X and Z of CCII-2 is equal, and this current flows into the capacitor C2, and as a result, a potential is developed across the capacitor C2. The terminal Z of CCII-2 is sorted with the controlling voltage VBof OTA, and therefore the potential at these terminals is the same and can be written as VZ2=VB= − 1 C2∫q(t) R1C1 dt = − σ(t) R1C1C2 (10) where σ(t) is the time integral of charge in the above equation. The terminal X of CCII-2 is sorted with the terminal P of OTA in case of incremental configuration while another input terminal of OTA is grounded, and therefore the voltage at these terminals is the same as written in equation (9). The output current of OTA can be written as IO=gm(VP−VN)= −gm q(t) C1 (11) Using the transconductance (gm) expression written in equation (2) of OTA and replacing the value of VBwith equation (10) in it, the equation (11) can be re-written as IO= − k √2−σ(t) R1C1C2−VSS −2Vthq(t) C1 (12) VOLUME 9, 2021 69863 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application The output terminal of OTA is sorted with the Y terminal of CCII-1, which is at high impedance. Therefore, the output current of OTA flows into the resistor R2and a voltage is developed across the resistor R2. Using the port relationship written in equation (1), the voltage at terminal Y and X of CCII-1 is the same and it is equal to the applied input voltage. The potential at these terminals can be written as Vin =VY1=kR2q(t) √2C1 (VSS +2Vth)+kR2σ(t)q(t) √2R1C2 1C2 (13) On rearranging equation (13), the value obtained for memcapacitance is written as: C−1 M(q(t)) =Vin q(t)=kR2 √2C1 (VSS +2Vth)+kR2σ(t) √2R1C2 1C2 (14) It can be observed from equation (14) that the obtained memcapacitance follows the general form of charge-controlled Memcapacitor. In order to analyze the frequency behavior of the presented memcapacitor design, the emulator circuit is excited with an input current such that the charge developed across the Memcapacitor is q(t)=VMsin(ωt) where VMand ωrepresent respectively the signal amplitude and operating frequency. The equation (14) can be re-written as C−1 M(q(t)) =kR2 √2C1 (VSS +2Vth) +kR2VM √2R1C2 1C2ωcos(ωt−π) (15) It can be observed that equation (15) consists of linear timevarying and time-invariant parts. The linear time-variant part is inversely proportional to the frequency and therefore the linear time-invariant portion shows clear dominance over the linear time-variant counterpart as the frequency is increased. With frequency tending to infinity, the linear nature of the curve is produced between the charge and voltage. The magnitude of the time-variant memcapacitance term can be written as C−1 M(q(t)) =kR2VM √2R1C2 1C2ω=1 τf(16) where τ=2√2πR1C2 1C2/kR2VMrepresents the time constant of the Memcapacitor. It is this time constant that is responsible for controlling the loop area of the pinched hysteresis loop. Following cases shows the relationship between the time constant and input frequency: 1. When the frequency tends to infinity, the time-varying linear resistance vanishes that in turn reduces the Memcapacitor to its original capacitor behavior. 2. When τ=1/f indicates that the time constant and the input frequency are matched, leading to maximum pinched hysteresis loop. 3. When τ≤1/f indicates that the time constant of the Memcapacitor is fairly less than the frequency of the applied signal which eventually reduces the pinched hysteresis loop. Considering nonidealities and parasitic impedances present at the terminal of the analog building block in equation (7), the memcapacitance equation can be written as C−1 M(q(t)) =α2β1β2σ(t) Req1Ceq1Ceq2+VSS +2Vth ×kα1α2β1γ1Req2 √2Ceq1 (17) where Req1=(R1+RX) RP, Req2=RO+RY1, Ceq1=C1+CZ1+ CY2, Ceq2=C2+CZ2+CVB. It can be observed from equation (17) that the value of memcapacitance is more affected at higher frequencies due to these errors and least affected at a lower frequency. The memcapacitor can be designed as either a voltage-controlled memcapacitive system or charge controlled memcapacitive system. The circuit design can be implemented using both mechanisms and provides comparative results. C. MEMINDUCTOR The proposed flux-controlled Meminductor emulator circuit comprises two CCII along with a single OTA in addition to few passive components. Meminductor is amongst the three mem-elements having constitutive parameters such as flux (ϕ(t)), (ρ(t)) which is the integration of flux with respect to time and current (I(t)). The most common representation of the flux controlled Meminductor with initial values (β) along with an incremental/decremental part (α) is governed by relation I(t)=(β±αρ(t))ϕ(t). Capacitor plays a crucial role in providing the time integral of flux. The integration of voltage (ϕ) with respect to the time and time integral of flux (ρ) is essential for implementing the Meminductor circuit. The presented design of the Meminductor emulator circuit has been shown in Figure. 5. The circuit can be configured in both incremental and decremental configurations by connecting the switch S to N terminal for incremental and switch S to P terminal for decremental while another terminal of OTA is grounded. Considering the general model and ideal behavior of the circuit operating in the incremental mode, the routine analysis FIGURE 5. Flux-controlled meminductor emulator circuit design. 69864 VOLUME 9, 2021 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application yields the same voltage at the X and Y terminal of CCII-1 using the port relationship equation (1), and this voltage is equal to the applied input voltage. The current at terminal X of CCII-1 can be evaluated using resistor R1and the same current flows at terminal Z of CCII-1. Since the Z terminal of CCII-1 and Y terminal of CCII-2 is sorted and the Y terminal is at high impedance, therefore Z terminal current flows into the capacitor (C1), and a voltage is developed across it. The voltage at terminal X and Y of CCII-2 is equal to the voltage across the capacitor (C1) using the port relationship. The voltages at these terminals can be written as VX2=VY2=VC1=1 C1∫Vin R1 dt =ϕin R1C1 (18) The current at terminal X and Z of CCII-2 is the same and can be evaluated by using resistor R2. The current at terminal Z of CCII-2 flows into the capacitor (C2), and potential is developed across it. The terminal Z of CCII-2 is sorted with the externally controlled terminal VBof OTA, and therefore same voltage appears at these terminals, which can be written as VZ2=VB=VC2=1 C2∫ϕin R1R2C1 dt =ρ(t) R1R2C1C2 (19) The switch S is connected to terminal N of OTA for incremental configuration while the P terminal is grounded. The potential at terminal N of OTA is equal to the voltage across the capacitor (C1) given in equation (18). The output current of OTA is the same but opposite in polarity to that of the input current. The current at these terminals can be written as IO= −Iin = −gm ϕin R1C1 (20) Using the transconductance value of OTA given in equation (2) and replacing the value of VBin it using equation (19), the current equation (20) can be modified as Iin =k √2ρ(t) R1R2C1C2−VSS −2Vthϕin R1C1 (21) By rearranging the above equation, the obtained meminductance can be written as L−1 M(ϕ(t)) = − k √2R1C1 (VSS +2Vth)+kρ(t) √2R2 1R2C2 1C2 (22) The above equation represents the flux-controlled memristor. The incremental/decremental mode of operation can be achieved by appropriate switching between N and P terminals of OTA. The proposed emulator circuit has been designed without using the multiplier. The AD633 multiplier IC supplies around 1/10th of the product term that eventually results in a reduced loop area of the hysteresis curve. The transconductance term of the operational transconductance amplifier has been utilized to perform the multiplication operation. Using this method, the multiplication operation can be achieved without the need for the multiplier. Furthermore, the frequency behavior of the proposed Meminductor circuit design has been examined. Let us assume that the Meminductor circuit is stimulated with the voltage source so that the flux is stated as ϕ(t)=VMsin(ωt) where VMand ωrepresent the amplitude and frequency of the signal. The equation (22) can be re-written as L−1 M(ϕ(t)) = − k √2R1C1 (VSS +2Vth)+kVMcos(ωt−π) √2R2 1R2C2 1C2ω (23) It can be observed that equation (23) consists of linear timeinvariant and linear time-variant parts. The linear time-variant part is inversely proportional to the frequency, and therefore the linear time-invariant part dominates the time-variant part when the frequency increases. The magnitude of the time-varying meminductance term can be written as kVM √2R2 1R2C2 1C2ω=1 τf(24) where τ=2√2πR2 1R2C2 1C2/kVMis the time constant of the proposed Meminductor emulator circuit, which in turn controls the area of the pinched hysteresis loop. The relationship of the time constant with input frequency is examined for the following cases: 1. It can be seen that the linear time-variant part of meminductance value disappears as the frequency tends to zero. 2. The area under the pinched hysteresis curve will be maximum at τ=1/f. 3. There may be losses in the pinched hysteresis characteristic if the time constant is less than the signal frequency. Considering nonidealities and parasitic impedances present at the terminal of the analog building block in equation (7), the meminductance equation can be written as L−1 M(ϕ(t)) =α1α2β1β2ρ(t) Req1Req2Ceq1Ceq2−VSS −2Vth ×kα1β1γ2 √2Req1Ceq1 (25) where Req1=R1+RX, Req2=R2+RX2, Ceq1=C1+CZ1+CY2+ CN, Ceq2=C2+CZ2+CVB. It can be observed from equation (25) that the value of meminductance is more affected at higher frequencies due to these errors and least affected at a lower frequency. IV. MEM-ELEMENTS SIMULATION RESULTS AND DISCUSSION In this section, the performance and functional correctness of the mem-elements emulator circuit have been simulated in the analog design environment of the Cadence tool using TSMC 180 nm process with the supply voltage of ±1.2 V to justify the theoretical explanations. The complementary MOS-based internal structure and aspect ratios of the fundamental analog building block such as CCII and OTA are discussed in [27]. The CMOS implementation of the element contains transistors in the saturation region of operation. VOLUME 9, 2021 69865 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application A. MEMRISTOR RESULTS AND DISCUSSION The functional verification of the proposed design of floating/grounded memristor emulator of Figure 3 has been performed and simulated in the Analog Design Environment of Cadence Virtuoso using 180 nm TSMC standard CMOS process parameter with ±1.2 V as the nominal supply voltage. A sinusoidal signal of amplitude 800 mV at different frequencies has been applied across the Memristor to observe the frequency-dependent pinched hysteresis behavior. The value of passive components considered are R =25 kand C varies from 100 pF to 160 pF. The transient response of the proposed memristor emulator design has been shown in Figure. 6. The simulation has been performed at a different frequency as shown in Figure. 7. The lobe area under the hysteresis curve is inversely related to the frequency of the applied signal validating the theoretical analysis in equation (6). The inverse relation of the capacitor with the memductance has been shown in equation (6) and describes that the pinched hysteresis loop area decreases with an increase in the value of capacitance. The behavior of the presented emulator design at different temperatures has been analyzed at 1 kHz frequency as shown in Figure. 8. It can be observed that the hysteresis loop area of the Memristor has an inverse relation with the temperature level. It has been deduced that FIGURE 6. Transient response of the proposed memristor emulator. FIGURE 7. Frequency-dependent pinched hysteresis loop in a current-voltage plane at a different frequency. FIGURE 8. Frequency-dependent pinched hysteresis loop for different temperature. the operating temperature is responsible for the change in leakage current and therefore proportional to absolute temperature (PTAT) biasing voltage source is used to reduce the effect of leakage current on the pinched hysteresis loop. In order to verify the robustness of the presented design, corner analysis has been carried out to check its consequences on the memristor design as shown in Figure. 9. The pinched hysteresis loop has been obtained for different SS, TT, and FF corner analyses at the same temperature. It can be observed that the hysteresis loop area is small showing less current flow in the case of process corner SS while in the case of process corner FF, a comparatively larger loop area has been observed as expected. The non-volatility is another characteristic of the memristor circuit apart from the frequency dependency of the pinched hysteresis loop. The non-volatility property states that the Memristor holds its last memductance value for a long time when no input signal is applied. The non-volatility behavior of the Memristor has been verified by applying a pulse train with an amplitude of 800 mV having a pulse width of 25 ms and a time period of 100 ms across the Memristor as shown in Figure. 10. The non-volatile nature of the memductance has been noted, and it is inferred that the variation is negligible over the entire non-pulse period. FIGURE 9. Pinched hysteresis loop at different process corners. 69866 VOLUME 9, 2021 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application FIGURE 10. Memductance variation in incremental mode when a pulse train is applied across the emulator circuit. FIGURE 11. (a) Layout of memristor circuit (b) Pre and post-layout simulation results. The value of the memductance has been preserved in the absence of the input signal showing the non-volatility property of the proposed design. The layout of the proposed memristor emulator design has been laid out, and post-layout simulations have been performed as shown in Figure. 11 to check the parasitic impact on the overall performance. It consumes an effective layout area of 4829µm2. It can be observed that there is a slight variation in the hysteresis loop of pre and post-layout results showing the presence of parasitic. The total power consumption is 9.843 mW. B. MEMCAPACITOR In order to verify the theoretical aspect of the presented memcapacitor emulator design in Figure 4, simulation has been carried out in Cadence design environment software using 0.18 µm TSMC process with the supply voltage of ±1.2 V. The memristor input terminal is subjected to an AC sinusoidal input which yields a pinched hysteresis loop in the voltage-current plane. A similar loop is observed in the memcapacitor case across sinusoidal input voltage and the voltage across the capacitor. A sinusoidal signal of amplitude 800 mV at different frequencies has been applied across the memcapacitor emulator circuit to observe the frequency-dependent characteristic of the pinched hysteresis phenomena. The value of passive components considered R1=25 k, R2=1 kand capacitor varies from 30 pF to 300 pF. The capacitor voltage is taken across C1. Figure. 12 shows the frequency-dependent characteristic of the pinched hysteresis curve of Memcapacitor at different frequencies. It can be observed that the area spanned by pinched hysteresis loop of proposed memcapacitor emulator design shows an inverse relation with the frequency validating the theoretical proposition. An increase in the frequency suppresses the linear time-varying part in comparison to the linear timeinvariant part, thereby validating the equation (15). At very high frequency, the area under the C-V curve decreases, and the Memcapacitor now replicates its original behavior. In order to verify the robustness of the presented design, corner analysis has been studied and carried out in order to validate the effectiveness of the memcapacitor design as depicted in Figure. 13. The pinched hysteresis loop is thus obtained for different process corners such as SS, TT, SF, and FF at room temperature. It is seen that the hysteresis loop area is small, showing less current flow in the case of process corner SS while in the case of process corner FF, a comparatively larger loop area has been observed as expected. The behavior FIGURE 12. Pinched hysteresis loop at a different frequency 500 kHz, 600 kHz, 700 kHz, and 800 kHz. VOLUME 9, 2021 69867 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application FIGURE 13. Pinched hysteresis loop obtained at different process corner SS, TT, SF, and FF. FIGURE 14. Frequency-dependent pinched hysteresis loop at different temperature. of the presented memcapacitor emulator design at different temperatures has been analyzed at 500 kHz frequency as shown in Figure. 14. It can be observed that the emulator design is still operational within acceptable limits. The layout of the proposed memcapacitor emulator design has been laid out, and post-layout simulations have been done as shown in Figure. 15 to check the parasitic impact on the overall performance. It has a layout area of 8098 µm2. The pre and post-layout outcomes show a slight variation in the hysteresis loop, which indicates the presence of parasitic as observed from the graph. The total power consumption is 14.741 mW. C. MEMINDUCTOR For the justification of theoretical explanations, the proposed design of the Meminductor emulator circuit shown in Figure. 5 has been simulated in ADE (Analog Design Environment) of Cadence Virtuoso design software using 180 nm TSMC standard CMOS process under the supply voltage of ±1.2 V. A sinusoidal signal of amplitude 800 mV at different frequency has been applied across the Meminductor circuit to observe the frequency-dependent pinched hysteresis behavior. The value of passive components considered FIGURE 15. (a) The layout of memcapacitor emulator circuit (b) Pre and post-layout simulation results. FIGURE 16. Transient response of Meminductor at 50 kHz. R1=15 k, R2=75 kand capacitor varies from 30 pF to 300 pF. The transient analysis of the proposed meminductor design has been carried out as shown in Figure. 16 with the sinusoidal input of amplitude 800 mV at 50 kHz frequency. It can be observed that there is a 90 degree phase shift in the obtained flux waveform with respect to the applied input voltage waveform. The transient response has been performed 69868 VOLUME 9, 2021 N. Raj et al.: Mem-Elements Emulator Design With Experimental Validation and Its Application RAJEEV KUMAR RANJAN (Member, IEEE) was born in India, in 1979. He received the M.Tech. and Ph.D. degrees from the Indian Institute of Technology (ISM) Dhanbad, Dhanbad, India, in 2007 and 2016, respectively. He is currently an Assistant Professor with the Department of Electronics Engineering, Indian Institute of Technology (ISM) Dhanbad. He has published more than 34 articles in esteemed journals and more than 34 papers in esteemed conferences. His main research interests include communication and VLSI signal processing circuits and systems. FABIAN KHATEB received the M.Sc. and Ph.D. degrees in electrical engineering and communication, and the M.Sc. and Ph.D. degrees in business and management from the Brno University of Technology, Czech Republic, in 2002, 2003, 2005, and 2007, respectively. He is currently a Professor with the Department of Microelectronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, and the Department of Information and Communication Technology in Medicine, Faculty of Biomedical Engineering, Czech Technical University in Prague. He has authored or coauthored over 100 publications in journals and proceedings of international conferences. He holds five patents. His research interest includes new principles of designing low-voltage low-power analog circuits, particularly biomedical applications. He is a member of the Editorial Board of Microelectronics Journal,Sensors,Electronics, and Journal of Low Power Electronics and Applications. He is an Associate Editor of the IEEE ACCESS,Circuits, Systems and Signal Processing,IET Circuits, Devices and Systems, and International Journal of Electronics. He was a Lead Guest Editor for the Special Issues on Low Voltage Integrated Circuits and Systems on Circuits, Systems and Signal Processing, in 2017, IET Circuits Devices and Systems, in 2018, and Microelectronics Journal, in 2019. He was also a Guest Editor for the Special Issue on Current-Mode Circuits and Systems; Recent Advances, Design and Applications on International Journal of Electronics and Communications, in 2017. MONTREE KUMNGERN received the B.S.Ind.Ed. degree in electrical engineering from the King Mongkut’s University of Technology Thonburi, Thailand, in 1998, and the M.Eng. and D.Eng. degrees in electrical engineering from the King Mongkut’s Institute of Technology Ladkrabang, Thailand, in 2002 and 2006, respectively. Since 2007, he has been a Lecturer with the Department of Telecommunications Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang. From 2010 to 2017, he was an Assistant Professor. He is currently an Associate Professor. He has authored or coauthored over 200 publications in journals and proceedings of international conferences. His research interests include analog and digital integrated circuits, discrete time analog filters, non-linear circuits, data converters, and ultralow-voltage building blocks for biomedical applications. VOLUME 9, 2021 69875