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Trabajo Fin de Máster Máster en Ingeniería de Sistemas e Informática Efficient instruction and data caching for high-performance low-power embedded systems Alexandra Ferrerón Labari Director: Darío Suárez Gracia Ponente: Jesús Alastruey Benedé Grupo de Arquitectura de Computadores (GAZ) Departamento de Informática e Ingeniería de Sistemas Escuela de Ingeniería y Arquitectura Universidad de Zaragoza Curso 2011/2012 Septiembre 2012 Abstract Although multi-threading processors can increase the performance of embedded systems with a minimum overhead, fetching instructions from multiple threads each cycle also increases the pressure on the instruction cache, potentially harming the performance/consumption ratio. Instruction caches are responsible of a high percentage of the total energy consumption of the chip, which for battery-powered embedded devices becomes a critical issue. A direct way to reduce the energy consumption of the first level instruction cache is to decrease its size and associativity. However, demanding applications, and specially applications with several threads running together, might suffer a dramatic performance slow down, or even increase the total energy consumption of the cache hierarchy, due to the extra misses incurred. In this work we introduce iLP-NUCA (Instruction Light Power NUCA), a new instruction cache that replaces the conventional second level cache (L2) and improves the Energy–Delay of the system. We provided iLP-NUCA with a new tree-based transport network-in-cache that reduces both the cache line service latency and the energy consumption, regarding the former LP-NUCA implementation. We modeled in our cycle-accurate simulation environment both conventional instruction hierarchies and iLP-NUCAs. Our experiments show that, running SPEC CPU2006, iLP-NUCA, in comparison with a state–of–the–art high performance conventional cache hierarchy (three cache levels, dedicated L1 and L2, shared L3), performs better and consumes less energy. Furthermore, iLP-NUCA reaches the performance, on average, of a conventional instruction cache hierarchy implementing a double sized L1, independently of the number of threads. This translates into a reduction of the Energy–Delay product of 21%, 18%, and 11%, reaching 90%, 95%, and 99% of the ideal performance for 1, 2, and 4 threads, respectively. These results are consistent for the considered applications distribution, and bigger gains are in the most demanding applications (applications with high instruction cache requirements). Besides, we increase the performance of applications with several threads without being detrimental for any of them. The new transport topology reduces the average service latency of cache lines by 8%, and the energy consumption of its components by 20%. i Resumen ejecutivo Los procesadores multi-hilo pueden incrementar el rendimiento de sistemas empotrados con una mínima sobrecarga en área y energía. Buscar instrucciones de varios hilos cada ciclo, no obstante, incrementa la presión en la cache de instrucciones, lo que potencialmente puede afectar el ratio rendimiento/energía. Las caches de instrucciones además son responsables de un porcentaje muy alto del total de la energía consumida por el chip, aspecto crítico para dispositivos alimentados por baterías. Una forma directa de reducir el consumo energético del primer nivel de cache de instrucciones es reducir su tamaño y asociatividad. Sin embargo, aplicaciones con demandas mayores, y especialmente aplicaciones multiprogramadas con varios hilos, pueden sufrir una drástica reducción del rendimiento, o incluso un incremento de la energía total consumida por la jerarquía de memoria cache, debido a los fallos adicionales. En este trabajo introducimos iLP-NUCA (Instruction Light Power NUCA), una nueva cache de instrucciones teselada que reemplaza la cache convencional de nivel 2 (L2) y mejora el Energy–Delay del sistema. Además proponemos una nueva red de transporte para iLP-NUCA con topología en forma de árbol que reduce tanto la latencia media de servicio, como la energía consumida por la red de transporte, en comparación con implementaciones previas de LP-NUCA. Hemos implementando en un entorno de simulación que modela en detalle los parámetros de la microarquitectura, jerarquías convencionales de cache de instrucciones e iLP-NUCAs. Nuestros experimentos demuestran que, ejecutando SPEC CPU2006, iLP-NUCA, en comparación con una jerarquía típica convencional de alto rendimiento (tres niveles de cache, L1 y L2 separados, L3 compartido), obtiene mayor rendimiento y consume menos energía. Aún más, iLP-NUCA consigue alcanzar el rendimiento, en media, de una jerarquía convencional reduciendo el tamaño del primer nivel de cache de instrucciones a la mitad, independientemente del número de hilos. Esto se traduce en una reducción del producto Energy–Delay del 21%, 18% y 11%, alcanzando el 90%, 95% y 99% del rendimiento de una cache de instrucciones perfecta, con 1, 2 y 4 hilos, respectivamente. Estos resultados son consistentes para la distribución de las aplicaciones consideradas y las mayores mejoras se dan en las aplicaciones que más estresan la jerarquía de instrucciones. Además en aplicaciones con varios hilos, el incremento en rendimiento se consigue sin perjudicar a ninguna de las aplicaciones. La nueva red de transporte reduce la latencia media de servicio de bloques un 8%, y reduce el consumo energético de los componentes de la red un 20%. iii iv Contents 1 Introduction 1 1.1 ScopeoftheProject .................................. 2 1.2 Objectives........................................ 2 1.3 Masters Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Contributions...................................... 3 1.5 Acknowledgements ................................... 3 2 Instruction cache hierarchies for embedded systems 5 2.1 State–of–the–art cache hierarchies for embedded systems . . . . . . . . . . . . . . 5 2.2 Performance and energy on a state–of–the–art embedded processor . . . . . . . . 6 2.3 Our proposal: instruction Light Power – NUCA . . . . . . . . . . . . . . . . . . . 8 2.3.1 Tree-based transport network for iLP-NUCA . . . . . . . . . . . . . . . . 9 3 Methodology 11 3.1 Processorbaseline ................................... 11 3.1.1 Memory hierarchy overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Simulator ........................................ 12 3.3 Workloads........................................ 13 3.4 Metrics ......................................... 13 4 Results 15 4.1 Impact of the tree-based transport network . . . . . . . . . . . . . . . . . . . . . 15 4.2 First level instruction caches: performance/energy trade-offs . . . . . . . . . . . . 16 4.2.1 Energy consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 Performance................................... 17 4.2.3 Energy-Delay.................................. 19 4.2.4 Summary .................................... 23 4.3 Putting all together: instructions and data . . . . . . . . . . . . . . . . . . . . . . 23 4.4 L1-Iaccesslatency ................................... 23 4.5 Resultssummary.................................... 24 5 Related Work 25 6 Conclusion and future work 29 6.1 Publications....................................... 30 6.2 FutureWork ...................................... 30 References 33 v CONTENTS A Project management 39 B Simulation environment and methodology 41 B.1 SMTScalar ....................................... 41 B.1.1 The microarchitectural model . . . . . . . . . . . . . . . . . . . . . . . . . 42 B.2 Simulationmethodology................................ 42 C SPEC CPU2006 characterization: instruction cache requirements 45 C.1 Cache size and associativity implications in performance . . . . . . . . . . . . . . 45 C.1.1 L1-I misses per k-instruction . . . . . . . . . . . . . . . . . . . . . . . . . 45 C.1.2 Performance evaluation: IPC . . . . . . . . . . . . . . . . . . . . . . . . . 48 D Shared iLP-NUCA designs 51 E ILP-NUCA: Cache de Instrucciones Teselada para Procesadores Empotrados 53 vi List of Tables 2.1 Cache hierarchy parameters of representative current high-end processor samples (28-45nm). ....................................... 6 3.1 Simulator micro-architectural parameters. . . . . . . . . . . . . . . . . . . . . . . 11 vii 4 Chapter 2 | Instruction cache hierarchies for embedded systems This chapter presents the design space for instruction cache hierarchies and introduces our proposal (iLP-NUCA) to simultaneously improve performance and save energy in single thread and SMT embedded systems. Superscalar execution cores demand a continuous instruction supply to feed their functional units [ 26 , 46 ]. Instruction flows might be interrupted by dependencies between instructions, breaks in the control flow (due to branches), and wait states generated by cache misses. Delays due to the instruction cache hierarchy affect the instruction flow speed and the instruction issue, and hence, performance. Simultaneous multi-threading (SMT) is a well-known technique to hide long latency operations by the execution of several threads [ 52 ]. SMT aims to have all the functional units highly utilized by using a more powerful front-end (fetch unit) supplying instructions from several threads. Although SMT can be implemented with a minimum energy and area overhead, it adds pressure to the front-end, and instruction caches become a critical component in the system design. Ideally we would like to have an instruction cache big enough to fit the working set of the most demanding applications, in order to increase their hit rate. However, bigger caches come at the expense of higher access times and higher power and energy consumption. Thus, there is a complex trade-off between size, and latency and energy consumption. In the following sections we will present current design choices for instruction caches in commercial systems. We will evaluate in terms of performance and energy consumption the behavior of potential applications using SPEC CPU2006 [ 21 ] for a state–of–the–art processor. Finally, we will present our proposal, iLP-NUCA, and its enhancements over previous designs. 2.1 State–of–the–art cache hierarchies for embedded systems Embedded systems cover a wide range of applications and domains. Table 2.1 collects information about representative commercial system-on-chips (SoCs) from several vendors. As we can see, instruction cache sizes vary between 16KB (Qualcomm MSM 8960 [ 17 ]) and 64 KB (Netlogics XLP864 [ 18 ]), while most of the caches are 32KB. Associativities of this processors usually vary between 2 and 8, being 4 a commonly adopted solution [53, 35, 3, 7]. Many of the embedded systems we can find nowadays such as smartphones, tablets, or multimedia players, are portable devices. These devices are usually powered by batteries, so energy consumption becomes more important, turning into a critical issue. Instruction caches are 5 CHAPTER 2. INSTRUCTION CACHE HIERARCHIES FOR EMBEDDED SYSTEMS Table 2.1: Cache hierarchy parameters of representative current high-end processor samples (28-45 nm). Model,Brand #threads/CPU L1/CPU (KB) L2/CPU L3 (MB) I D QorIQ AMP T2080,Freescale [7] 2 32 32 512KB 512KBa PowerPC 476FP,IBM–LSI [35] 1 32 32 512KB 2MB + 4 eDRAM Cortex-A15 MPCore,ARM [53] 1 32 32 up to 4MB shared no XLP864,NetLogic [18] 4 64 32 512KB 16MB shared MSM 8960,Qualcomm [17] 1 16b16b512KB no MIPS32 ProAptiv,MIPS [13] >1 32-64c32-64cup to 1.3MB no aPlatform cache. bL0 cache 4KB. cOptional 4KB–1MB scratchpad. responsible of a high amount of energy consumption of the system. To cite some examples, the StrongARM SA-100 consumes the 27% of its total energy in the instruction cache [ 38 ], and ARM 920TTM dissipates 25% of the power in its instruction cache [45]. Some recent works claim that the applications executed in this kind of devices have high requirements on instructions and therefore would benefit from a big first level instruction (L1-I) cache [ 10 , 16 ]. Others maintain that requirements of instruction caches are small [ 32 , 50 , 41 , 33 ]. SPEC CPU2006 is a benchmark suite highly utilized by academia and industry, composed by 29 applications, including artificial intelligence, compilation, compression, and speech recognition, among others [ 21 ]. This kind of applications are commonly employed in the embedded domain. We consider that SPEC CPU2006 covers a wide range of applications of different disciplines and therefore can represent the behavior of this domain applications. 2.2 Performance and energy consumption evaluation on a state– of–the–art embedded processor We run SPEC CPU2006 benchmarks with a typical state-of-the-art processor configuration including a 32KB 4–way set associative first level instruction cache, dedicated L2 cache (i.e., separated data and instruction L2 caches), and a shared L3 cache. We assume 32nm technology and run experiments with 1, 2, and 4 threads. For more details please refer to Chapter 3, Methodology. Our experiments show that only a small subset of applications from the suite take advantage of such a big instruction cache. In concrete, from the 28 benchmarks considered 1 , half of them keep performance reducing the cache size and associativity by 2 (i.e., 16KB 2–way set associative cache). Nine of them even keep the same performance with a 4KB 2–way set associative cache. However, those applications from the set that have a big instruction footprint experiment a huge slow-down. For example, 11 of the benchmarks slow down more than 20% when reducing the cache to 4KB 2–way. When running 2 threads, 15% of the mixes keep performance when the cache is 4KB 2–way, and 30% does it when 16KB 2–way. Again the slow down of applications with high requirements is dramatic. A more detailed characterization in terms of instruction requirements of SPEC CPU2006 can be found in Appendix C. Although many applications fit in a small instruction cache, the performance loss of applications with high requirements is not acceptable to satisfy the user experience. 1483.xalancbmk could not be executed in our simulation environment. 6 2.2. PERFORMANCE AND ENERGY ON A STATE–OF–THE–ART EMBEDDED PROCESSOR Instruction cache size and associativity have also a high impact on the energy consumption of the structure. Figure 2.1 shows the energy consumption of the memory hierarchy for 1, 2, and 4 threads. For the sake of clarity, we show they dynamic energy consumption of each structure, and group the total static energy consumed. The latter value is small in comparison with the total energy as we consider LSTP (Low STandby Power) technology. We keep all the parameters the same and vary the first level instruction cache size and associativity. We consider four configurations: CV–32KB–4ass (32KB, 4–way associative), CV–16KB–2ass, CV–8KB–2ass, and CV–4KB–2ass. Each bar corresponds to one configuration, and represents the sum of the total energy consumed by all the applications considered. 0 20 40 60 80 100 120 Energy (mJ) CV-32KB-4ass CV-16KB-2ass CV-8KB-2ass CV-4KB-2ass 1 thread 0 500 1000 1500 2000 2500 3000 3500 2 threads 0 2000 4000 6000 8000 10000 12000 14000 16000 4 threads L1-I dyn L1-D dyn L2-I dyn L2-D dyn L3 dyn Total static Figure 2.1: Dynamic energy consumption of the memory hierarchy for several L1 sizes/associativities for 1, 2, and 4 threads. Each bar corresponds to a configuration. Names of configurations include the size of the cache and the associativity. For example: CV–32KB-4ass means conventional hierarchy, 32KB 4–way set associative L1-I cache. If we focus on one thread, we can draw several conclusions. As we said before, many of the applications have a working set that fits within a 32KB 4–way set associative L1 instruction cache. This implies that all the requests hit in the first level (L1-I) and there is no need to fetch instructions from the next one (L2-I). The instruction cache consumes 32.5% of the memory hierarchy energy. The dynamic energy consumption of the L2-I is negligible (less than 1% of the total). As the L1-I cache shrinks, the dynamic energy per access also decreases (for example, with 4KB the percentage of energy consumption due to the L1-I is 13.5%). Per contra, the amount of blocks that the cache can hold is smaller, so the probability of a miss is higher. If we continue shrinking the L1-I cache there is a point where this reduction does not pay off. We can see that when the cache size is less than 8KB, the reduction on the energy consumption of the L1-I is smaller than the increase of the energy consumption of the L2-I, which at the end increases the total energy consumption of the system. With two threads the scenario is similar, although the reductions are smaller as the cache requirements are bigger. If we consider four threads we can see how just reducing the cache to 16KB implies that the total energy consumption increases. 7 CHAPTER 2. INSTRUCTION CACHE HIERARCHIES FOR EMBEDDED SYSTEMS Potentially, reducing the first level instruction cache, as MSM 8960 does [ 17 ], is going to benefit the system from the energy point of view. But reducing the size of the L1-I will affect also its hit rate, which heavily affects performance. Yet the energy consumption of the L2-I cache will increase, counteracting the other savings. Summing up, we would like to reduce the L1-I size and associativity to reduce the energy consumption of the system but without increasing the energy consumption of the L2-I, and losing as less performance as possible. With this idea in mind, recent works proposed to dynamically reconfigure the L1 size and associativity so only part of the ways or part of the sets are used in a given moment [ 50 , 8 , 15 ]. With such approach the cache adapts to the behavior of the application and can operate with the optimal size. Other works proposed to add a small structure before or next to the first level cache to capture part of the accesses to the L1-I and increase the fetch speed, reduce the energy consumption, or both [ 32 , 29 ]. A different approach is to rely on the compiler to map cache lines in a given structure or a given way/set of the cache [6, 27]. All these techniques need to either modify the interface between the L1-I and the processor, or add additional hardware or software support. We propose a different approach. We will not modify the fetch unit or the L1-I structure, but we will optimistically reduce the size and associativity of the first level instruction cache. We will substitute the L2 cache by an improved and energy efficient structure, iLP-NUCA (instruction Light Power NUCA), based on the LP-NUCA design, which will minimize the performance degradation without increasing the energy consumption of the system. In the following section we will explain this structure in more detail. 2.3 Our proposal: instruction Light Power – NUCA LP-NUCAs [ 47 ] extend the conventional first-level cache capacity by surrounding it with one or more levels of small cache tiles interconnected by specialized networks, as shown in Figure 2.2. LP-NUCA levels 123 from next cache level processor to next cache level 35 53 3 4 6 7 56 4 6 6 7 RT Figure 2.2: 3-level LP-NUCA. The numbers inside tiles represent the tile hit latency seen by the processor (assuming single-cycle tiles). The first level of LP-NUCA (root-tile, RT) corresponds to a conventional L1 cache with additional control logic. We substitute the second level of the conventional hierarchy by a tiled structure whose effective access time increases gradually. The numbers inside tiles represent the minimum hit latency of a tile seen by the processor. We define the minimum hit latency of a tile 8 2.3. OUR PROPOSAL: INSTRUCTION LIGHT POWER – NUCA as the time since we inject a request into the LP-NUCA until the block is actually served by that tile (i.e., received by the root-tile). The LP-NUCA design is characterized by the use of three specialized networks: search, transport, and replacement, which allow for a simple implementation and provide low latency and high bandwidth. Please refer to [ 47 ] for further details about the design and implementation of LP-NUCAs. This structure has been proved to be efficient with data hierarchies, achieving high performance and reducing the energy consumption of the system. LP-NUCAs are good candidates for instruction hierarchies because they exploit the reuse (temporal locality), are energy-efficient structures, and provide a lot of bandwidth to the root-tile. Besides they do not change the interface between the L1 and the processor. We call this structure adapted to instruction hierarchies iLP-NUCA (instruction Light Power NUCA). We expect that the use of iLP-NUCAs in the instruction hierarchy will allow for great reductions in energy consumption, at the same time that it will allow us to keep performance losses in an acceptable range. In the following section we will describe the enhancements from the baseline design that we propose. 2.3.1 Tree-based transport network for iLP-NUCA Previous designs of LP-NUCA utilized a 2-D mesh for the transport network because it provides high bandwidth with its multiple return paths to the root-tile. Figure 2.3 shows the 2-D mesh topology (Figure 2.3a) and the transport components inside a tile (Figure 2.3b). The numbers inside the tiles represent the tile latency assuming one-cycle tiles. This topology provides an increasing latency as we move further away from the root-tile. The main components of the transport network are the two transport buffers (Tbf) and the switch. In a given moment only three of the five inputs can be active in the crossbar (the contents among tiles are in exclusion, and therefore hits cannot happen simultaneously in the replacement buffers, Rbf in the Figure 2.3b, and the cache), which simplifies its design. We rely on buffered flow control, and use store-and-forward flow control with on/off back-pressure and two-entry buffers per link. LP-NUCA levels 123 from next cache level processor 35 53 3 4 6 7 56 4 6 6 7 RT (a) 2-D Mesh transport network. on/off control links CACHE T bf T bf R bf R bf T bf T bf (b) Transport components. Figure 2.3: 2-D Mesh transport network and its components. The numbers inside the tiles represent the tile latency assuming one-cycle tiles. Tile latency includes search, tile access, and transport delay. The main components shown in Figure 2.3b are the transport buffers (Tbf), the replacement buffers (Rbf), the cache, and the switch. 9 CHAPTER 2. INSTRUCTION CACHE HIERARCHIES FOR EMBEDDED SYSTEMS LP-NUCA levels 123 from next cache level processor 35 53 3 3 5 5 55 3 5 5 5 RT (a) Tree-based transport network. on/off control links CACHE T bf T bf R bf R bf T bf (b) Transport components. Figure 2.4: Tree-based transport network and its components. The numbers inside the tiles represent the tile latency assuming one-cycle tiles. Tile latency includes search, tile access, and transport delay. The main components shown in Figure 2.4b are the transport buffers (Tbf), the replacement buffers (Rbf), the cache, and the switch. In comparison with the former 2-D Mesh, the number of output links has decreased and so does the complexity of the switch. We already observed that the occupancy of the transport network links is very low [ 48 ]. Thus, we could decrease the path diversity in order to reduce the nodes degree. Figure 2.4 shows an alternative transport network based on a tree topology, and the transport components inside a tile (Figures 2.4a and 2.4b, respectively). With this topology the benefit is twofold. On one hand we decrease the links between tiles: now each tile only has one transport output link (before they had two), simplifying the crossbar design. On the other hand, we decrease the tile hit latency, especially for the tiles of higher levels, as we need less hops to reach the RT (which also means that we will consume less energy to deliver blocks to the root tile). Thus, we expect to reduce the effective service latency of blocks in comparison with previous LP-NUCA designs, and the energy consumption of the transport network. The novel topology slightly increases the length of some wires, but it does not affect the tile cycle time because both search and replacement networks have less slack. It also increases the degree of the root-tile crossbar from 3 to 5 inputs without performance impact. To start the execution of a refill instruction, we only need to notify the MSHR (miss status holding register) which entry is going to be written. The MSHR will notify then the Issue Window that launches the refill instruction, and that is the time when the data will be necessary. We can take advantage of these cycles to pass through the root-tile crossbar. From now on, we will assume that iLP-NUCA refers to the structure with this novel transport network. Next chapters will show the detailed evaluation of a processor where we substitute the conventional L2 for a iLP-NUCA, and how it behaves in comparison with a conventional hierarchy. 10 Chapter 3 | Methodology This chapter presents the methodology followed in this project. We briefly present the modeled processor, the simulation methodology and environment, the benchmarks utilized, and the metrics used to evaluate them. For more information please refer to Appendix B. 3.1 Processor baseline For our experiments, our simulator models the system summarized in table 3.1. We based our model in typical state-of-the-art high performance embedded systems such as IBM/LSI PowerPC 476FP, NetLogic XLP864, and Freescale QorIQ AMP T2080 [ 35 , 18 , 7 ]. Our system has a more powerful memory hierarchy, and it is able to execute up to 4 threads simultaneously. Table 3.1: Simulator micro-architectural parameters. BS, AM, lat, and init stand for block size, access mode, latency, and initiation rate, respectively Clock Frequency 1 GHz Threads 1/2/4 Fetch/Decode/Commit width4 Issue width 4(IN+ME) + 2FP INT/FP/MEM IW entries 24/16/ 16 ROB/LSQ entries 64/32 Branch Predictor bimodal + gshare, 16 bitMiss. branch penalty 6 L1/L2/L3 MSHR entries 8 / 8 / 4 MSHR secon. misses 4 TLB miss latency 30 Store Buffer/L2/L3 WB sizea32/16/16 Baseline L1/root-tileb32KB–4Way–32B BS, write-through, 2-cycle lat, 1-cycle init L2c512KB–8Way–32B BS, serial AM, 4-cycle lat, 2-cycle init, copy-back iLP-NUCA rest of tiles 32KB–2Way–32B BS, parallel AM, copy-back, levels: 3, total size: 448KB L3 4MB eDRAM–16Way–128B BS, 14-cycle lat, 7-cycle init, copy-back Main Memory 100 cycles/4 cycle inter chunk, 16 Byte bus aL2, iLP-NUCA, and L3 Write Buffers coalesce entries. bIn root-tile, copy-back and write-around. cL2 dedicated for data and instructions. We estimate conventional cache access latencies and energy consumption assuming 32nm LSTP (Low STandby Power) technology with Cacti 6.5 [ 40 ]. Cacti is an integrated cache access time, cycle time, area, leakage, and dynamic power model. By integrating all these models together, cache trade-offs are all based on the same assumptions and, hence, are mutually consistent. Besides, the latencies provided by Cacti are typically lower than the ones achieved in commercial products, thus our assumptions are conservative. For iLP-NUCA latencies and energy estimations we use both CACTI 6.5 and a scaled 90nm layout [47]. 3.1.1 Memory hierarchy overview Figure 3.1 shows our baseline, a conventional three level cache hierarchy with dedicated first and second level caches, and with a third level shared between data and instructions. First level 11 CHAPTER 3. METHODOLOGY caches are true multiported (2 read/write ports). Second and third level caches are multi-banked, and have one read/write port. All caches use LRU (least recently used) but LP-NUCA, that employs LRF (least recently filled). L3-0 L3 MSHR to/from main memory L3-1 L2D-1 L2D MSHR L2D-0 L2I-0 L2I-1 L2I MSHR L1-D L1D MSHR Ports Ports L1-I L1I MSHR Figure 3.1: Baseline system modeled: cache hierarchy detail. For the sake of brevity, only the loads path is shown, omitting structures for stores. L1 (baseline) and L2 caches are based on state-of-the-art commercial embedded systems (Table 2.1). For the shrunk L1-I configurations we decided to keep associativity in 2 as a compromise between energy consumption and performance in SMT applications [22]. We chose to model a separated L2 design for several reasons. First, we want to examine the behavior of the instructions and therefore we do not want data to interfere on it. In some of our experiments we will consider that the L1 data cache always hits. Second, dedicated caches offer higher performance, although they occupy more area. Finally, the implementation of a shared iLP-NUCA is not straightforward, and it is currently ongoing work. We assume for the L2 serial access mode (tag array is accessed before the data array). We modeled with CACTI 6.5 L2 caches with smaller size (128 KB), and the results show that the size reduction does not affect either the access time or initiation rates (4 and 2 cycles, respectively). Reducing the L2 size would potentially reduce its energy consumption. However smaller L2 cache sizes might suffer higher miss rates, increasing the amount of accesses to the L3, and affecting both the performance of the system, and the energy consumption. 3.2 Simulator We use SMTScalar, a cycle-accurate execution-based simulator based on SimpleScalar 3.0d for Alpha ISA [ 4 ]. SimpleScalar was heavily extended to support detailed microarchitectural models, highly configurable memory hierarchies, and simultaneous multi-threading execution for previous LP-NUCA works [ 48 , 47 ]. We extended SMTScalar to add instruction cache hierarchies. We 12 3.3. WORKLOADS provided a realistic instruction fetch unit, and we evaluated the optimal values for the structures involved by both an extensive review of literature and state–of–the–art commercial processors, and experimentation with our simulation environment. More details about our simulated architecture and methodology can be found in Appendix B. 3.3 Workloads We use the full SPEC CPU2006 [ 21 ] benchmark suite, but 483.xalancbmk (which we could not execute in our environment). For each program we simulate 100M representative instructions that were selected following the SimPoints methodology [ 19 ]. One thread experiments warm up cache and branch predictor during 200M instructions. Multi-thread experiments are multiprogrammed and we utilize last as simulation ending policy; there is no structure warming up and we only obtain statistics for the first 100M of instructions of each thread. For 2 SMT experiments we run all the combinations of benchmarks. For 4 SMT experiments, we assure the representativity of the results by following a methodology based on statistical sampling that allows for 97% of confidence level and between 3% error [25, 54, 49]. 3.4 Metrics We use performance metrics for multiprogrammed workloads including misses per k-instructions (mpki), average memory access latency (AMAT), IPC throughput (i.e., committed user instructions summed over all threads divided by total elapsed cycles 1 ), and fairness [ 12 ]. IPC throughput and fairness are calculated according to the following formulas: IP C througput = n X i=1 IP Ci, fairness = min iCP IM P i CP ISP i max iCP IM P i CP ISP i where CP I refers to instructions per cycle, and MP and SP refers to single-thread and multi-thread execution, respectively. Other metrics such as weighted speed up, ANTT (average normalized turnaround time), or STP (system throughput), were not utilized because we consider different baselines [9]. Regarding energy consumption, we report the total energy consumed as well as the Energy– Delay and Energy–Delay 2 products. We follow the Li et al. approach for SMT environments [ 34 ], and account for all the energy consumed until the last thread commits 100M instructions. 1The use of IPC throughput is save in our environment because we have no synchronization instructions. 13 CHAPTER 4. RESULTS Similar conclusions can be drawn for ED 2 , yet the impact of the performance degradation (delay) affects more the conventional hierarchy. In conclusion, in terms of ED and ED 2 , iLP-NUCA on average performs better than a conventional hierarchy independently of the L1-I size and the number of threads. Untill now we have shown the average values of ED and ED 2 . To examine in more detail the behavior of our structure we will see the distribution of ED for all the applications considered. We want to see how iLP-NUCA performs against the conventional hierarchy. To do that, we take as baseline the best configuration of conventional caches: for 1 thread, 2 threads and 4 threads the best conventional configuration (on average) are CV–8KB–2ass, CV–16KB–2ass, and CV–32KB–4ass, respectively. Figure 4.4 contains three graphs. The upper one presents the distribution of ED normalized to the 1 thread baseline (CV–8KB–2ass). The graph in the middle shows the absolute ED. The graph in the bottom of the figure shows the L1-I mpki (misses per k–instruction). We plot the baseline CV–8KB–2ass, and three of the iLP-NUCA configurations: iLP–16KB–2ass, iLP–8KB–2ass, and iLP–4KB–2ass. Benchmarks are sorted according to the L1-I mpki of the baseline. 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ED normalized ILP-4KB-2ass ILP-8KB-2ass ILP-16KB-2ass CV-8KB-2ass 0.00 0.05 0.10 0.15 0.20 0.25 0.30 ED (mJ*s) 434.zeusmp 470.lbm 462.libquantum 447.dealII 437.leslie3d 433.milc 473.astar 481.wrf 456.hmmer 410.bwaves 436.cactusADM 401.bzip2 450.soplex 435.gromacs 429.mcf 464.h264ref 471.omnetpp 465.tonto 459.GemsFDTD 453.povray 400.perlbench 416.gamess 403.gcc 444.namd 482.sphinx3 458.sjeng 454.calculix 445.gobmk 0 20 40 60 80 100 120 L1-I mpki Figure 4.4: ED distribution for 1 thread applications. Names of configurations include the size of the cache and the associativity. For example: CV–32KB–4ass means conventional hierarchy, 32KB 4–way set associative L1-I cache. Data cache always hits. The upper graph represents ED values normalized to the best conventional configuration (baseline CV–8KB–2ass). The graph in the middle represents the absolute ED values. ED is a the lower–the–better metric. The lower graph represents the L1-I mpki. Benchmarks are sorted according to the L1-I mpki of the baseline (CV–8KB–2ass). If we pay attention to the upper graph we can see how for the same L1-I cache size (8KB, 2–way set associative) iLP-NUCA always have the same or a smaller relative ED value (below 1). The performance (in terms of ED) of the iLP-NUCA is better when the mpki values of the 20 4.2. FIRST LEVEL INSTRUCTION CACHES: PERFORMANCE/ENERGY TRADE-OFFS applications are bigger. The lower graph sorts the SPEC CPU2006 benchmarks from small values to big mpki values for the baseline configuration. The first 11 applications on the left hand side of the graph fit in a 8KB cache (their mpki is close to 0). Therefore the energy consumption of the 8KB cache is smaller than the 16KB cache, as each access to the cache consumes less energy. When the application does not fit anymore in the 8KB instruction cache, 16KB configuration takes advantage of its larger capacity and reduces its relative ED. The right hand side of the graph shows applications with high mpki. We can see how iLP-NUCA performs better in this kind of applications as it can exploit its full potential to reduce the ED. The behavior of the 4KB 2–way set associative cache is too irregular due to the small capacity. Figures 4.5 and 4.6 are the equivalent graphs for 2 and 4 threads applications. Regarding two threads applications, again for the same L1-I cache size iLP-NUCA shows a relative ED below the baseline. Also the difference increases as we move to the applications that show a higher aggregated L1-I mpki (right hand side of the graph). If we reduce the cache size to 8KB 2–way set associative, for applications with low L1-I mpki we achieve a large reduction in ED, as the aggregated footprint fits in the first level cache. In some applications with high L1-I mpki values ILP–8KB–2ass has a relative value over the baseline. Nevertheless, in most of the applications iLP-NUCA reduces the relative ED product with an instruction cache with half of the capacity. Thus, the reduction in ED is consistent among all the applications with two threads. 0 50 100 150 200 250 300 350 0.5 1.0 1.5 2.0 2.5 ED normalized ILP-4KB-2ass ILP-8KB-2ass ILP-16KB-2ass CV-16KB-2ass 0 50 100 150 200 250 300 350 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ED (mJ*s) 0 50 100 150 200 250 300 350 0 50 100 150 200 250 L1-I mpki Figure 4.5: ED distribution for 2 threads applications. Names of configurations include the size of the cache and the associativity. For example: CV–32KB–4ass means conventional hierarchy, 32KB 4–way set associative L1-I cache. Data cache always hits. The upper graph represents ED values normalized to the best conventional configuration (baseline CV–16KB–2ass). The graph in the middle represents the absolute ED values. ED is a the lower–the–better metric. The lower graph represents the L1-I mpki. Benchmarks are sorted according to the L1-I mpki of the baseline (CV–16KB–2ass). Figure 4.6 shows all the mixes considered in our experiments for 4 threads applications. The 21 CHAPTER 4. RESULTS best conventional configuration in this case is a L1-I cache of 32KB 4–way set associative, so we consider the iLP-NUCA configurations iLP–32KB–4ass, iLP–16KB–2ass, and iLP–8KB–2ass. 4KB 2–way set associative first level instruction cache shows a very irregular pattern and it is too small to hold the aggregated instruction footprint of four applications. The same pattern as in previous figures can be observed. For the same size, iLP-NUCA performs better in terms of ED, and this differences are clearer as the aggregated L1-I mpki increases (applications on the right hand side of the graph). Shrinking the cache size to 16KB improves the ED product for those applications with low L1-I mpki. The relative ED product of this configuration (ILP–16KB–2ass) in general is below the baseline with some exceptions that rarely go beyond 10% increase, and usually reaches 20% decrease, until mix 350, approximately. Then the values swing around the baseline without big differences until approximately mix 500, where the relative ED is increased in some points by 20%. For most of the applications iLP-NUCA with a 16KB 2–way set associative instruction cache improves the ED of a conventional hierarchy with a 32KB 4–way set associative first level instruction cache. For more than half of the applications, iLP-NUCA with a L1-I 8KB 2–way set associative cache also outperforms a conventional hierarchy with four times more capacity and the double of the associativity. 0 100 200 300 400 500 600 700 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ED normalized ILP-8KB-2ass ILP-16KB-2ass ILP-32KB-4ass CV-32KB-4ass 0 100 200 300 400 500 600 700 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ED (mJ*s) 0 100 200 300 400 500 600 700 0 50 100 150 200 250 300 350 400 L1-I mpki Figure 4.6: ED distribution for 4 threads applications. Names of configurations include the size of the cache and the associativity. For example: CV–32KB–4ass means conventional hierarchy, 32KB 4–way set associative L1-I cache. Data cache always hits. The upper graph represents ED values normalized to the best conventional configuration (baseline CV–32KB–4ass). The graph in the middle represents the absolute ED values. ED is a the lower–the–better metric. The lower graph represents the L1-I mpki. Benchmarks are sorted according to the L1-I mpki of the baseline (CV–32KB–4ass). 22 4.3. PUTTING ALL TOGETHER: INSTRUCTIONS AND DATA 4.2.4 Summary To summarize the results presented in this section, we can conclude that iLP-NUCAs are able to improve performance over conventional designs when the L1-I has the same size, and yet reduce the energy consumption. Even more, iLP-NUCA with a root-tile of 8KB, 2–way set associative achieves, on average, the performance of a conventional hierarchy with a 16KB, 2–way set associative cache, independently of the number of threads, and reduces the energy consumption by 21%, 18%, and 11%, for 1, 2, and 4 threads, respectively. With a 8KB, 2–way set associative root-tile, iLP-NUCA reaches 90%, 95%, and 99% performance of an ideal first level instruction cache. We have seen also that these results are consistent among the applications and that iLP-NUCA outperforms conventional caches specially in environments with high L1-I mpki (misses per k-instruction). 4.3 Putting all together: instructions and data The results we have presented so far consider that data caches always hit. In this section we will examine the behavior of the complete system considering the same memory hierarchy model: a three level cache hierarchy, with L1 and L2 dedicated caches (i.e., separated for instructions and data), and shared L3. In iLP-NUCA configurations we substitute each L1/L2 for a 3 level iLP-NUCA (one iLP-NUCA for data, and one iLP-NUCA for instructions). The detailed microarchitectural parameters can be found in Table 3.1 (Chapter 3). To describe the behavior of the complete system we chose ED and ED2metrics. Figure 4.7 shows Energy-Delay (Figure 4.7a) and Energy-Delay 2 (Figure 4.7b) products normalized to the baseline (CV–32KB–4ass) when the data cache is not perfect. The graphs show the same tendency as before and similar conclusions can be derived. A conventional hierarchy reduces ED and ED 2 when we reduce the L1-I cache to 16KB and 8KB for 1 thread applications, and increases for 4KB. With 2 and 4 threads shrinking the L1-I cache translates into bigger ED and ED 2 values. iLP-NUCA, on the other hand, keeps ED and ED2 below the conventional baseline and improves for 16KB and 8KB. The ED and ED 2 values increase for for 4KB L1-I but still they are below the conventional ones. Several observations must be made. There are two factors that influence the drastic reduction in Energy–Delay. • The energy savings. The energy savings are double by the combination of instruction iLP-NUCA and data iLP-NUCA. • The performance increase. iLP-NUCA and its new transport network provide cache lines with a minimum latency taking great advantage of their temporal reuse. We detected that benchmarks with high slow downs in performance are bounded by stores. The higher iLP-NUCA bandwidth helps to increase the stores speed. In conclusion, the system take advantage of faster instructions paths, faster data paths, and higher bandwidth to commit stores. 4.4 L1-I access latency The decrease on the L1-I cache size and associativity influences the access latency and initiation rate of the cache. We modeled the different cache configurations with CACTI 6.5 [ 40 ] and our experiments show that for the given technology and cycle time (LSTP, 1 GHz) the access latency of the cache is never less than 2 cycles. 23 CHAPTER 4. RESULTS 1 thread 2 threads 4 threads 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ED normalized to baseline CV-32KB-4ass CV-16KB-2ass CV-8KB-2ass CV-4KB-2ass ILP-32KB-4ass ILP-16KB-2ass ILP-8KB-2ass ILP-4KB-2ass (a) Energy–Delay product for 1, 2, and 4 threads, several configurations. Values are normalized to baseline (CV– 32KB–4ass). 1 thread 2 threads 4 threads 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ED 2 normalized to baseline CV-32KB-4ass CV-16KB-2ass CV-8KB-2ass CV-4KB-2ass ILP-32KB-4ass ILP-16KB-2ass ILP-8KB-2ass ILP-4KB-2ass (b) Energy–Delay 2 product for 1, 2, and 4 threads, several configurations. Values are normalized to baseline (CV–32KB–4ass). Figure 4.7: ED (Figure 4.7a) and ED 2 (Figure 4.7b) products for 1, 2, and 4 threads. Each bar corresponds to one configuration. Values are normalized to baseline (CV–32KB–4ass). Names of configurations include the size of the cache and the associativity. For example: CV–32KB–4ass means conventional hierarchy, 32KB 4–way set associative L1-I cache. ED and ED2are the lower–the–better metrics. Assuming that technology allows for accessing the L1-I cache in 1 cycle, we run experiments for different configurations of L1-I with both conventional and iLP-NUCA based hierarchies. Our results show that, as expected, the lower latency improves the performance of the system. However, the tendency remains, and the same conclusions extracted for 2-cycle access latencies can be observed. Furthermore, an instruction cache with 1-cycle access latency could request a cache line per cycle to the L2 in case of a batch of misses. iLP-NUCA can inject one miss per cycle and offers more bandwidth than a conventional hierarchy. Thus we also expect iLP-NUCA to perform better in this kind of scenario. 4.5 Results summary To sum up, we have seen that first level instruction caches are responsible of a high percentage of the total energy consumption. We observed that by reducing the size and associativity of the L1-I we consume less energy, but at the expense of a non acceptable performance degradation. We proposed to utilize for instructions hierarchies LP-NUCAs with a new transport network (iLP-NUCAs). This new transport network effectively reduces the average service latency of the blocks and the energy consumption of the network. We also saw how iLP-NUCA achieves better performance than conventional hierarchies for the same configuration of L1-I, independently of the number of threads, and without being detrimental for any of them. Furthermore, it can achieve the same performance than a conventional hierarchy with smaller L1-I cache sizes, which allows for great energy reductions. In any case we observed that the optimal results in terms of Energy–Delay, on average, are those given by a 8KB 2–way set associative L1-I cache. The results are consistent for data, where we observed a twofold benefit due to the instructions and the data iLP-NUCAs. 24 Chapter 5 | Related Work Several works addressed the instruction cache energy consumption problem by adding hardware structures that are able to capture a great amount of instruction fetches. Kin et al. proposed the Filter cache, a small direct mapped conventional cache placed before the first level instruction cache (L1-I) that trades off performance for power [ 32 ]. If the instruction request hits in the filter cache, the access is faster and consumes less energy. However, if the fetched instruction misses in the filter cache, we incur in a penalty delay for accessing the L1-I. Thus, although a 256-byte direct mapped filter cache achieves a 58% energy reduction, the performance loss is about 21%. To cope with the extra delay incurred when a miss occurs in the filter cache, Jung et al. proposed to add a small cache (EM-cache) next to the L1-I instead of before [ 29 ]. In this way, some of the accesses will go to the L1-I and some of them will save energy by accessing only the EM-cache. The key idea is to detect if following instructions access the same cache block than the last instruction fetched. In this case, we can directly access the EM-cache. However, if we want to capture a bit more complicated patterns, we need to add instructions to the ISA and rely on the compiler to indicate the hardware when to access each structure. In a similar way, Bellas et al. proposed the L-cache [ 6 ]. The L-cache contains instructions within a loop, so that iterations of the loop will fetch instructions from the L-cache rather than from the instruction cache, saving great amount of energy. As the compiler decides which blocks are kept in the L-cache, the performance loss in much lower. The energy savings are directly related to the amount of large blocks within loops, and the amount of times that those blocks are executed. Therefore this technique works well for floating point workloads, but the energy savings are lower in the case of integer workloads. Trace caches follow a similar idea, although their main concern is increasing performance. Dynamic instruction streams are kept in an additional hardware structure to avoid noncontiguous fetches [ 43 ]. They were implemented in the Pentium 4, where they store already decoded microoperations, or translations of complex x86 instructions, which had a positive impact by reducing the energy consumption of the machine [44]. All these proposals (and others like [ 57 , 56 ]) add extra hardware structures between the processor and the first level instruction cache. Their goal is to reduce the amount of accesses to the L1-I, but at the expense of introducing extra fetch latency when a miss to these structures occurs. On the contrary, we keep clear the interface between the processor and the L1 instruction cache, and therefore, all these designs are orthogonal to ours, and they could be easily implemented in front of our system. Besides, these works do not consider multi-thread environments, where threads interfere with each other and may pollute the filter structure. Aragon et al. proposed a technique to reduce the power consumption of CAM-based instruction cache designs with high associativity [ 2 ]. The key observation is that not all the instructions fetched are executed due to taken branches. They implement a prefetch mask to avoid fetching instructions from a block that will not be used. 25 CHAPTER 5. RELATED WORK Associativity tends to have a strong impact on power consumption on modern high-performance low-power embedded systems. First level caches of such systems usually have associativity varying from 2 to 8. For example: 2–way for ARM Cortex A15 [ 53 ], 4–way for IBM PowerPC 476FP [ 35 ] and ARM Cortex A9 [ 3 ], or 8–way for the Freescale QorIQ AMP T2080 [ 7 ]; in comparison with the 32-way associative L1-I cache used in Aragon’s work. Furthermore, CAMs generally have about twice the area of SRAM cells and tend to consume a large amount of power because the matchlines are heavily loaded and have an activity factor close to 1 [ 55 ]. These structures are preferred for TLBs (translation lookaside buffers), as they require a high-speed table look-up. They are also especially popular in network routers (where they are very useful for IP classification and forwarding). Although SMT get more benefit from associativity than from size [ 14 ], our experiments conclude that instruction caches with associativities between 2 and 4 work well while they keep a reasonable energy consumption. Other proposals also exploit the varying requirements of instruction caches not only among programs, but also among phases of the same program, to reduce the cache energy consumption. There are some techniques to selectively place some of the unused cache lines into a low-leakage, state-preserving or switched-off state [ 11 , 30 , 42 ]. These approaches are straightforward applicable to our system and can account for additional energy savings. Ishihara et al. proposed to relax the cache uniformity constraint to reduce the dynamic power consumption and the leakage power [ 24 ]. They developed both a non-uniform cache architecture which varies the number of ways per set, and a code placement algorithm to reduce cache accesses and cache misses. Other similar works that focus on analyzing cache requirements at run-time are [1, 8, 15, 58]. A recent proposal from Sundararajan et al. is Smart cache, a reconfigurable cache that adapts dynamically to the requirements of each program/phase [ 50 ]. They proposed a way to dynamically reconfigure the cache parameters (size and associativity) at run-time based on the behavior on the application with a machine learning decision tree model. This model is applicable to all the cache levels. They reduce the energy-delay product with an overall performance degradation of 2%. All these proposals imply important design changes in the structure of the caches. The key advantage is that the variable L1-I size or associativity allows to capture big working sets of demanding applications and at the same time reduce energy when the requirements are small. The main performance losses come when the prediction of a certain optimal size is wrong (smaller than it should) and the L1-I cannot capture all the accesses. iLP-NUCA works as a distributed victim cache which backs up the L1-I. We believe that the combination of a reconfigurable cache approach and our iLP-NUCA would achieve high energy reductions while keeping performance. Other proposals take advantage of the compiler to place blocks in an specific location of the cache. Jones et al. proposed to place frequently executed code at the start of the program binary and explicitly place these instructions in a particular way [ 27 ]. Thus, in a given access, the processor would be able to detect that the request is aimed to the selected instructions, and only one way and one set will need to be accessed. Similar proposals are [36, 23]. All these approaches are orthogonal to our design, as we do not modify the interface between the processor and the first level cache. Victim caches [ 28 ] have also been studied as energy saving structures [ 37 , 5 ]. Memik et al. proposed to put a victim cache before the L2 and enhance its behavior by a predicting schema. This schema would tell us if a block is not in the victim cache, or per contra is likely to be 26 there [ 37 ]. In this way they can save some of the accesses to the victim cache that will not produce a hit. Our experiments show that a conventional victim cache (8-16 entries) is not enough to capture the instruction footprint and produce a significant improve in performance. This work does not consider SMT applications neither. Several threads running together and sharing a small victim cache would interfere each other by evicting other threads victim blocks. Besides, iLP-NUCA is far more complex than a conventional victim cache and its networks-in-cache offer a fast communication with the L1 cache and lots of bandwidth. 27 28 Chapter 6 | Conclusion and future work Although multi-threading processors can increase the performance of embedded systems with a minimum overhead, fetching instructions from multiple threads each cycle also increases the pressure on the instruction cache. Instruction caches are responsible of a high percentage of the total energy consumption of the chip, which for battery-powered embedded devices becomes a critical issue. In this Master’s Thesis we proposed to reduce the size of the first level instruction cache to achieve significant energy reductions. We proposed iLP-NUCA, an energy efficient tiled structure, that substitutes a conventional first and second level caches, for the instruction hierarchy, We provide iLP-NUCA of a new transport network-in-cache that reduces the average service latency of blocks by 8%, and the energy consumption of the network. We compare our proposal with a state-of-the-art conventional three level cache hierarchy, where L1 and L2 are dedicated (separated for instructions and data), and L3 is shared. To evaluate both proposals we implemented them in our simulation environment, providing it of instruction cache hierarchies and a realistic fetch unit. We run experiments of representative applications (SPEC CPU2006) for the two structures (conventional and iLP-NUCA), varying the L1-I cache size and associativity, for 1, 2, and 4 threads. From these experiments we can extract the following conclusions: • First level instruction caches energy consumption represents an important percentage of the total energy consumed by the memory hierarchy. • By reducing the L1-I cache size we can achieve great energy reductions. However, we suffer from a non acceptable performance degradation. • In a system with ideal data caches, iLP-NUCA in comparison with a conventional hierarchy performs better and consumes less energy for the same L1-I size, independently of the number of threads. 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