Circuit modeling of a MEMS varactor including dielectric charging dynamics

Circuit Modeling of a MEMS Varactor Including Dielectric Charging Dynamics P Giounalis 1 , D Andrade-Miceli 1 , S Gorreta 2 , J Pons-Nin 2 , M Dominguez-Pumar 2 and E Blokhina 1 1 School of Electrical, Electronic and Communications Engineering, University College Dublin, Dublin, Ireland 2 Micro and Nano Technologies Group Electronic Engineering Department, Technical University of Catalonia, Barcelona, Spain E-mail: [email protected] Abstract. Electrical models for MEMS varactors including the eect of dielectric charging dynamics are not available in commercial circuit simulators. In this paper a circuit model using lumped ideal elements available in the Cadence libraries, and a basic Verilog-A model, has been implemented. The model has been used to simulate the dielectric charging in function of time and its eects over the MEMS capacitance value. 1. Introduction Capacitive Micro-electromechanical Systems (MEMS) oer excellent performance combining mechanical and electrical components. They are the manufacturing of a wide variety of applications such as sensors, resonators, switches, ultrasonic transducers and varactors [1,2]. However, their micro-scale size brings a number of reliability issues which prohibit their mass commercialization [3]. In particular, MEMS variable capacitors (varactors) suer from deviations of their capacitance-voltage (C-V) characteristic. Their performance is limited by the dielectric charging eect which is an inherent reliability problem for these devices. The build-up process of trapping charges into the dielectric layer, can be treated as an oset voltage connected in series with the MEMS, provoking a voltage shift in the characteristic curve. To remove this trapped charge, techniques which apply bipolar width-modulated voltage pulse sequences have been recently introduced and tested with good results [4,5,6]. In modern circuit design the integration of MEMS with CMOS technology is a challenging step in micro-scale evolution. Computer aided design (CAD) tools play a signicant role in the design and analysis process of chips [7,8]. However, the complexity of MEMS, including failure mechanisms and reliability behavior, makes the modelling and simulation of chips which include these devices a task of high complexity. In this paper, we present an adaptive system to implement a control method for the restriction of the dielectric charge of a MEMS varactor. The system's reliability relies highly on the MEMS capacitance measurement accuracy and resolution [9,10]. Therefore, an accurate real-time measuring of the capacitance value is essential. Electrical models for MEMS varactors including the eect of dielectric charging dynamics are not available in commercial circuit simulators. That is, here, for rst time, we will focus in the implementation of a complete circuit model of a MEMS varactor using lumped ideal elements available in the Cadence libraries along with a basic Verilog-A model. The model has been used to simulate the dielectric charging in function of time and its eects over the MEMS capacitance value. 2. Statement of the Problem The complete description of the bipolar control method to deal with the dielectric charging issue is out of the scope of this study (for a full description see [4]). Here, we will only present briey the whole system and we will focus mainly in the circuit modelling of the MEMS varactor, which is a crucial component for the successful design and simulation of the chip. The system consists of a closed control loop as shown in Fig. 1and it aims to restrict the build-up charge in the insulator of the MEMS varactor. Briey, it works as follows: The value of the MEMS capacitance Cm is compared with the value of the reference capacitor Cr . Then the error signal e is fed to analogue processing stage which amplies the capacitance dierence. Finally, the output is converted into a digital word. This digital output is then used by the FPGA to set the duty cycle, and the polarity of the voltage to be applied to the MEMS using the DC voltage source VB . The control loop is grouped into dierent sets: the MEMS varactor, ASIC Cm+ Cr analog digital FPGA VB +e − Figure 1: Control loop basic description at block level the ASIC, the FPGA and the bias voltage. The ASIC consists of the input stage (including the reference capacitor), the analogue processing and the digital conversion. The FPGA reads and saves the digital output from the ASIC, and actuates the DC voltage, VB . The capacitance dierence measurement, the analogue processing and the digital conversion are performed inside the ASIC to reduce the second order eects and deviations introduced by parasitics. Since the accumulation of the dielectric charge is time dependent, in order to have reliable simulations for the ASIC design, is essential to include an electrical model for the MEMS that not only reects the voltage dependence, but also the charge dynamics. 3. MEMS varactor DC model The MEMS varactor consists of a moveable electrode which deects due to the presence of an electrostatic force, and a xed bottom electrode which includes a thin dielectric layer on the top (for a detailed description see [6,11]). The device operates in two regimes, the contact-less operation (below pull-in) and the contacting (ON) operation (beyond pull-in). Pull-in denotes the value of the voltage where the varactor changes mode of operation. The behavior of the MEMS C-V characteristic in the contact-less regime can be approximated by a parabola, eq. (1), whilst eq. (2) can be used to simulate the operation of the device in the regime beyond pull-in. Below pull-in: Cm(V) = C0+aV 2 (1) Beyond pull-in: Cm(V) = b1−b2 √V (2) Here, the values C0 , a , b1 and b2 can be calculated by the tting of experimental data. These equations were integrated into a Verilog-A script to simulate the MEMS in a simulator for electric circuits. Fig. 2visualizes the curve tting along with the simulation results obtained with the use of a Verilog-A model. The C-V curve for the Verilog-A model was simulated with the use of basic circuit consisting of the MEMS model itself, connected to a DC power supply and performing a DC sweep in Cadence ADE-L. −20 −15 −10 −50510 15 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VB(V) Cm(pF) num sim Cmva ncm Cm(V) pcm Figure 2: MEMS C(V) : numerical simulation in solid blue, cadence simulation in dashed red. VB=Vpcm −Vncm . 4. Equivalent electrical model for the dielectric charge dynamics In principle, the charge dynamics of the dielectric is a complex dynamical procedure which can include more than one mechanisms [12] In this study, we will use a semi-empirical multiexponential model (for a complete description see [13,14]). The total charge consists of positive and negative multi-exponential components, in the most general case. Those components evolve in time, in principle, with dierent time constants, depending also on the polarity and the value of the applied voltage: Qp(t) = Qp max Piζp ie−t/τp Di V > 0 Qp max(1 −Piζp ie−t/τp Ci )V < 0 Qn(t) = Qn max(1 −Piζn ie−t/τn Ci )V > 0 Qn max Piζn ie−t/τn Di V < 0 (3) where Qp max is the maximum value of the positive charge component, Qn max the maximum value of the negative charge component, τCi and τDi the charging and discharging time constants and ζi coecients which express the contribution of each exponential to the total charge. By denition Piζi= 1 for each component. It is seen from this model that the time varying expression of the total charge Qd(t) in the dielectric is given as: Qd(t) = Qp(t) + Qn(t) = Pqp n+Pqn n , and it is the sum of multiple independent charge components. For the simulations of this paper, a two exponential model have been used. Based on the form of this equation set, an equivalent electrical network consisting of resistors and capacitors can be found, see eqs.(4) and (5) (where for simplicity we use only two components, but these expressions can be easily generalized): Qcp =Cc1pV(1 −e −t Cc1pRc1p) + Cc2pV(1 −e −t Cc1pRc1p) (4) Qdp =Cd1pV e −t Cd1pRd1p+Cd2pV e −t Cd1pRd1p (5) where the same sub-indexing rules for the positive and negative components apply. Note that the value of voltage V can be set arbitrarily because is not directly related with the bias voltage applied to the MEMS. The values for R and C can be calculated in order the values between the numerical model and the corresponding electrical equivalent model to be matched. It must be taken into account that: Switched RC Network C1n φ Rc1nφRd1n C2n φ Rc2nφRd2n C1p φ Rc1pφRd1p C2p φ Rc2pφRd2p Vb Vc1p Vc2p Vc1n Vc2n φφ Figure 3: Equivalent switched RC network modelling the RF MEMS dielectric charging dynamics. VCVS nvc + − Vc2n·Avc2n + − Vc2p·Avc2p + − Vc1n·Avc1n + − Vc1p·Avc1p pvc Vc1pVc1nVc2pVc2n Figure 4: VCVS to generate equivalent Vsh . Comps + − A∞·VB φ + − −A∞·VB φ Vn Vp Figure 5: Comparators to generate φ−φ . Switched RC VCVS Cmva Comps n p Figure 6: MEMS integrated model • for positive bias , the capacitors C1p & C2p are charged to a positive voltage through the resistors Rc1p & Rc2p , respectively; and simultaneously, the capacitors C1n & C2n are discharged from the previous stored voltage (if exists) through the resistors Rc1n & Rc2n • for negative bias , the capacitors C1p & C2p are discharged through the resistors Rd1p & Rd2p , respectively; and simultaneously, the capacitors C1n & C2n are charged through the resistors Rc1n & Rc2n That is, the equivalent circuit must be switched according with these rules, and the control signals must be derived from the voltage applied to the MEMS. The equivalent switched RC network is shown in Fig. 3. The analog switches are modeled using Verilog-A with very high o-resistance, zero on-resistance and threshold voltage of 0.1mV . The resulting switched RC network models the dielectric charging and discharging times according to the applied voltage polarity. Moreover, in order to convert the voltage stored in every capacitor into an equivalent votlage shift, it must be amplied by a gain factor determined by the ratio between the corresponding capacitor in the network and the MEMS dielectric capacitance Cd . Once amplied, the resulting voltages must be added to calculate the total voltage shift. This must be connected to Cm as a voltage oset source. To perform these tasks, a series-connected Voltage Controlled Voltage Sources (VCVS), every of them sensing the voltage on every capacitor and with the corresponding gain factor, is implemented, as depicted in Fig. 5. This source array is connected to the negative terminal of Cmva . In order to generate the control signals φ−φ , two ideal comparators made of VCVS 0 200 400 600 800 −3 −2 −1 0 Time(s) V(V) Vn1num Vn1sim Vn2num Vn2sim Figure 7: Negative charge contribution to Vsh 0 200 400 600 800 0 1 2 Time(s) V(V) Vp1num Vp1sim Vp2num Vp2sim Figure 8: Positive charge contribution to Vsh 0 200 400 600 800 −4 −2 0 2 Time(s) V(V) Vsh−pnum Vsh−psim Vsh−nnum Vsh−nsim Vsh num Vsh sim Figure 9: Positive and negative voltage shift and total Vsh −5 0 5 V(V) VB −1 −0.5 0 0.5 V(V) Vsh−p Vsh−n Vsh−t 0 20 40 0.1 0.2 0.3 0.4 Time(s) C(pF) Cm Figure 10: MEMS capacitance for a pulse voltage. −20 −10 0 10 20 V(V) VB −2 0 2 V(V) Vsh−p Vsh−n Vsh−t 0 20 40 60 80 100 0.2 0.4 0.6 0.8 Time(s) C(pF) Cm Cmno dielect. charging Figure 11: MEMS capacitance for a ramp voltage. has been included. Comparators have extremely high voltage gain, no hysteresis, threshold voltage of 0.1mV , minimum voltage of 0V , and maximum voltage output of 1V . The voltage applied to the MEMS integrated electrical model, between the node pcm in Cmva and node nvc in V CV S block, is used as control voltage for the comparators. When the polarity is positive and larger than 0.1mV , φ is high and φ is low. When the polarity changes, the signals switch their values. Finally, the whole MEMS electrical model can be integrated as shown in Fig. 6. 5. Simulation results The electrical model was simulated using the same circuit described in Section 3for DC sweep, but now for transient analysis. The input signal (not shown in the plots) is a square pulse with maximum voltage of 10V and minimum of −10V and a period of 240s . All the results are compared with the corresponding numerical simulations. In Fig. 7the contribution of the components of the negative charge to the voltage shift are shown. Similarly in Fig. 8for the positive charge. Additionally, in Fig. 9the results for the total positive and negative charge are visualized along with the voltage shift Vsh considering all the contributions. The error is minimum, so the circuit eectively models the dielectric charging eects. In Figs. 10 and 11 the resulting capacitance in function of time is shown. In Fig. 10, a pulse bias signal from ±6.5V has been applied (top plot) provoking the voltage shift changes (middle plot) and then aecting the value of the capacitance (bottom plot). When the bias voltage is near to the pull-in value, it can be observed that the charge accumulation makes the Vsh large enough to provoke the MEMS to switch from high to low capacitance. In Fig. 11, a ramp is applied with voltage value of ±20V (top plot). One can see that the evolution of the Vsh (middle plot) alters the C-V characteristic (bottom plot), in solid black, which deviates from the ideal behaviour (dashed blue) when no charge injection in the dielectric is considered. 6. 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