Digital system for spiking neural network emulation

TREBALL DE FI DE GRAU Grau en Enginyeria Electrònica Industrial i Automàtica DIGITAL SYSTEM FOR SPIKING NEURAL NETWORK EMULATION Report - Cost Estimation - Annexes Autor: Eduard-Guillem Merino Mallorquí Director: Jordi Cosp Vilella Departament Enginyeria Electrònica (EEL) Convocatòria: Juny 2017 Digital system for spiking neural network emulation i Abstract The present project is about the design, simulation and an experimentational test of a digital system in a single chip able to emulate the behavior of spiking neural networks, which is possible thanks to the use of mathematical models that emulate the behavior of these networks in the brain. A modular system has been proposed in order to provide the necessary flexibility and scalability for the simulation of different neural networks. At the same time the most flexible, simple and efficient option has been chosen in order to have a good performance without losing or reducing the necessary accuracy and exactitude for the emulation of the neural networks. The solution has been implemented by making use of different combinational blocks and totally synchronous flip-flops from a 100 MHz clock signal, besides, the description of the system was performed by using the high-level hardware description language VHDL. Finally, a neural network for pattern recognition has been implemented on a programmable logical device FPGA in order to demonstrate the correct operation of the digital system. Eduard-Guillem Merino Mallorquí ii Resum El present projecte tracta en el disseny, simulació i test experimental d’un sistema digital en un sol xip capaç d’emular el comportament de xarxes neuronals d’impulsos, el qual és possible gràcies al ús de models matemàtics que emulen el comportament d’aquestes xarxes en el cervell. S’ha plantejat un sistema modular per tal de dotar-lo de la flexibilitat i escalabilitat necessària per a la realització de diferents xarxes neuronals. Alhora s’ha buscat la opció més simple i alhora eficient per tal de disposar d’un bon rendiment d’aquesta sense perdre o disminuir la precisió i exactitud necessària per a la emulació de les xarxes neuronals. La solució ha estat implementada fent ús de diferents blocs combinacionals i biestables totalment síncrons a partir d’un senyal de rellotge de 100 MHz, a més, la descripció del sistema s’ha realitzat mitjançant el llenguatge de descripció hardware d’alt nivell (VHDL). Finalment, per demostrar el correcte funcionament del sistema digital s’ha realitzat una xarxa neuronal per al reconeixement de patrons, la qual s’ha implementat sobre un dispositiu lògic programable FPGA. Digital system for spiking neural network emulation iii Resumen El presente proyecto trata el diseño, simulación y test experimental de un sistema digital en un solo chip capaz de emular el comportamiento de redes neuronales de impulsos, el cual es posible gracias al uso de modelos matemáticos que emulan el comportamiento de estas redes en el cerebro. Se ha planteado un sistema modular para dotarlo de la flexibilidad y escalabilidad necesaria para la realización de diferentes redes neuronales. A la vez se ha buscado la opción más simple y a la vez eficiente para disponer de un buen rendimiento de esta sin perder o disminuir la precisión y exactitud necesaria para la emulación de las redes neuronales. La solución ha sido implementada haciendo uso de diferentes bloques combinacionales y biestables totalmente síncronos a partir de una señal de reloj de 100 MHz, además, la descripción del sistema se ha realizado mediante el lenguaje de descripción hardware de alto nivel (VHDL). Finalmente, para demostrar el correcto funcionamiento del sistema digital se ha realizado una red neuronal para el reconocimiento de patrones, la cual se ha implementado sobre un dispositivo lógico programable FPGA. Eduard-Guillem Merino Mallorquí iv Digital system for spiking neural network emulation v Acknowledgements First and foremost, I have to thank my thesis supervisor Jordi Cosp. Without his assistance and dedicated involvement in every step throughout the process, this project would have never been accomplished. I am also grateful to Electronic Engineering Department, for providing me with all the necessary facilities for the development of this project. Last but not the least, I would like to thank my family: my mother Marta and my sister Mireia for helping me and supporting me whenever I needed it. Eduard-Guillem Merino Mallorquí vi Digital system for spiking neural network emulation vii Index ABSTRACT ___________________________________________________________ I RESUM _____________________________________________________________ II RESUMEN __________________________________________________________ III ACKNOWLEDGEMENTS ________________________________________________ V 1. INTRODUCTION _________________________________________________ 1 1.1. Project scope ............................................................................................................ 1 1.2. Objectives ................................................................................................................. 2 1.3. Biological background .............................................................................................. 2 1.3.1. Neural Networks ..................................................................................................... 2 2. ARTIFICIAL NEURAL NETWORKS ____________________________________ 7 2.1. Threshold Logic Unit ................................................................................................ 8 2.2. Multilayer Perceptron .............................................................................................. 9 2.3. Spiking Neural Networks........................................................................................ 10 3. PRELIMINARY STUDY OF ALTERNATIVES ____________________________ 13 3.1. Bluehive .................................................................................................................. 13 3.2. One million neuron single-FPGA neuromorphic system ....................................... 14 3.3. SNAVA .................................................................................................................... 15 4. SPIKING NEURAL NETWORKS _____________________________________ 17 4.1. Neural models ........................................................................................................ 17 4.1.1. Integrate-and-Fire model ..................................................................................... 17 4.1.2. Hodgkin-Huxley model ......................................................................................... 18 4.1.3. Izhikevich model ................................................................................................... 19 4.2. Neuronal connectivity ............................................................................................ 21 4.2.1. AER System ........................................................................................................... 22 4.3. Learning of neural networks .................................................................................. 23 4.3.1. Spike-Timing-Dependent Plasticity ...................................................................... 23 5. DESIGN AND IMPLEMENTATION OF A SNN __________________________ 25 5.1. Izhikevich neuron ................................................................................................... 26 5.1.1. Model adaptation ................................................................................................. 26 5.1.2. Design and architecture ....................................................................................... 27 Eduard-Guillem Merino Mallorquí 4 1.3.1.2. Neural transmission In a neural network, the information is transmitted by nerve impulses that cause polarity changes in the membranes of the cells and propagate through the neurons as if they were small electrical currents, ranging from dendrites and passing through the neural body until the axon. To make this communication between the neurons possible, they establish connections called synapses. Initially, inside the neuron there are proteins and ions with negative charge. This difference in ion concentration produces a potential difference between the outside and inside of the membrane of the neuron. In fact, the usual value is about -70 mV [5]. Moreover, when a nerve impulse reaches a neuron which is at its resting state the membrane depolarizes, achieving the variation of the potential difference that presents the neuron. In the event that the depolarization causes enough variation in the membrane potential, it is said that the neuron has reached the action potential and thus generates a nerve impulse, always with the same intensity, which is transmitted to the next neuron. It has to be noted, that the transmission of nerve impulses follows the law of all or nothing. This means that if the membrane depolarization does not reach a minimum potential, called the threshold potential, the impulse is not transmitted. Figure 1.2. Evolution of the membrane potential of a neuron [5]. Digital system for spiking neural network emulation 5 In addition, the post-synaptic impulses can be either positive or negative called, excitatory or inhibitory, respectively. One neuron receives about ten thousand potential synapses. Therefore, the sum of these potentials determines the value of polarization of the membrane of a neuron. In short, as shown in Figure 1.2, if a neuron receives inhibitory potential, the polarization increases, however, if it receives an excitatory potential, the polarization of the membrane decreases. Only if the stimulus is sufficiently large, so that the depolarization reaches the threshold of excitation, the neuron sends a spike that is transmitted to the neural network. Then, the neuron enters into a short moment of rest, called the refractory period, in which it cannot send another spike again. Finally, the neuron will return to its initial state of rest if it does not receive more stimulus that perturbate its membrane potential charge. Digital system for spiking neural network emulation 7 2. Artificial Neural Networks An artificial neural network (ANN) is a mathematical model that is based on the functionality of biological neural networks and thus, it can be defined as an emulation of biological neural systems. It is designed to produce and replicate the intelligent behavior, ANN’s are at the vanguard of computational systems. Unlike the classical Artificial Intelligence approach, it intends to develop systems to directly simulate rational or logical reasoning, artificial neural networks aims lie at the reproduction of the underlying processing mechanisms that give a system its intelligence. In order to take the full advantage of the artificial neural networks it is needed to interconnect the individual neural networks or its fundamental units, the neurons, in a topology that contributes to an easier, faster and more efficient problem solving. In the past, researchers have developed a series of “standardized” topographies of artificial neural networks that are suited for solving different types of problems. Therefore, after choosing the type of functionality that the neural networks need to offer, it is required to decide the appropriate topology and fine-tune it. Figure 2.1. Example of a simple artificial neural network [6]. In addition, before using the neural network it is an indispensable condition to perform training to teach it problem solving. There are three major learning paradigms: supervised learning, unsupervised learning and reinforced learning. Even though these learning paradigms have their differences in their training methods they all have one thing in common: they train the neural network so it gives the desired output response in line with a series of input signals. Some of the advantages of the artificial neural networks are [5]: • It can be used to solve linear as well as non-linear programming tasks. Eduard-Guillem Merino Mallorquí 8 • If a component of an ANN fails, the net continues to operate (based on its highly parallel nature). • A neural network learns and does not have to be re-programmed. • An ANN can be used to solve classification, movement recognition or visual processing related problems. On the other hand, the main cons of the artificial neural networks are: • Most ANN’s require a training phase to operate or function. • As an ANN’s architecture differs from microprocessors, they have to be simulated. • Large ANN’s require powerful hardware to run and accomplish reasonable execution times. To sum up, artificial neural networks have been in use for some time now and their main application is in the field of robotics. They can be used to plan and direct the way of an autonomous vehicle, recognize obstacles or perform a classification of images. Essentially, artificial neural networks are capable of learning and generalizing from examples and experience to obtain solutions, and as its biological predecessor they are considered an adaptive system. 2.1. Threshold Logic Unit The fundamental unit of an artificial neural network is the neuron. The first computational model for neural networks was based on mathematics and algorithms, which was the Threshold Logic Unit [7], developed by Warren McCulloch and Walter Pitts in 1943. 𝜑𝜑(𝑣𝑣)=�1, 𝑣𝑣≥0 0, 𝑣𝑣< 0 (Eq. 2.1) As shown in equation 2.1, the output of a neuron takes on the value of 1 if the total internal activity level of that neuron is nonnegative and otherwise 0. This statement describes the all-or-nothing property of the McCulloch-Pitts model. Figure 2.2. Threshold activation function [7]. Digital system for spiking neural network emulation 9 Additionally, the Threshold Logic Unit model of a neuron is simple yet has substantial computing potential and a precise mathematical definition. Nevertheless, it is so simple that the weight and threshold values are fixed. 2.2. Multilayer Perceptron The simplest form of an artificial neural network used for the classification of patterns, which are linearly separable, is the perceptron. The single-layer perceptron consists of a single McCulloch-Pitts neuron with adjustable synaptic weights and threshold. Such network is only able to perform pattern classification with only two classes [9]. Figure 2.3. Single-layer perceptron [9]. In order to perform more complex functions, several single-layer perceptron can be combined to obtain a neural network of multilayer perceptron as shown in figure 2.4. Figure 2.4. Multilayer perceptron [9] Eduard-Guillem Merino Mallorquí 10 When the perceptrons were invented, many researchers speculated that the intelligent systems could be developed out of perceptrons. Nevertheless, as the ongoing research was evolving it turned out that it was impossible to develop a convenient learning algorithm. As an example, the exclusive-or (XOR) operation could not be solved. Only when McCulloch-Pitts neurons were replaced by neural models with a differentiable activation function, a back-propagation learning algorithm was invented. 2.3. Spiking Neural Networks The first ideas and models of artificial neural networks are over fifty years old, hence they are already becoming an old technique within the computer science field. The first generation of artificial neural networks consisted of McCulloch-Pitts threshold neurons, as explained above. Rather than using a step or threshold function to compute its output signals, the second generation uses a continuous activation function, making them acceptable for analogue input and output. The last and third generation is what we call the spiking neural networks [10]. The spiking neural networks are the third generation of neural networks which raise the level of biological realism by the use of individual spikes. Just like real neurons do, this functional characteristic allows the codification of spatial-temporal information in communication and computation. Therefore, instead of using rate coding this type of neural networks use mechanisms where neurons receive and do send out individual pulses, called pulse coding, allowing the codification of information as frequency and amplitude of sound. Figure 2.5. Spike-trains [10]. Digital system for spiking neural network emulation 11 The neuronal signal of a spiking neural network consists of short electrical pulses called spikes. These pulses, called action potentials or spikes, have an amplitude of about 100 mV and a duration of 1-2 ms. As shown in Figure 2.5 individual neurons send out sequences of spikes, or spike-trains, which alter dramatically in frequency over a short period of time. Thus, neurons have to use spatial and temporal information of incoming spike patterns to encode their message to other neurons. In short, since all neuron spikes of a spiking neural networks look alike, the form of the action potential does not carry any information. Therefore, it is the number and timing of these spikes which actually matter. Digital system for spiking neural network emulation 13 3. Preliminary study of alternatives This chapter presents a few hardware implementations of artificial neural networks on FPGAs. A general analysis of these implementations has been performed in order to point out their benefits and drawbacks of their computational structures. 3.1. Bluehive Bluehive is a field-programable custom computing machine for extreme-scale real-time neural network simulation, which is capable of emulating 64k neurons along with 64M synapses per FPGA, aimed to be used for scientific simulations with high demanding communication requirements [11]. Figure 3.1. Processing engine of a node in Bluehive [11]. The design places the focus on the communication mechanism and it uses the Izhikevich neural model for neural networks simulations. The core SNN emulation is done by the processing engine that includes the following functional components: • Equation Processor: calculates the equation of the Izhikevich neural model to performs the neuron computation. • Fan-out Engine: takes the neuron firing events, looks up the destination nodes to be notified and the delay to be implemented and farms it out. • Delay-Unit: performs the first part of the fan-in phase. Messages are placed into one of the sixteen 1ms bins, thereby delaying them until the right 1ms simulation time step. • Accumulator: performs the second part of the fan-in phase, accumulation weights to produce an I-value for each neuron. Eduard-Guillem Merino Mallorquí 20 Under these premises, Eugene M. Izhikevich in 2003 presented a simple neuron model for spiking neural networks, which is as biologically plausible like the Hodgkin-Huxley model, and at the same time as computationally efficient as the Integrate-and-Fire model. The author has reduced the accurate biophysiological models of Hodgkin-Huxley neurons into a twodimensional system of differential equations: 𝑣𝑣′= 0,04𝑣𝑣2+ 5𝑣𝑣+140 −𝑢𝑢+𝐼𝐼 (Eq. 4.6) 𝑢𝑢′=𝑎𝑎(𝑏𝑏𝑣𝑣−𝑢𝑢) (Eq. 4.7) If 𝑣𝑣≥30 𝑚𝑚𝑉𝑉,𝑡𝑡ℎ𝑒𝑒𝑛𝑛�𝑣𝑣←𝑐𝑐 𝑢𝑢←𝑢𝑢+𝑑𝑑 (Eq. 4.8) Where 𝑣𝑣 and 𝑢𝑢 are dimensionless variables, and 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, and 𝑑𝑑 are dimensionless parameters, and ′= 𝑑𝑑 𝑑𝑑𝑡𝑡, where 𝑡𝑡 is the time. In biological terms, the variable 𝑣𝑣 represents the membrane potential of the neuron and 𝑢𝑢 represents a membrane recovery variable, which simulates the activation of K+ ionic currents and inactivation of Na+ ionic currents, and it provides negative feedback to the membrane potential of the neuron, 𝑣𝑣. Regarding the behavior of the neuron, the positive synaptic currents 𝐼𝐼 from other neurons increase the value of the membrane potential. In the case that these currents are not sufficient to make the neuron generate an impulse or spike, the voltage of the membrane its reset to its initial value. Alternatively, if the neuron generates a spike (+30 mV) due to sum of their input current, the membrane voltage 𝑣𝑣 and the recovery variable 𝑢𝑢 are reset according to equation 4.8. The resting membrane voltage in this model is between -70 and -60 mV depending on the value of the parameter 𝑏𝑏. In addition, just like real neurons, the model does not have a fixed threshold, hence depending on the history of the membrane potential before the generation of a spike the potential threshold can be as low as -55 mV or as high as -40 mV. The following considerations have to be taken into account for the use of the parameters exhibited in this model: • The parameter 𝑎𝑎 describes the time scale recovery of the variable 𝑢𝑢. Small values result in a slow recovery. A typical value is 𝑎𝑎= 0,02. • The parameter 𝑏𝑏 describes the sensitivity of the recovery variable 𝑢𝑢 to the subthreshold fluctuations of the membrane potential 𝑣𝑣. A typical value is 𝑏𝑏= 0,2. Digital system for spiking neural network emulation 21 • The parameter 𝑐𝑐 describes the after-spikes reset value of the membrane potential 𝑣𝑣. A typical value is 𝑐𝑐=−65 𝑚𝑚𝑉𝑉. • The parameter 𝑑𝑑 describes the after-spike reset of the recovery variable 𝑢𝑢. A typical value is 𝑑𝑑= 8. Figure 4.2. Different types of neurons based on the parameters a, b, c and d [16]. Conclusively, as shown in Figure 4.2, setting different parameters values result in different patterns of intrinsic activation, which allows the behavior emulation of diverse real biological neurons. 4.2. Neuronal connectivity The digital systems implemented for neural networks emulation are still far from an equal efficiency in neural computation or neural coding like the real biological neural networks. Computers use a million times more energy for an operation than a real brain. Video cameras use a thousand times more bandwidth per bit of information than retinas do [17]. Due to these and other shortcomings, today we still cannot replace the damaged parts of the nervous system. Eduard-Guillem Merino Mallorquí 22 Due to this, it is not surprising that a small but growing community of engineers are trying to build systems that meet the efficiency and effectiveness of their biological references, in order to match the efficiency of the performance and computational communication by nature. One of these problems arises when trying to establish the communications between neurons of an emulated neural network. In fact, the neural systems need to connect millions of neurons and thus establish a connection-efficient chip implementation, which creates a major challenge. Therefore, this section will discuss the AER system (Address-Event Representation) which aims to reduce some of these shortcomings and has been implemented in the emulated neural network of this project. 4.2.1. AER System Mahowald and Sivilotti proposed a system of event representation to be able to transmit pulses of a number of neurons on a chip to the appropriate location in an array of neurons in a second chip. Figure 4.3. Schematic of the AER system [18]. In the schematic shown in Figure 4.3 an encoder assigns a unique address for each neuron that generates a spike. Then, a bus transmits these addresses to a decoder that selects the appropriate location of the spike. This communication system is quite efficient to avoid the bottlenecks that occur when the information needs to be exchanged in a massively interconnected system, like the neural networks impulses or spikes. Nevertheless, a number of issues should be considered in order to achieve an efficient implementation of the AER system. One of them is the case in which two or more events occur at the same time, then the system needs to decide in which order they are transmitted through the bus, since it can only transmit one address per time unit. Digital system for spiking neural network emulation 23 4.3. Learning of neural networks To understand how the mammalian cerebral cortex performs its calculations, it is necessary to understand mainly two aspects. First, we must have a good understanding of the neuronal processing units, the neurons; and secondly, we must gain a better understanding of how the mechanisms of these neurons combine to build functional systems. This section talks about the STDP (Spike-Timing-Dependent Plasticity) as a method for building artificial neural networks to perform complex computational operations or solving pattern recognition tasks. 4.3.1. Spike-Timing-Dependent Plasticity The STDP (Spike-Timing-Dependent Plasticity) [19] is a biological process responsible for altering the connections, or synapses, of all the neurons in a spiking neural network. To do so, it strengthens or weakens the connectivity between the neurons based on the degree of synchronization of their spikes. This degree of connectivity is commonly known as the weight of the link or synapse. This rule is a method of unsupervised learning, the concept of which is to strengthen synapsis that contribute to the generation of an output spike, while those that do not contribute, i.e. those that generate spikes after the output spike, are weakened. Considering a presynaptic neuron 𝑖𝑖 and a postsynaptic neuron 𝑗𝑗, the function that characterizes the modification of the synaptic weight is as follows: ∆𝑤𝑤 𝑗𝑗 =��𝑊𝑊(𝑡𝑡 𝑗𝑗𝑙𝑙 −𝑡𝑡 𝑖𝑖𝑘𝑘 ) 𝑁𝑁 𝑙𝑙=1 𝑁𝑁 𝑘𝑘=1 (Eq. 4.9) Along with the function, which defines the degree of increase or decrease of the synaptic weight based on the timing of the impulses between the pre- and postsynaptic neurons expressed as: 𝑊𝑊(𝑥𝑥) = � 𝐴𝐴 + 𝑒𝑒𝑥𝑥𝑒𝑒�−𝑥𝑥 𝜏𝜏+ � 𝑖𝑖𝑓𝑓 𝑥𝑥> 0 𝐴𝐴−𝑒𝑒𝑥𝑥𝑒𝑒�𝑥𝑥 𝜏𝜏−� 𝑜𝑜𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑤𝑤𝑖𝑖𝑒𝑒𝑒𝑒. (Eq. 4.10) In equations 4.9 and 4.10, 𝑡𝑡𝑗𝑗𝑙𝑙 represents the activation time 𝑙𝑙𝑡𝑡ℎ of the neuron 𝑗𝑗; similarly, 𝑡𝑡𝑖𝑖𝑘𝑘 represents the activation time 𝑘𝑘𝑡𝑡ℎ of the neuron 𝑖𝑖; 𝐴𝐴+ and 𝐴𝐴− are the constants that define the extent of the change in the synaptic weight (at 𝑡𝑡= 0+ and 𝑡𝑡= 0− respectively); and, 𝜏𝜏+ and 𝜏𝜏− are the constants of the exponential decrease in the change of the synaptic weight. Eduard-Guillem Merino Mallorquí 24 Figure 4.4. Graphical representation of the STDP learning rule [20]. Figure 4.4 represents equation 4.10 of relative weight changes based on the time between the prespikes and post-spikes of the synapsis between two neurons. Therefore, it shows the reduction of the synaptic weight when a presynaptic neuron fires after a postsynaptic neuron; and on the contrary, an increase of the synaptic weight from a presynaptic neuron to a postsynaptic neuron if a presynaptic neuron fires before the postsynaptic neuron. Digital system for spiking neural network emulation 25 5. Design and implementation of a SNN The simulations of neural networks, due to their intrinsic characteristic of being formed by thousands of interconnected neurons, require high computing power which in turn requires high computational power that can exceed the computing power of a generic microprocessor. Thanks to the technological development, today we have sufficient tools to provide customized hardware systems with the ability to obtain a high computing power by reducing the energy consumption and needed resources. The fact of designing and implementing a microprocessor which is designed to perform a particular task allows us to optimize and maximize its performance with respect to a generic microprocessor. Figure 5.1. Nexys 4 Artix-7 FPGA [21] One of the tools that allow the development and implementation of microprocessors or digital systems are the FPGA (Field-Programmable Gate Array). A FPGA is a semiconductor device based on a matrix of configurable logic blocks connected via programmable interconnections. The aim of this chapter is to explain the design and architecture of the different modules that form the spiking neural network and their interconnection to achieve its implementation in a FPGA. In order to provide the maximum flexibility and scalability possible for the emulation of SNNs a modular system has been proposed. In the following sections, it is explained the design and architecture of a neuron, the AER communication system and the STDP learning method which interconnected allow the emulation of a SNN. Finally, in the next chapter, a SNN for pattern recognition is proposed as a proof-of-concept application. Eduard-Guillem Merino Mallorquí 26 5.1. Izhikevich neuron To simplify the computing power necessary to reproduce the neuron model of Izhikevich and optimize the resources used in the FPGA, a series of adaptions have been made, similar to the fixed-point implementation of the model proposed in [22]. Due to the transition of the neuron model equations from the real numbers to the digital domain, all the properties of binary numbers have been studied in order to avoid performing complex multiplications and divisions that could complicate the implementation and exceed the resources available in a FPGA for the emulation of large-scale neural networks. 5.1.1. Model adaptation Initially, the numbers of the equations for the digital system are represented with a signed vector of 13 bits, therefore with one bit for the sign of the number. In order to start working with the equations, the parameters corresponding to the variables 𝑎𝑎, 𝑏𝑏, 𝑐𝑐 and 𝑑𝑑 have been set to their recommended values in order to obtain a regular spiking neuron model proposed by Izhikevich. Therefore, the following equations have been obtained: 𝑣𝑣′= 0,04𝑣𝑣2+ 5𝑣𝑣+140 −𝑢𝑢+𝐼𝐼 (Eq. 5.1) 𝑢𝑢′= 0,02(0,2𝑣𝑣−𝑢𝑢) (Eq. 5.2) If 𝑣𝑣≥30 𝑚𝑚𝑉𝑉,𝑡𝑡ℎ𝑒𝑒𝑛𝑛�𝑣𝑣←−65 𝑚𝑚𝑉𝑉 𝑢𝑢←𝑢𝑢+ 8 (Eq. 5.3) Secondly, it has been decided to work with a binary representation of integers. Hence, due to the lack of decimal numbers in a binary vector representation a multiplication per ten has been performed. Thus, the membrane potential, 𝑣𝑣, along with the recovery voltage, 𝑢𝑢, are multiplied by ten, obtaining the following model: 𝑣𝑣 ′ =1 250 𝑣𝑣 2 + 5𝑣𝑣+1400 −𝑢𝑢+𝐼𝐼 (Eq. 5.4) 𝑢𝑢′=1 50 (1 5𝑣𝑣−𝑢𝑢) (Eq. 5.5) If Digital system for spiking neural network emulation 27 𝑣𝑣≥300,𝑡𝑡ℎ𝑒𝑒𝑛𝑛�𝑣𝑣←−650 𝑢𝑢←𝑢𝑢+80 (Eq. 5.6) On the other hand, a way to save resources in the FPGA implementation is doing a power of two multiplications or divisions. Therefore, if you calculate a power of two multiplication in a binary number, you only need to shift left the binary vector as many positions as power of two multiplications need to be made. On the contrary, if you calculate a power of two division a shift right operation in the binary vector is enough to obtain the result. In short, the coefficients of the equations have been adjusted to achieve multiplications and divisions by power of two in order to optimize the design. Firstly, for the equation 5.4 the number 250 has been replaced by 256, since 256 = 28. Secondly, for equation 5.5 the divisors 50 and 5 have been replaced by 64 and 4 respectively, since 64 = 26 and 4 = 22. In addition, the multiplication 5𝑣𝑣 and 𝑣𝑣 term of the equation 5.4 have been replaced to implement a sum of six terms of the membrane potential. Since the sum of the six terms can be expressed as a sum of a 2𝑣𝑣 and 4𝑣𝑣, this two power of two multiplications have been implemented as shift left operations. Therefore, the following equations for the adapted model have been obtained: 𝑣𝑣[𝑛𝑛+ 1]= 2𝑣𝑣[𝑛𝑛]+1 28𝑣𝑣2[𝑛𝑛]+ 22𝑣𝑣[𝑛𝑛]+1400 −𝑢𝑢[𝑛𝑛]+𝐼𝐼[𝑛𝑛] (Eq. 5.7) 𝑢𝑢[𝑛𝑛+ 1]=𝑢𝑢[𝑛𝑛]+1 26(1 22𝑣𝑣[𝑛𝑛]−𝑢𝑢[𝑛𝑛]) (Eq. 5.8) If 𝑣𝑣[𝑛𝑛+ 1]≥300,𝑡𝑡ℎ𝑒𝑒𝑛𝑛�𝑣𝑣[𝑛𝑛+ 1]←−650 𝑢𝑢[𝑛𝑛+ 1]←𝑢𝑢[𝑛𝑛+ 1]+80 (Eq. 5.9) 5.1.2. Design and architecture As explained above, a modular, flexible and scalable digital system has been proposed in order to include all the different possibilities that can exist in the emulation of a spiking neural network, while trying to maintain its simplicity. The designed module for the neuron implementation has seven entries, including the clock signal, and one output. Furthermore, the neuron has a small Random Access Memory (RAM), where it stores the different weights of the synaptic connections with other neurons. Eduard-Guillem Merino Mallorquí 28 Looking at Figure 5.2 and going in order, firstly, there is the clock signal (CLK), which is responsible for coordinating the different actions of the neuron; secondly, and activation signal (EN) which serves to activate the functioning of the neuron; thirdly, there are the signals write enable (WE), address (Addr) and synaptic weight (Weight) that are used to write to the internal RAM of the neuron; fourthly, there is the input of the AER bus (AER_Bus) where the neuron reads which neuron of the neural network generated a spike; finally, there is a binary output signal (Spike_out) which indicates whether the neuron generated a spike. Figure 5.2. Digital bloc of a neuron. Lowering a level in the implementation of the neuron, shown in Figure 5.3, there are the different sequential and combinational digital blocks that operate the actions of the neuron. These are: an internal RAM, a sequential block for the weight synaptic input, two registers for the membrane potential and voltage recovery, and two combinational blocks corresponding to the implementation of the differential equations presented above. Figure 5.3. Block diagram of the neuron. Digital system for spiking neural network emulation 29 The internal RAM of the neuron is a matrix that forms a column of synaptic weights. As shown in Table 5.4, each position in the column corresponds to the weight of a synaptic connection with a neuron, so the first column corresponds to the synaptic weight of the connection with the zero neuron of the neural network. NEURON SYNAPTIC WEIGHT 0 70 1 -40 2 0 3 120 4 -15 Table 5.1. RAM of the neuron. Therefore, if the value of the synaptic weight is zero, it means that there is no link between these two neurons. In addition, the used model allows the use of excitatory and inhibitory synaptic weights, i.e. positive and negative respectively. Also, as mentioned above, it is possible to modify the synaptic weights of the connections with write enable (WE), address (Addr) and synaptic weight (Weight) signals. Moreover it is possible to initialize the RAM of a neuron with a .mif text file. Sequentially the functionality process of the neuron is as follows: firstly, it reads the AER communication bus for the neuron that it fired. Then, the RAM is responsible for reading the synaptic weight associated with the number written on the AER bus and it sends it to the Input Align sequential bloc. This blog will dispatch the synaptic weight to the combinational block of the potential membrane equation, also it is responsible for adding the synaptic weights in the case that several neurons fired at the same time. For this purpose, as it will be explained in the next section, the AER bus stops the activity of the neuron deactivating the EN signal, since it cannot transmit more than one spike at once and writes one of the addresses of the neurons that fired in each clock cycle. Also, the Input Align block limits the negative value that a synaptic weight can have to -140 mV because for values under -140 mV the neuron ends up generating a spike when, biologically, the neuron should not excite for inhibitory synaptic weights. To verify that this anomaly was not a consequence of the adapted model for this implementation, several simulations were performed with the original model and it reproduced the exact same behavior with high negative synaptic weights. Finally, the combination blocks corresponding to the model equations perform their operations with the registers “v” store and “u” store where the signals v_n, v_n1 and u_n and u_n1 are stored respectively. The digital implementation of the adapted equations can be seen in detail in Figure 5.5. The top of the diagram corresponds to the equation 5.7 where; firstly, the signal v1 is generated by the square of v_n Eduard-Guillem Merino Mallorquí 36 so it can write, in every clock cycle, the address of the firing neurons. Besides, during the transmission of these spikes neurons number 1 and 2 fire. Then, FIFO stores the corresponding spikes vector and the addresses of these two neurons are written once the priority encoder finishes the spikes transmission of neurons 4, 3, 1 and 0, implementing the functionality as shown in Figure 5.10 of the previous section. 5.3. Spike-Timing-Dependent Plasticity Recent efforts in artificial intelligence studies suggest that the software can be trained and taught to obtain a behavior that goes beyond the reproduction of a fixed sequence of events. Learning is a distinction that separates the intelligent systems from the unintelligent. Thus, researchers are directing considerable effort in developing learning skills for neuronal networks and other synthetic systems. Therefore, this chapter proceeds to explain the design and implementation of the Spike-Timing- Dependent (STDP) learning rule, that modifies the synaptic weights of the connections between neurons depending on the synchrony of their firing. That is, the synapses that contribute to the generation of an output spike of the neural network should be enhanced, while those not contributing to the generation of a spikes in the output must be weakened. 5.3.1. Design and architecture The digital block shown in figure 5.12 has been designed for the implementation of the STDP learning rule based on the digital logic approach from [24]. This block has six inputs, including the clock signal, along with three outputs corresponding to the write enable (WE), address (Addr) and synaptic weight (Weight) signals of the internal RAM of the neuron. Figure 5.12. Digital block of the STDP module. The training system described in the previous chapter is responsible of modifying the weights of all the connections of the neural network. Due to the complexity of creating a module to handle all the Digital system for spiking neural network emulation 37 synaptic weights of the neural network the following solution has been proposed: create a training module that is in charge of the connections of a single neuron. Therefore, having a learning module for each neuron of the neural network that is responsible of all the links coming to that neuron, and thus to maintain and update the RAM of it. Observing the Figure 5.12 and going in order, primarily, there is a clock signal (CLK) which is responsible for coordinating the different actions of the learning module; following this, an activation signal (EN) which serves to activate the learning; next, an activation signal (EN_Addr) that is responsible for changing the connection in which the STDP rules is applied; thus, two signals Pre_Spikes and Post_Spike that are the responsible of reading the firings of the previous neurons and the spike of the neuron where the STDP module is connected respectively; and finally, at the output there are the write enable (WE), address (Addr) and synaptic weight (Weight) signals that allow to write in the RAM of the neuron. In addition, there is a reset signal (RST) that along with the enable signal (EN) allow to reset all the synaptic weights of the neuron’s RAM. Figure 5.13. Block diagram of the STDP module. As shown in Figure 5.13, there are several interconnected combinational and sequential blocks for the STDP module to function. These are: a counter address (Addr cnt) to select on which synaptic link the STDP rule is applied, an increment or decrement link selector (I/D Sel.) that actives the corresponding signal whether the pre-spike happens before or after the post-spike of the connection, a synaptic weight counter (Weight cnt) that is responsible for storing and modifying the synaptic weight of all the Eduard-Guillem Merino Mallorquí 38 connections of the neuron, and finally a set of combinational blocks that allow the digital logic implementation of equations 4.9 and 4.10 from the STDP learning rule. Sequentially the operational process of the learning module is as follows: initially, the pre-spikes and post-spike signals are being read while the address counter is in charge of selecting the connection to apply the STDP rule with the Syn_Addr signal, which at the same time serves as a selector channel for the multiplexer, indicates to the weight counter the link to modify and proportionate the address of the neuron’s RAM. After, in the event of a spike from the previous neurons of the neuron in which the STDP module is connected, the I/D Sel block activates the corresponding output signal to indicate whether the weight counter needs to increase or decrease the connection’s value of the synaptic weight. Also, the spike is propagated through the shift register and activating the pre_gate signal. Then, if the neuron of the training module fires, its spike is propagated by the corresponding shift register activating the post_gate signal. The activation of these two logic gates along with the increased signal provided by the I/D Sel block generates an increment pulse for the synaptic weight counter. Therefore, depending on the duration of this pulse counter it will increase more or less the weight of the synaptic connection. Moreover, it will activate the write enable signal (WE) to allow the update of the neuron’s RAM. Figure 5.14. Timeline of the implemented STDP learning rule [24]. In short, as shown in Figure 5.14, depending on the increasing or decreasing pulse duration the value of the synaptic weight will increase or decrease respectively. That is, if the neuron fires after its preceding neurons generated a spike, the almost synchronous activation of the logic gates pre_gate and post_gate will create a long pulse length for the synaptic weight counter, which increases the weight of the connection for each clock cycle. Finally, this design allows the regulation of the STDP function by modifying the length of the registers corresponding to the neuron’s spikes. Therefore, creating a more or less sensible STDP learning rule to the synchrony of the neural impulses. Digital system for spiking neural network emulation 39 5.3.2. Simulations In this section, there are the various simulations of the implemented module made with Vivado in order to show the different behaviors exhibited by the learning module. In the timeline simulations, there are the inputs and outputs of the STDP module along with the pre_gate, post_gate, incr and decr internal signals for a better understanding of the inner workings of the design. Figure 5.15. Timeline of inputs and outputs of the STDP learning module (Case 1). First, for the preparation of the timelines a neuron connected to a previous layer of three neurons has been simulated. Therefore, the Pre_Spikes signal is a vector of three binary numbers corresponding to the three synaptic connections and the Post_Spike signal is a single bit that corresponds to the firing of the neuron that is connected to the STDP learning module. Looking at figure 5.15, around the 20 ns, there is a spike from the first synaptic connection, moments later, the neuron generates a spike that is read through the Post_Spike signal. Because of this, the internal signals pre_gate and post_gate activate respectively and when these two come together in time, the signal incr generates a pulse of one clock cycle that is sent to the weight counter. Finally, the value of the synaptic weight, which at the start was 0, is updated to the neuron’s RAM with a value of 1 by the write enable (WE), address (Addr) and synaptic weight (Weight) signals. Continuing with Figure 5.16, the same functionality is exhibited with the difference that the time between the two spikes is lower, therefore the value of the synaptic weight is increased to a greater extent, i.e. from 0 to 4. Eduard-Guillem Merino Mallorquí 40 Figure 5.16. Timeline of inputs and outputs of the STDP learning module (Case 2). Moreover, Figure 5.17 shows the case in which a neuron of the input layer fires after the neuron where the STDP module is connected fired. Hence, due to the I/D Sel block and the digital combinational logic explained above, a decrement pulse is generated, indicating to the synaptic weight counter the decline in the value of the link connectivity from 0 to -2. Figure 5.17. Timeline of inputs and outputs of the STDP learning module (Case 3). Digital system for spiking neural network emulation 41 Finally, the functionality of the learning module for this small neural network is shown in Figure 5.18. As it can be observed, approximately every 200 ns the neuron receives the same trend of spikes from the neurons which is connected to. Thus, the learning module has the ability to alter one synaptic connection for each time that it receives the spikes. Firstly, the first synapsis that corresponds to the first bit of the Pre_Spikes vector is updated with a value of 4. Secondly, the EN_Addr signal is activated so the learning module operates for the second synapsis, since there is no spike from it the value is not modified. Finally, the EN_Addr signal is triggered again to apply the STDP learning in the third synapsis, and the weight value is updated to 2 due to the time difference between the two spikes. Figure 5.18. Timeline of inputs and outputs of the STDP learning module (Case 4). Ultimately, the goal of this module is to sequentially update all the synapses to which the neuron is connected to in order to implement the STDP learning rule. This way, the number of resources needed to implement this system is greatly reduced in comparison to a module that took care of all the synapses of the neural network at once. 5.4. SNN Emulation As explained in the introduction to this chapter, to give the neural network the highest possible flexibility and scalability a modular system of three main entities or digitals modules has been proposed. These are: first, the neuron; second, the AER communication bus; and thirdly, the STDP learning system. Once explained in the previous sections the internal functionality of each digital block, this section aims to explain how to perform an SNN emulation by interconnecting each one of the proposed digital modules. Meaning, how to connect and replicate these main digital modules in order to obtain a neural network of two, ten or thousands of neurons if the available resources allow it. Eduard-Guillem Merino Mallorquí 42 5.4.1. Design and architecture To start with, a neural network made up of several layers is shown in figure 5.19. Firstly, an input layer which receives all external stimuli, second, a variable number of hidden layers that are responsible for performing the operations of the neural network, and then thirdly, an output layer in which the neural network broadcasts its stimuli or responses to the outside. Figure 5.19. Architecture of a neural network [25]. To make it simple, Figure 5.20 shows a neural network of two neurons. However, this architecture allows the implementation of as many neurons as needed. To begin with, what can be seen is that the AER system is responsible for establishing the communication between all the neurons, i.e. read the spikes to translate them into the appropriate address and transmit them to the AER bus. All neurons are connected to the EN_Neuron signal which allow to stop the activity of the neurons, since as explained before, the AER bus can only transmit one address per clock cycle. Moreover, the neurons of the input layer are merely external stimuli, so the introduction of such into the neural network is done by treating the spikes vector. Additionally, each neuron is formed by its digital module and a STDP learning module. The interconnection between these two is established with the write enable (WE), address (Addr) and synaptic weight (Weight) signals that allow to write in the neuron’s RAM. Digital system for spiking neural network emulation 43 Figure 5.20. Interconnection of the different blocks for the emulation of SNN of two or more neurons. Utimately, the STDP modules the EN and EN_Addr signals along with the Pre_Spikes signal need to be treated with specific digital blocs. These blocks were not included in the diagram of the Figure 5.20, because they depend either from the layer architecture or the functionality of the neural network to emulate. Therefore, it is not possible to provide a standard solution for the many neural networks that this design can implement. However, in the next chapter a SNN for pattern recognition is proposed where the various blocks that allow the configuration of the STDP modules are explained. Digital system for spiking neural network emulation 45 6. Pattern recognition with a SNN Below is simple spiking neural network that is presented as an example to demonstrate the functionality of the design of the previous chapter. More specifically, it is a SNN with the functionality to recognize patterns and generate a response based on these types of networks, which are mainly used for image processing, for example to identify the letters of the alphabet or the numbers displayed in an image, recognize the movement of an object in a sequence of images or to detect cars in each lane of a motorway. This chapter explains in detail the design of this SNN for pattern recognition beginning with the model of the network used, the patterns to recognize and the training method [20]. Finally, several simulations are carried and the final design is implemented into a FPGA to verify its functionality. 6.1. Neural network model The neural network developed in this project as an example for pattern recognition tasks is presented in Figure 6.1. This network is dedicated to recognizing patterns in images of 5x7 pixels, i.e. 35 pixels. Figure 6.1. Representation of the neural network developed for the recognition of six patterns. Eduard-Guillem Merino Mallorquí 52 Figure 6.8. Complete simulation of the SNN for pattern recognition digits 0 to 5. Therefore, in the first phase of the training where the image of digit 0 is selected along with the training neuron that corresponds to the output neuron 41, it can be seen that the output neuron does not fire, but as long as the training advances in time, the synapses that contribute to its firing are modified and the output neuron 41 ends up learning to generate spikes for the selected pattern. Then, in the third phase of the training the image of digit 2 and the training neuron of the output neuron 43 is selected. In this case when the third phase is just starting the output neuron 41 is firing, however, as the training phase advances stops firing and it is only the output neuron 43 that generates spikes for the selected pattern. In the following phases of the training the process is the same, until the training is complete in about 9 ms. Then, the correct pattern recognition of the neural network is tested and for one millisecond the images from digits 0 to 5 are introduced and the corresponding output neurons fire only for their respective trained digit. Figure 6.9. Modification of the synaptic weights of the SNN. Digital system for spiking neural network emulation 53 The modification of the synaptic weights of the SNN are shown in Figure 6.9. As it can be observed this are only modified when the EN_STDP pulse is triggered, which means they are only modified during the different training phases. Also, as explained before when triggering the reset signal along with the training button all the synaptic weights values are reset to zero, getting the SNN ready to start another training. Other behaviors described in the previous sections on the input stimulus and training neurons can be seen by looking at Figure 6.10, which is the same simulation performed on 6.8 and 6.9. Firstly, the position of the marker corresponds to the introduction of stimuli corresponding to the image of the 0 digit, from bit 0 to 34 in the Spikes vector. A few clock cycles later the training neuron 35 fires in order to train the output neuron 41. On the contrary, the rest of the training neurons fire before the stimulus of the neural network in order to weaken the corresponding synapses. After some more input stimuli, neuron 41 ends up learning and firing in its own as shown in Figure 6.11. Figure 6.10. Firing of input, training and output neurons of the SNN. Figure 6.11. Firing of input, training and output neurons of the SNN. Eduard-Guillem Merino Mallorquí 54 Digits from 0 to 5 are not the only patterns that the SNN can be trained to recognize. In Figure 6.12 the output neurons 41 to 46 have been trained with the patterns of digits 4 to 9 respectively, as it can be seen with the values of the Image vector (“0000000001” corresponds to number 0, “0000000010” to number 1, until “1000000000” for number 9). Figure 6.12. Complete simulation of the SNN for pattern recognition digits 4 to 9. Moreover, the influence of the training phase time can be observed in Figures 6.13 and 6.14. Following on from the same learning for pattern recognition of digits 4 to 9, in Figure 6.13 not all the output neurons end up generating spikes due to an insufficient training time. However, in Figure 6.14 due to an excessive training time the output neuron corresponding to the digit 8 fires when a digit 6 and 9 are introduced as stimuli to the SNN. Digital system for spiking neural network emulation 55 Figure 6.13. Complete simulation of the SNN for pattern recognition digits 4 to 9 (insufficient training time). Figure 6.14. Complete simulation of the SNN for pattern recognition digits 4 to 9 (excessive training time). Eduard-Guillem Merino Mallorquí 56 Moreover, the influence of the training phase time can be observed in Figures 6.13 and 6.14. Following on from the same learning for pattern recognition of digits 4 to 9, in Figure 6.13 not all the output neurons end up generating spikes due to an insufficient training time. However, in Figure 6.14 due to an excessive training time the output neuron corresponding to the digit 8 fires when a digit 6 and 9 are introduced as stimuli to the SNN. Additionally, Figure 6.14 and Figure 6.15 represent a complete simulation of the SNN for pattern recognition of digits 0 to 5 and digits 4 to 9 respectively, as shown before. Nevertheless, in these simulations the difference resides in the stimuli used after the training phases have concluded. Instead of using the same digits for the whole simulation, after the training phase the digits with noise from Figure 6.3 are introduced into the SNN thanks to the activation of the signal SEL. Regardless of the difference in several pixels due to the noise of the images, since the main shape of the digits remains unchanged the neural network is capable of recognizing the correct numbers. Therefore, it proves the functionality of recognizing similar patterns. Figure 6.15. Complete simulation of the SNN for pattern recognition digits 0 to 5. Having said that, in Figure 6.15, the neuron corresponding to digit 8 fires for either digits 8 and 9 with noise, which is something to expect since the main shape of this two numbers are quite similar and therefore the SNN recognizes them as the same. Digital system for spiking neural network emulation 57 Figure 6.16. Complete simulation of the SNN for pattern recognition digits 4 to 9. Finally, the simulations which were performed enabled a corroboration of what has previously been said. For long training time periods a less restrictive training is performed which, in excess, can trigger the firing of all output neurons for any given pattern. On the contrary, for short training time periods a more restrictive training is performed which cannot be enough to trigger the firing of the output neurons. Succinctly, although the SNN has been able to learn different patterns (digits 0 to 5 and 4 to 9) with the same training time, it is not required to be similar for other pattern combinations because, at the end, each pattern combination has its appropriate training time period in order to trigger the firing of the corresponding output neuron. 6.4.4. Experimental results The results of the physical implementation of the design into the FPGA are presented in this section. As said before the FPGA used to verify the functionality of the digital system is a Nexys 4 Artix-7 model at 100 MHz. Initially, in order to read the spikes from all the output neurons from the FPGA analog outputs two oscilloscopes has been used. Firstly, the AD Instruments DS2202A with a 200 MHz bandwidth that allowed to view the form of a single spike. Secondly, the RIGOL DS1102D, a digital oscilloscope of 100 Eduard-Guillem Merino Mallorquí 58 MHz bandwidth with a logic analyzer channel that can read up to 16 signals, which has been used to read the spikes of the six output neurons of the neural network at the same time. Observing the 6.17 picture, taken with the DS2202A oscilloscope, there are three spikes of an output neuron of the SNN with a frequency of about 625 KHz. This is the time period between the input of the pattern, so the SNN has time to generate a response to the introduced pattern and all neurons have enough time to return to their initial state of rest. Figure 6.17. Spikes from output neuron 0. Next, the SNN has being trained for the pattern recognition of digits 0 to 5, as did before with the simulations. The results are shown in figure 6.18, with six captures made with the DS1102D digital oscilloscope, one for each input pattern. Therefore, first image corresponds to the stimuli of the SNN with digit 0, second image with digit 1, until sixth image with digit 5. As it can be observed, the SNN exhibits the expected behavior recognizing the input pattern by generating spikes with the corresponding output neuron. Digital system for spiking neural network emulation 59 Figure 6.18. Spikes from output neurons 0 to 5 of the neural network for the pattern recognition of digits 0 to 5 respectively (Digit 0 as input pattern for the first image, digit 1 for second image...). Moreover, in Figure 6.19 the SNN has being trained for the pattern recognition of digits 4 to 9, as did before with the simulations. Therefore, first image corresponds to the stimuli of the SNN with digit 4, second image with digit 5, until sixth image with digit 9. As it can be observed, the SNN exhibits the expected behavior recognizing the input pattern by generating spikes with the corresponding output neuron. Nevertheless, for input pattern of digit 9 the output neuron corresponding to digit 8 recognition also generates spikes. This shows one of the fundamental properties of the SNN, which are the recognition of similar patterns. Since the shape of digit 9 is close to the shape of digit 8 the SNN mistakes the 9th digit shape as digit 8. Eduard-Guillem Merino Mallorquí 60 Figure 6.19. Spikes from output neurons 0 to 5 of the neural network for the pattern recognition of digits 4 to 9 respectively (Digit 4 as input pattern for the first image, digit 5 for second image...). As explained above, the challenge resides on finding the appropriate training time period in order to trigger the firing of the corresponding output neuron. Therefore, to improve the training in the digit 4 to 9 recognition the train time period needs to be adjusted or output neuron 5 could send inhibition pulses to the output neuron 8 in order to prevent its firing. In order to test out the property of the SNN to recognize similar patterns, the inputs of digits 6 to 9 has been introduced to the SNN presented in Figure 6.18 and the inputs of digits 0 to 3 into the SNN presented in Figure 6.19. Digital system for spiking neural network emulation 61 The response of the SNN of Figure 6.18 has been negative to the inputs of digits 6, 7 and 9 except for digit 8. Therefore, when introducing the stimuli to the SNN corresponding to digit 8 the output neuron 0 and 3 start to generate spikes as shown in Figure 6.20. This behavior is expected since digit 8 shape is similar to digit 0 and 3 shapes. Figure 6.20. Spikes from output neurons 0 to 5 of the neural network for the pattern recognition of digits 0 to 5 respectively (Digit 8 as input pattern). On the other hand, the response of the SNN of figure 6.19 has been null to the inputs of digits 1 and 2, but for inputs of digits 0 and 3 the output neuron corresponding to digit 8 detection starts firing. Therefore, exhibiting the same behavior explained above but just the other way around as shown in Figure 6.21. Figure 6.21. Spikes from output neurons 0 to 5 of the neural network for the pattern recognition of digits 4 to 9 respectively (Digit 0 as input pattern for the first image and digit 3 for the second image). Digital system for spiking neural network emulation 69 Cost estimation This annex is about the cost estimation to carry out the totality of this final project, which takes into account the money spent on the devices, licenses and hours of work required to design, implement and verify the results of the developed digital system in the laboratory. Firstly, the used devices for the successful realization of the digital system are: a personal computer to design, synthesize and simulate the design along with the creation of the different schematics and block diagrams presented in this report, a Nexys4 DDR Artix-7 FPGA trainer board where the design is implemented to demonstrate the functionality of the digital system, a RIGOL DS1022CD digital oscilloscope that allows to capture the spikes of the spiking neural network and an AD Instruments DS2202A analog oscilloscope to show the shape of a single spike. Total price (€) Useful life (yr.) Time used (yr.) Eqv. price (€) Computer 800,00 4 0.5 100,00 Nexys4 DDR Artix-7 294,65 4 0.5 36,83 RIGOL DS1022CD 715,00 6 0.5 59,58 AD INSTR. DS2202A 595,00 6 0.5 49,58 Total 1.809,65 - - 245,99 Table 1. Equivalent price of used devices. Secondly, the cost of the licenses of the different software used to develop this project are; the Vivado WebPack for students license to design, synthesize, simulate and implement the digital system into the FPGA board, the Microsoft Office package to create the different schematics and block diagrams along with the report of this project, and a Windows 10 license for the computer. Price per year (€/yr.) Time used (yr.) Eqv. price (€) Vivado WebPack 0,00 0.5 0,00 Microsoft Office 29,89 0.5 14,95 Windows 10 44,00 0.5 22,00 Total 73,89 - 36,95 Table 2. Equivalent price of software licenses. Furthermore, there is the cost of the working hours to develop the digital system of this project. Since this is the work of an engineering student, a price of approximately 8€ per hour has been established as a recommendation in the educational cooperation agreement between the UPC and the companies that offer academic practices for engineering students. Eduard-Guillem Merino Mallorquí 70 Work (hours) Price per hour (€) Total price (€) Engineering student 600 8 4800,00 Table 3. Total price of the engineering student. Ultimately, the total price to carry out the totality of this final project is obtained by computing the sum of all the calculated prices above starting with the used devices, software licenses and ending with the cost of an engineering student’s work hours. Price (€) Devices 245,99 Software licenses 36,95 Engineering student 4800,00 Total 5082,94 Table 4. Total price of the project. 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[28] Izhikevich, Eugene M. 2004. “Which Model to Use for Cortical Spiking Neurons?” IEEE Transactions on Neural Networks 15 (5): 1063–70. doi:10.1109/TNN.2004.832719. [29] Linares-Barranco, Alejandro. 2003. “Estudio Y Evaluación de Interfaces Para Conexión de Sistemas Neuromórficos Mediante Address-Event Representation (AER),” 228. [30] Rivera, Giovanny Sanchez. 2014. “Efficient Multiprocessing Architectures for Spiking Neural Network Emulation Based on Configurable Devices.” Thesis UPC. [31] Zupan, Jure. 1994. “Introduction to Artificial Neural Network (ANN) Methods: What They Are and How to Use Them.” Acta Chimica Slovenica 41 (September): 327–52. http://www2.ccc.uni-erlangen.de/publications/ANN-book/publications/ACS-41-94.pdf. Digital system for spiking neural network emulation 75 Annexes A1. User’s Manual 1. Introduction This document is intended to be used by any individual interested in developing the emulation of a spiking neural network (SNN) by using the digital system presented in this project. For such an aim, a software suite for synthesis and analysis of VHDL designs is needed, for this project Vivado Design Suite has been used with the free WebPack license. 2. Overview The digital system is formed by several VHDL files for different purposes: • Design Sources: Top.vhd, AER_Bus.vhd, IZH_Neuron.vhd, RAM_09.vhd, STDP.vhd. • Constraints: Nexys4_Master.xdc. • Simulation Sources: Testbench - Top.vhd, Testbench - IZH_Neuron.vhd, Testbench - AER_Bus.vhd, Testbench - STDP.vhd. First of all, the design sources, which include the AER system, an Izhikevich neuron with its RAM and the STDP training module that can be used as default templates for developing any type of SNN. In addition, a Top entity is provided in which an example of a SNN for pattern recognition is designed. Second, a constraint file that together with all the provided design sources gives the ability to implement the SNN for pattern recognition into a Nexys 4 Artix-7 FPGA. Finally, four test bench, one to simulate the example of a SNN for pattern recognition and three to simulate each one of the modules proposed as default templates (AER, IZH_Neuron and STDP) for any type of SNN emulation. 3. Design sources This section’s aim is to provide the general instructions for the use of the different design sources of the design for the emulation of any SNN. Eduard-Guillem Merino Mallorquí 76 1.1. Top entity The Top entity of the design is provided through the Top.vhd file. It is the responsible for implementing a type of SNN for pattern recognition making use of the rest of the design sources. For a custom SNN refer to last section to learn how to use the IZH_Neuron, AER and STDP entities as default templates for your design. The structure of the files is shown in the following picture from the Vivado’s project manager: Figure 1. Design Sources’ files structure. The generic variables are at the top of the file and they can be easily modified in order to adjust the SNN before the synthesis and implementation of the design. These are the following: GENERIC Description Default value image_num Number of images or patterns. (If 9 then 10 images since “9 downto 0”). Multiplexer needs to be updated if image_num changed. 9 rest_time Number of clock cycles between the input stimuli for the SNN (Should be enough for all the neurons of the SNN to return to their default state). 149 train_time Number of input stimuli for a training phase. 200 train_spike Number of clock cycles after the input stimuli to generate the spike for the selected training neuron. 10 untrain_spike Number of clock cycles before the input stimuli to generate the spike for the unselected training neurons. 5 pre_reg STDP pre-spike or increment register width. 15 post_reg STDP post-spike or decrement register width. 5 width Number of bits plus one for equation variables of IZH_Neuron. 12 neuron_adr Number of bits plus one for neuron addresses (If 5 then up to 64 neuron addresses since 2^6=64). 5 weights Number of bits plus one for synaptic weights (signed vector). 10 input_neuron_num Number of input and training neurons minus one. 40 training_neuron_num Number of training neurons. 6 neuron_num Total number of neurons. 46 Table 2. Top’s entity generics. Digital system for spiking neural network emulation 77 1.2. Izhikevich neuron The Izhikevich neuron module of the design is provided through the IZH_Neuron.vhd and RAM_09.vhd files. It is the responsible for implementing a neuron of the Izhikevich model. The structure of the files is shown in the following picture from the Vivado’s project manager: Figure 2. Izhikevich neuron’s files structure. The generic variables are at the top of the file and they can be easily modified in order to adjust the neuron before the synthesis and implementation of the design. These are the following: GENERIC Description Default value number Address number assigned to the neuron. 0 width Number of bits plus one for equation variables of IZH_Neuron. 12 neuron_adr Number of bits plus one for neuron addresses (If 5 then up to 64 neuron addresses since 2^6=64). 5 weights Number of bits plus one for synaptic weights (signed vector). 10 Table 2. Izhikevich neurons’ generics. In addition, a .mif file can be provided in order to initialize the synaptic weights values of the neuron’s RAM. These files can be easily created with a text editor or notepad always making sure the number of bits is correct. In Figure 3 an 11-bit signed vector is provided for each address of the RAM, which corresponds to the default value of the weights generic. Figure 3. Path for the initialization file of the RAM for each neuron. Furthermore, the path of the file for the initialization of the synaptic weight values of the neurons’ RAM needs to be defined in the RAM_09.vhd file in order to synthesize the design. This can be found at line 46 as shown in the following picture of the code: Eduard-Guillem Merino Mallorquí 84 end if; end process; -- Input neurons process(clk) begin if (CLK='1' and CLK'event) then Image_Signal <= Image; Neuron_Signal <= Neuron; end if; end process; Digit <= "01110100011000110001100011000101110" when Image_Signal(0)='1' else "00100011000010000100001000010001110" when Image_Signal(1)='1' else "01110100010000100010001000100011111" when Image_Signal(2)='1' else "01110100010000100110000011000101110" when Image_Signal(3)='1' else "00010001100101010010111110001000010" when Image_Signal(4)='1' else "11111100001111000001000011000101110" when Image_Signal(5)='1' else "00110010001000011110100011000101110" when Image_Signal(6)='1' else "11111000010001000100010000100001000" when Image_Signal(7)='1' else "01110100011000101110100011000101110" when Image_Signal(8)='1' else "01110100011000101111000010001001100" when Image_Signal(9)='1' else (others => '0'); Digit_Noise <= "11111100011000110001100011000111111" when Image_Signal(0)='1' else "00100011000010000100001000010000100" when Image_Signal(1)='1' else "01110000010000100010001000100001111" when Image_Signal(2)='1' else "01110000010000100110000010000101110" when Image_Signal(3)='1' else "00010100101001010010111110001000010" when Image_Signal(4)='1' else "11110100001111000001000010000101110" when Image_Signal(5)='1' else "00110010001000001110100001000101110" when Image_Signal(6)='1' else "11111000010001000000010000100001000" when Image_Signal(7)='1' else "01110100011000111111100011000101110" when Image_Signal(8)='1' else "01110100011000101110000010001000100" when Image_Signal(9)='1' else (others => '0'); Pixels <= Digit_Noise when SEL='1' else Digit; Digital system for spiking neural network emulation 85 Spikes_in(input_neuron_num downto 0) <= Neuron_Signal & Pixels; Input_Neurons : for I in 0 to input_neuron_num-training_neuron_num generate process(clk) begin if (CLK='1' and CLK'event) then if Counter=rest_time then Spikes(I)<=Spikes_in(I); else Spikes(I)<='0'; end if; end if; end process; end generate Input_Neurons; -- STDP Change synaptic addr process(clk) begin if (CLK='1' and CLK'event) then if Counter=rest_time-1 then EN_Addr<='1'; else EN_Addr<='0'; end if; end if; end process; -- Training Neurons Training_Neurons : for I in input_neuron_num-training_neuron_num+1 to input_neuron_num generate process(clk) begin if (CLK='1' and CLK'event) then if(EN_STDP='1') then if(Spikes_in(I)='1' and Counter=train_spike) then Spikes(I)<='1'; elsif(Spikes_in(I)='0' and Counter=rest_time- untrain_spike) then Spikes(I)<='1'; else Spikes(I)<='0'; end if; else Spikes(I)<='0'; end if; end if; end process; end generate Training_Neurons; -- Output Spikes process (CLK) begin if (CLK='1' and CLK'event) then Eduard-Guillem Merino Mallorquí 86 Spikes_Signal<=Spikes(neuron_num downto input_neuron_num+1); Spikes_out<=Spikes_Signal; end if; end process; -- State Machine to detect the pushbuttons process (CLK) begin if (CLK='1' and CLK'event) then case STATE0 is when NP => if BTN='1' then STATE0 <= P0; BTN_Signal <= '0'; else STATE0 <= NP; BTN_Signal <= '0'; end if; when P0 => STATE0 <= P1; BTN_Signal <= '1'; when P1 => if BTN='1' then STATE0 <= P1; BTN_Signal <= '0'; elsif BTN_Rebound=2000 then STATE0 <= NP; BTN_Signal <= '0'; end if; end case; end if; end process; process(CLK) begin if (CLK='1' and CLK'event) then if (BTN_Signal='1') then BTN_Rebound <= (others=>'0'); else if BTN_Rebound=2000 then BTN_Rebound <= (others=>'0'); else BTN_Rebound <= BTN_Rebound + 1; end if; end if; end if; end process; -- Enable signal for the STDP Module process (CLK) begin if (CLK='1' and CLK'event) then case STATE1 is when NP => if BTN_Signal='1' then STATE1 <= P0; En_Pulse <= '1'; EN_STDP <= '1'; else En_Pulse <= '0'; EN_STDP <= '0'; Digital system for spiking neural network emulation 87 end if; when P0 => STATE1 <= P1; when P1 => if Pulse=train_time*rest_time then STATE1 <= NP; else En_Pulse <= '1'; EN_STDP <= '1'; end if; end case; end if; end process; process(clk) begin if (CLK='1' and CLK'event) then if (EN_Neuron='1') then if(En_Pulse='1') then if Pulse=train_time*rest_time then Pulse<=(others => '0'); else Pulse <= Pulse + 1; end if; end if; end if; end if; end process; -- AER AERX:AER_Bus GENERIC MAP( neuron_adr => neuron_adr, neuron_num => neuron_num) PORT MAP( CLK => CLK, Spikes => Spikes, EN_Neuron => EN_Neuron, AER => AER); -- IZH Neurons Network : for I in input_neuron_num+1 to neuron_num generate NX:IZH_Neuron GENERIC MAP( number => I, width => width, neuron_adr => neuron_adr, weights => weights) PORT MAP( CLK => CLK, RST => RST_Signal, EN => EN_Neuron, WE => WE(I), Addr => Addr(I), Weight => Weight(I), AER_Bus => AER, Eduard-Guillem Merino Mallorquí 88 Spike_out => Spikes(I)); end generate Network; -- STDP Pre_Spikes <= Spikes(input_neuron_num-training_neuron_num downto 0); EN_Train <= EN_STDP and EN_Neuron; Training : for I in input_neuron_num+1 to neuron_num generate TX:STDP GENERIC MAP( neuron_adr => neuron_adr, weights => weights, input_neuron_num => input_neuron_num, training_neuron_num => training_neuron_num, pre_reg => pre_reg, post_reg => post_reg) PORT MAP( CLK => CLK, RST => RST_Signal, EN => EN_Train, EN_Addr => EN_Addr, Pre_Spikes => Pre_Spikes, Post_Spike => Spikes(I-training_neuron_num), WE => WE(I), Addr => Addr(I), Weight => Weight(I)); end generate Training; end Behavioral; Digital system for spiking neural network emulation 89 1.2. Izhikevich neuron ------------------------------------------------------------------------- -- Engineer: Eduard-Guillem Merino Mallorqui -- Create Date: 11:53:08 02/12/2017 -- Module Name: IZH_Neuron - Behavioral -- Project Name: Digital System for Neural Network Emulation ------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity IZH_Neuron is Generic ( number : in integer; width : in integer; neuron_adr : in integer; weights : in integer); Port ( CLK : in std_logic; RST : in std_logic; EN : in std_logic; WE : in std_logic; Addr : in std_logic_vector(neuron_adr downto 0); Weight : in std_logic_vector(weights downto 0); AER_Bus : in std_logic_vector(neuron_adr downto 0); Spike_out : out std_logic); end IZH_Neuron; architecture Behavioral of IZH_Neuron is COMPONENT RAM_09 GENERIC( width : in integer; neuron_adr : in integer; weights : in integer; number : in integer); PORT( clk : in std_logic; we : in std_logic; a : in std_logic_vector(neuron_adr downto 0); dpra : in std_logic_vector(neuron_adr downto 0); di : in std_logic_vector(weights downto 0); dpo : out std_logic_vector(weights downto 0)); end COMPONENT; signal c,d,thresh : signed(width downto 0); signal I,v_n,v_n1,u_n,u_n1 : signed(width downto 0) := (others => '0'); signal v1,v2,v3,u1,u2,u3,u4,u5 : signed(width downto 0); signal Synaptic_in : std_logic_vector(weights downto 0); signal Spike : std_logic; type signed_array is array (0 to 1) of signed(width downto 0); signal I_store, v_store, u_store : signed_array := (others => (others=>'0') ); begin Eduard-Guillem Merino Mallorquí 90 -- RAM RAM:RAM_09 GENERIC MAP( number => number, width => width, neuron_adr => neuron_adr, weights => weights) PORT MAP( clk => CLK, we => WE, a => Addr, dpra => AER_Bus, di => Weight, dpo => Synaptic_in); -- Input align process (CLK) begin if (CLK='1' and CLK'event) then if (EN='1') then I_store(0)<=resize(signed(Synaptic_in),I_store(0)'length); I<=I_store(1); if I_store(0)>-140 then I_store(1)<=I_store(0); else I_store(1)<=to_signed(-140,I_store(0)'length); end if; else I_store(0)<=I_store(0)+resize(signed(Synaptic_in),I_store(0)'length); end if; end if; end process; -- "v" Store process (CLK) begin if (CLK='1' and CLK'event) then if (EN='1') then v_store(0)<=v_n1; v_store(1)<=v_store(0); v_n<=v_store(1); end if; end if; end process; -- "u" Store process (CLK) begin if (CLK='1' and CLK'event) then if (EN='1') then u_store(0)<=u_n1; u_store(1)<=u_store(0); u_n<=u_store(1); Digital system for spiking neural network emulation 91 end if; end if; end process; -- Parameters c <= to_signed(-650,width+1); d <= to_signed(80,width+1); thresh <= to_signed(300,width+1); -- "v" Pipeline process (CLK) begin if (CLK='1' and CLK'event) then if (EN='1') then v3 <= resize( shift_right(v_n*v_n,8) -- v_n^2/256 + shift_left(v_n,1) + shift_left(v_n,2) -- v_n + 5*v_n + to_signed(1400,width+1) -- + 1400 - u_n + I,v3'length); -- - u_n + I end if; end if; end process; Spike <= '1' when v3 > thresh else '0'; v_n1 <= c when RST = '1' else v3 when Spike = '0' else c when Spike = '1' else (others => '0'); Spike_out <= Spike; -- "u" Pipeline u1 <= shift_right(v_n,2); -- v_n/4 u2 <= u1-u_n; -- v_n/4 - u_n u3 <= shift_right(u2,6); -- (v_n/4 - u_n)/64 u4 <= u_n + u3; -- u_n + (v_n/4 - u_n)/64 u5 <= u4+d; -- u_n + (v_n/4 - u_n)/64 + d u_n1 <= u4 when RST = '1' else u4 when Spike = '0' else u5 when Spike = '1' else (others => '0'); end Behavioral; Eduard-Guillem Merino Mallorquí 92 1.3. RAM ------------------------------------------------------------------------- -- Engineer: Eduard-Guillem Merino Mallorqui -- Create Date: 10:00:00 03/05/2017 -- Module Name: RAM_09 - Behavioral -- Project Name: Digital System for Neural Network Emulation ------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; entity RAM_09 is generic ( number : in integer; width : in integer; neuron_adr : in integer; weights : in integer); port ( clk : in std_logic; we : in std_logic; a : in std_logic_vector(neuron_adr downto 0); dpra : in std_logic_vector(neuron_adr downto 0); di : in std_logic_vector(weights downto 0); dpo : out std_logic_vector(weights downto 0)); end RAM_09; architecture syn of RAM_09 is type ram_type is array (0 to 63) of std_logic_vector(weights downto 0); impure function init_mem(mif_file_name : in string) return ram_type is file mif_file : text open read_mode is mif_file_name; variable mif_line : line; variable temp_bv : bit_vector(weights downto 0); variable temp_mem : ram_type; begin for i in ram_type'range loop readline(mif_file, mif_line); read(mif_line, temp_bv); temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; signal RAM : ram_type := init_mem("C:\Users\emerino\Desktop\SNN_1\RAM\RAM" & INTEGER'IMAGE(number) & ".mif"); begin process (clk) begin if (clk'event and clk = '1') then Digital system for spiking neural network emulation 93 if (we = '1') then RAM(conv_integer(a)) <= di; end if; end if; end process; dpo <= RAM(conv_integer(dpra)); end syn; Eduard-Guillem Merino Mallorquí 100 ##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 set_property PACKAGE_PIN R6 [get_ports {Image[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[3]}] ##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 set_property PACKAGE_PIN R5 [get_ports {Image[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[4]}] ##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 set_property PACKAGE_PIN V7 [get_ports {Image[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[5]}] ##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 set_property PACKAGE_PIN V6 [get_ports {Image[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[6]}] ##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 set_property PACKAGE_PIN V5 [get_ports {Image[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[7]}] ##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 set_property PACKAGE_PIN U4 [get_ports {Image[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[8]}] ##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 set_property PACKAGE_PIN V2 [get_ports {Image[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {Image[9]}] ##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 set_property PACKAGE_PIN U2 [get_ports {Neuron[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[0]}] ##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 set_property PACKAGE_PIN T3 [get_ports {Neuron[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[1]}] ##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 set_property PACKAGE_PIN T1 [get_ports {Neuron[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[2]}] ##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 set_property PACKAGE_PIN R3 [get_ports {Neuron[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[3]}] ##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 set_property PACKAGE_PIN P3 [get_ports {Neuron[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[4]}] ##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 set_property PACKAGE_PIN P4 [get_ports {Neuron[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Neuron[5]}] ##Pmod Header JA ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 set_property PACKAGE_PIN B13 [get_ports {Spikes_out[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[0]}] Digital system for spiking neural network emulation 101 ##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 set_property PACKAGE_PIN F14 [get_ports {Spikes_out[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[1]}] ##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 set_property PACKAGE_PIN D17 [get_ports {Spikes_out[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[2]}] ##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 set_property PACKAGE_PIN E17 [get_ports {Spikes_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[3]}] ##Pmod Header JB ##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 set_property PACKAGE_PIN G14 [get_ports {Spikes_out[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[4]}] ##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 set_property PACKAGE_PIN P15 [get_ports {Spikes_out[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Spikes_out[5]}] Eduard-Guillem Merino Mallorquí 102 3. Simulation Sources 1.1. Top entity – Testbench ------------------------------------------------------------------------- -- Engineer: Eduard-Guillem Merino Mallorqui -- Create Date: 11:40:19 03/03/2017 -- Module Name: Top - Testbench -- Project Name: Digital System for Neural Network Emulation ------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; ENTITY Testbench IS Generic ( image_num : integer := 9; width : integer := 12; neuron_adr : integer := 5; -- Up to 32 neuron_adr weights : integer := 10; -- 255 downto -256 input_neuron_num : integer := 40; -- Number of virtual neurons +1 training_neuron_num : integer := 6; -- Number of training neurons neuron_num : integer := 46); -- Number of neurons +1 END Testbench; ARCHITECTURE behavior OF Testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Top PORT( CLK : in STD_LOGIC; RST : in STD_LOGIC; BTN : in STD_LOGIC; SEL : in STD_LOGIC; Image : in STD_LOGIC_VECTOR(image_num downto 0); Neuron : in STD_LOGIC_VECTOR(neuron_num-input_neuron_num-1 downto 0); Spikes_out : out STD_LOGIC_VECTOR(neuron_num-input_neuron_num-1 downto 0)); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; signal BTN : std_logic := '0'; signal SEL : std_logic := '0'; signal Image : std_logic_vector(image_num downto 0) := (others => '0'); signal Neuron : std_logic_vector(neuron_num-input_neuron_num-1 downto 0) := (others => '0'); --Outputs Digital system for spiking neural network emulation 103 signal Spikes_out : STD_LOGIC_VECTOR(neuron_num-input_neuron_num-1 downto 0) := (others => '0'); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Top PORT MAP ( CLK => CLK, RST => RST, BTN => BTN, SEL => SEL, Image => Image, Neuron => Neuron, Spikes_out => Spikes_out ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. RST<='1'; wait for CLK_period*5; RST<='0'; wait for 200us; Image <= (0=>'1',others => '0'); -- 0 Neuron <= (0=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; Image <= (1=>'1',others => '0'); -- 1 Neuron <= (1=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; Image <= (2=>'1',others => '0'); -- 2 Neuron <= (2=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; Image <= (3=>'1',others => '0'); -- 3 Eduard-Guillem Merino Mallorquí 104 Neuron <= (3=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; Image <= (4=>'1',others => '0'); -- 4 Neuron <= (4=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; Image <= (5=>'1',others => '0'); -- 5 Neuron <= (5=>'1',others => '0'); BTN<='1'; wait for 10us; BTN<='0'; wait for 600us; SEL<='1'; Neuron <= (others => '0'); Image <= (0=>'1',others => '0'); wait for 400us; Image <= (1=>'1',others => '0'); wait for 400us; Image <= (2=>'1',others => '0'); wait for 400us; Image <= (3=>'1',others => '0'); wait for 400us; Image <= (4=>'1',others => '0'); wait for 400us; Image <= (5=>'1',others => '0'); wait for 400us; Image <= (others => '0'); RST <='1'; wait for 20us; BTN<='1'; wait for 1000us; RST <='0'; BTN<='0'; Neuron <= (others => '0'); Image <= (0=>'1',others => '0'); wait for 400us; Image <= (1=>'1',others => '0'); wait for 400us; Image <= (2=>'1',others => '0'); wait for 400us; Image <= (3=>'1',others => '0'); wait for 400us; Image <= (4=>'1',others => '0'); wait for 400us; Image <= (5=>'1',others => '0'); wait for 400us; Image <= (others => '0'); Digital system for spiking neural network emulation 105 wait; end process; END; Eduard-Guillem Merino Mallorquí 106 1.2. Izhikevich Neuron – Testbench ------------------------------------------------------------------------- -- Engineer: Eduard-Guillem Merino Mallorqui -- Create Date: 14:27:19 02/17/2017 -- Module Name: IZH_Neuron - Testbench -- Project Name: Digital System for Neural Network Emulation ------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; ENTITY Testbench IS GENERIC( number : integer := 0; width : integer := 12; neuron_adr : integer := 5; weights : integer := 10); END Testbench; ARCHITECTURE behavior OF Testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT IZH_Neuron GENERIC( number : in integer; width : in integer; neuron_adr : in integer; weights : in integer); PORT( CLK : in std_logic; RST : in std_logic; EN : in std_logic; WE : in std_logic; Addr : in std_logic_vector(neuron_adr downto 0); Weight : in std_logic_vector(weights downto 0); AER_Bus : in std_logic_vector(neuron_adr downto 0); Spike_out : out std_logic); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; signal EN : std_logic := '0'; signal WE : std_logic := '0'; signal Addr : std_logic_vector(neuron_adr downto 0) := (others => '0'); signal Weight : std_logic_vector(weights downto 0) := (others => '0'); signal AER_Bus : std_logic_vector(neuron_adr downto 0) := (others => '0'); --Outputs signal Spike_out : std_logic; Digital system for spiking neural network emulation 107 -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: IZH_Neuron GENERIC MAP ( number => number, width => width, neuron_adr => neuron_adr, weights => weights) PORT MAP ( CLK => CLK, RST => RST, EN => EN, WE => WE, Addr => Addr, Weight => Weight, AER_Bus => AER_Bus, Spike_out => Spike_out ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. EN<='1'; RST<='1'; AER_Bus <= (others=>'1'); wait for CLK_period*5; RST<='0'; wait for 50 ns; WE<='1'; Weight <= std_logic_vector(to_signed(120,Weight'length)); Addr <= std_logic_vector(to_signed(1,Addr'length)); wait for 50 ns; WE<='0'; wait for 50 ns; AER_Bus <= std_logic_vector(to_signed(1,AER_Bus'length)); wait; end process; END; Eduard-Guillem Merino Mallorquí 108 1.3. AER Bus – Testbench ------------------------------------------------------------------------- -- Engineer: Eduard-Guillem Merino Mallorqui -- Create Date: 11:40:19 03/03/2017 -- Module Name: AER_Bus - Testbench -- Project Name: Digital System for Neural Network Emulation ------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; ENTITY Testbench IS Generic ( neuron_adr : integer := 4; -- Up to 32 neuron_adr neuron_num : integer := 4); -- Number of neurons +1 END Testbench; ARCHITECTURE behavior OF Testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AER_Bus GENERIC( neuron_adr : in integer; neuron_num : in integer); PORT( CLK : in STD_LOGIC; Spikes : in STD_LOGIC_VECTOR(neuron_num downto 0); EN_Neuron : out STD_LOGIC; AER : out STD_LOGIC_VECTOR(neuron_adr downto 0)); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal Spikes : std_logic_vector(neuron_num downto 0) := (others => '0'); --Outputs signal EN_Neuron : STD_LOGIC := '0'; signal AER : STD_LOGIC_VECTOR(neuron_adr downto 0) := (others => '0'); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: AER_Bus GENERIC MAP ( neuron_adr => neuron_adr, neuron_num => neuron_num) PORT MAP ( CLK => CLK, Spikes => Spikes, EN_Neuron => EN_Neuron, Digital system for spiking neural network emulation 109 AER => AER ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. Spikes <= "00000"; wait for 10 ns; Spikes <= "00001"; wait for CLK_period; Spikes <= "00000"; wait for 20 ns; Spikes <= "11011"; wait for CLK_period; Spikes <= "00000"; wait for CLK_period; Spikes <= "00110"; wait for CLK_period; Spikes <= "00000"; wait; end process; END;