Local secondary control for inverter-based islanded microgrids with accurate active-power sharing under high load conditions

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS  Abstract—Local secondary control has been successfully used to regulate the frequency of inverterbased islanded microgrids without using communications. In this scenario, noticeable steady-state deviations have been observed in active power sharing caused by the inherent clock drift of the digital processors that implement each inverter local control. This paper presents a control scheme that performs frequency regulation and improves the active power sharing under high load conditions, thus alleviating the impact of clock drifts in this situation. The study introduces a theoretical analysis that quantifies the steady-state deviations in active power sharing. It also includes a design procedure for the control parameters based on static and dynamic specifications. Experimental tests validate the expected features of the proposed control. The experimental setup is based on a laboratory microgrid equipped with three independent digital signal processors with different clock drifts. Index Terms—Inverter-based microgrids, islanded operation, frequency regulation, power sharing. I. INTRODUCTION IERARCHICAL control is widely used today to manage the operation of inverter-based islanded microgrids [1], [2]. This control policy is organized in several layers to meet different control objectives [3], [4]. The primary layer is responsible for the sharing of the load power. It is normally implemented using the well-known droop control method [5]. The secondary layer is responsible for the regulation of the microgrid frequency. Its purpose is to remove the frequency Manuscript received December 21, 2017; revised May 3, 2018; accepted May 29, 2018. This work was supported by ELAC2014/ ESE0034 from the European Union and its linked Spanish national project PCIN-2015-001. We also appreciate the support from the Ministry of Economy and Competitiveness of Spain and the European Regional Development Fund (FEDER) under project ENE2015-64087C2-1-R. M. Castilla, A, Camacho and J. Miret are with the Electronic Engineering Department, Technical University of Catalonia, Av. Victor Balaguer s/n, 08800 Vilanova i la Geltrú, Spain, email: {miquel.castilla, antonio.camacho.santiago, jaume.miret}@upc.edu, M. Velasco and P. Martí are with the Automatic Control Department, Technical University of Catalonia, Pau Gargallo 5, 08028 Barcelona, Spain, email: {manel.velasco, pau.marti}@upc.edu, steady-state deviations introduced by the droop control method [5], [6]. The tertiary layer is responsible for the energy dispatching and power balance. Its target is to optimize operational costs and durability [7], [8]. Focusing on the use of the communication service, normally the primary layer is a control that uses only local measures while the tertiary layer is a communication-based control [8]. For the secondary layer, most of the control schemes use the communication service [9]-[14]. In centralized approaches, the secondary control is implemented in a central controller that calculates the corrective terms that compensate the frequency deviations and sends them to the inverters’ control units [3], [9]. In distributed approaches, each local controller implements its own secondary layer using both local measures and data received from other controllers through the communication service. Distributed averaging and consensus are two examples of communication-based secondary control schemes [10], [11]. In both cases, the microgrid frequency is regulated by the cooperative action of the inverters [12], [13]. Droop-free distributed control is another communication-based control scheme for frequency regulation in microgrids [14]. This is an alternative implementation to the consensus algorithm in which the functions of the primary and secondary control are achieved without separating the control system in layers, thus flattering the hierarchical control structure. Both centralized and distributed control schemes based on communications have excellent performance. In fact, with these schemes, the power sharing and frequency regulation show insignificant steadystate errors. However, in digital communication networks, messages suffer from delays and dropouts that can degrade the microgrid performance. This degradation has been reported in several studies, see for instance [15]-[18]. It is worth mentioning that the operation of the microgrid may become unstable when a certain percentage of dropouts is exceeded, e.g., see [18]. Even with these adverse effects, the communication service is today an important element in microgrids. But a tendency to reduce the use of communications in the control system of the microgrid is observed in some recent studies [19]-[23]. The idea is to implement several functionalities of the control system without data interchange between the local control units of the Local Secondary Control for Inverter-based Islanded Microgrids with Accurate ActivePower Sharing under High Load Conditions Miguel Castilla, Antonio Camacho, Jaume Miret, Member IEEE, Manel Velasco, and Pau Martí H This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS microgrid. This is inherently done in the primary layer by the droop control method. For the secondary layer, communication-less control schemes have been presented in [19]-[23]. Since they do not use the communication service, they are insensible to communication delays and dropouts. Moreover, with these control schemes, the security, confidentiality and integrity of the microgrid is improved due to the reduction of malicious cyberattacks [23]. The price to pay is a slight loss of quality in power sharing and frequency regulation, as reported in [20] and [21]. In addition to the communication constraints, another technological issue that affects the practical operation of inverter-based microgrids is the drift in the local controller clocks [24], [25]. Each inverter operates with its own digital processor and the clock used to generate the time signal of this processor differs from the time signals of the other processors due to the clock drifts. In the droop-based primary layer, the impact of clock drifts is nearly negligible, as shown in [25]. However, the effects in the secondary layer highly depend on the selected control algorithm. Using local integral controllers in the secondary layer, the steady-state operation of the microgrid tends to an unstable equilibrium point, as stated in [26]. Using the droop-free control scheme, the performance is good and the effects of clock drifts can be considered negligible when the control parameters are properly adjusted [27]. However, when a key control parameter is not carefully tuned, large errors in active power sharing appear. The local secondary control based on distributed low-pass filters (DLPF) analyzed in [28] exhibits a similar problem with power sharing. With this scheme, the difference in the active power supplied by the inverters is a constant value for all load conditions. Moreover, this value can be large in some circumstances, as discussed in detail in the next section. It is worth mentioning that the error in active power sharing represents a negative impact on the system performance during high load conditions. In this case, the active power supplied by the inverters is high and mismatches in power sharing may produce both excessive stress and poor thermal distribution in the inverters. The source of the active power deviations is the different values of the line impedances when primary and secondary control layers are not implemented in the local control units, as shown in [18]. However, using the droop control in the primary layer, the different line impedances have no effect in power sharing, as demonstrated in [24] and [25]. The fact that the clock drifts cause active power deviations using different secondary control layers is revealed in [26]-[28]. In particular, in [27], it is verified experimentally that different clock drifts provoke different active power deviations. Conversely, the effect of the clock drifts on the sharing of reactive power is negligible, as confirmed experimentally in [27]. The main reason for this is that: 1) the clock drifts cause a direct error only at the inverter operating frequencies (and indirectly at the active powers due to the coupling between frequency and active power through the droop-based control scheme) and 2) the coupling between active and reactive power through the power flow equations is low and, therefore, the errors in active power are not practically transferred to the reactive power. In view of this, the control schemes for voltage and reactive power are not included in this study. Interested readers can see [5] for a recent review of these control schemes. This paper focuses on improving the performance of secondary control schemes that do not require communications for the control purposes. The local DLPFbased secondary control [20] is taken as a starting point for the study. The paper presents a new control algorithm that provides accurate active power sharing under high load conditions. And this feature is achieved even in real applications with the presence of different clock drifts in the digital signal processors implementing the local control. Thanks to this characteristic, the thermal load is distributed better along the system, which avoids the hot spots in the power inverters during high load conditions. In addition, the maximum injected currents coincide, which prevent excessive stress in the power switches and other passive components. For low load conditions, power sharing deviation is not a relevant problem since the current and power of the inverters are small and their differences will have no impact on the stress and thermal distribution of the inverters. From a theoretical point-of-view, the study includes a static analysis that quantifies the steady-state deviations in active power sharing. It also presents a design procedure for the control parameters including considerations based on static and dynamic specifications. Selected experimental tests validate the advantages and limitations of the proposed control scheme. The experimental tests were carried out in a laboratory microgrid equipped with three inverters driven by three digital signal processors, each one enabled with its own clock, thus reproducing real applications affected by distributed clock that inherently drift. The rest of the paper is organized as follows. Section II presents the problem statement, including the description of the inverter-based microgrid and the practical limitations of the local DLPF-based secondary control. Section III proposes a control scheme that reduces the impact of clock drifts on the active power sharing under high load conditions. In addition, a theoretical study derives the particular features of the proposal using static and dynamic analytical tools. Section IV presents guidelines to design the parameters of the proposed control. Section V validates the theoretical results by experimental tests. Section VI presents a sensitivity analysis and a discussion on the results. Section VII concludes the study. II. PROBLEM STATEMENT This section presents the inverter-based islanded microgrid, reviews the standard local control scheme for the primary and secondary layers, and provides the problem formulation. A. Inverter-based Islanded Microgrid Fig. 1 shows a diagram of the laboratory three-phase microgrid considered in this study. Table I lists the nominal values of its components. This microgrid is tested to experimentally validate the features of the control proposed in next section. This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS The microgrid consists of three power inverters (INV i), which generate its internal current and voltage waveforms at the frequency 𝜔𝑖 and deliver the active power 𝑃𝑖 to the load (𝑃𝐿). The impedances 𝑍𝐼𝑁𝑉𝑖 and 𝑍𝑖 model the output impedances of the inverters and the line impedances of the distribution cables, respectively. A digital signal processor (DSP i) controls the output of each inverter using only local measurements. The three processors have autonomous clocks that generate time 𝑡𝑖 that differs between inverters (𝑡𝑖≠𝑡𝑗) due to clock drifts. The local time 𝑡𝑖 can be written as a function of the global time t as [24], [25] 𝑡𝑖=(1+𝑑𝑖)𝑡 (1) where 𝑑𝑖 is the clock drift rate of the i processor. Ideally, the clock drift rate is 𝑑𝑖=0. In practice, all clocks have drifts with very small values (typically, several parts per million, ppm). Table I lists the measured clock drift rates of the three processors shown in Fig. 1 [28]. Note that the clock of the DSP 2 is chosen to represent the global time of the microgrid. This choice is made only to carry out the theoretical analysis of the system. The reference frequency of each inverter 𝜔𝑖∗ is generated using the local time 𝑡𝑖. The power inverters force the local frequency 𝜔𝑖 to follow the reference frequency 𝜔𝑖∗ in order to regulate the frequency of the microgrid and supply the load cooperatively. As discussed next, active power steady-state errors are observed due to the clock drifts. B. Control Objectives The control objectives of the inverters shown in Fig. 1 are formulated in steady-state as follows: 1) To provide accurate power sharing (i.e., the power of the inverters must be proportional to its power rating while guaranteeing the supply of the load), which can be formulated as 𝑃𝑖,𝑠𝑠 𝑖𝑑 =𝑃𝐿∑(𝑚𝑖 𝑚𝑗). 𝑛 𝑗=1 ⁄ (2) In (2), 𝑃𝑖,𝑠𝑠 𝑖𝑑 is the ideal power provided by each inverter in steady state. In this context, ideal power means the power supplied by each inverter assuming that the clock drift rate is zero, 𝑑𝑖=0. Moreover, 𝑃𝐿 is the load power and 𝑚𝑖 and 𝑚𝑗 are two parameters related to the rated power of the inverters. They will be formally defined in the following subsection. 2) To regulate the frequency of the microgrid in steady-state 𝜔𝑠𝑠 to its nominal value 𝜔0, which can be formulated as 𝜔𝑠𝑠 =𝜔0. (3) Due to clock drifts, the steady-state active power delivered by each inverter 𝑃𝑖,𝑠𝑠 is different to the ideal power 𝑃𝑖,𝑠𝑠 𝑖𝑑 . The difference between these two values depends on the control scheme used for the primary and secondary layers, as discussed in [25]-[28]. In addition, the steady-state microgrid frequency deviates from the nominal frequency [24]. These deviations are quantified by the active power and frequency steady-state errors as follows 𝑒𝑃𝑖,𝑠𝑠 =100𝑃𝑖,𝑠𝑠−𝑃𝑖,𝑠𝑠 𝑖𝑑 𝑃𝑖𝑚𝑎𝑥 (4) 𝑒𝑓𝑠𝑠 =𝜔𝑠𝑠−𝜔0 2𝜋 (5) where 𝑃𝑖𝑚𝑎𝑥 is the maximum power of the INV i; see Table I. C. Local Hierarchical Control without Communications The hierarchical control without communications considered in this paper uses the droop method in the primary layer and the DLPF technique in the secondary layer. Fig. 2 shows a diagram of this standard control [20]. From Fig. 2, the reference frequency is generated as 𝜔𝑖∗(𝑡𝑖)=𝜔0−𝑚𝑖𝑃𝑖(𝑡𝑖)+𝛿𝑖(𝑡𝑖) (6) where 𝜔0 is the operating frequency of the inverter at no load (NL), 𝑚𝑖 is the slope of the droop function and 𝑃𝑖 is the averaged active power. This last variable is calculated using a low-pass filter 𝐿𝑃𝐹𝑃 with cutoff frequency 𝜔𝑃 (the frequency sub-index P indicates primary layer) Fig. 1. Diagram of the inverter-based islanded microgrid. P t 2 2 INV 2 ω2 * ω2 Z2 P t 1 1 INV 1 ω1 * ω1 Z1 P t 3 3 INV 3 ω3 * ω3 Z3 Z4P L ZINV2 ZINV1ZINV3 DSP 1 DSP 2 DSP 3 TABLE I NOMINAL VALUES OF THE MICROGRID COMPONENTS Symbol Quantity Nominal value n Number of inverters 3 𝑃𝑖𝑚𝑎𝑥 Maximum power of inverters 910 W 𝑃𝐿𝑚𝑎𝑥 Maximum load power 2730 W 𝑉𝑖 Phase voltage 110 Vrms 𝜔0 Angular frequency 2 60 rad/s 𝑍𝐼𝑁𝑉.𝑖 Output impedance of inverters 0 + j 3.77 Ω 𝑍1 Line impedance 1 0.50 + j 1.13 Ω 𝑍2 Line impedance 2 0.50 + j 0.38 Ω 𝑍3 Line impedance 3 1.13 + j 0.23 Ω 𝑍4 Line impedance 4 0 + j 0.30 Ω 𝑑1 Clock drift rate in DSP1 -1.69 ppm 𝑑2 Clock drift rate in DSP2 0 𝑑3 Clock drift rate in DSP3 2.81 ppm This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 𝑃𝑖(𝑡𝑖)=𝜔𝑃∫(𝑝𝑖(𝑡𝑖)−𝑃𝑖(𝑡𝑖))𝑑𝑡𝑖 (7) where the instantaneous active power 𝑝𝑖 is the input of the filter. Additionally, 𝛿𝑖(𝑡𝑖) in (6) is the output of the secondary layer, as shown in Fig. 2, which is implemented using the DLPF technique as follows [20] 𝛿𝑖(𝑡𝑖)=𝜔𝑆∫(𝛼𝑆(𝜔0−𝜔𝑖∗(𝑡𝑖))−𝛿𝑖(𝑡𝑖))𝑑𝑡𝑖. (8) In (8), the input of the low-pass filter 𝐿𝑃𝐹𝑆 is 𝜔0−𝜔𝑖∗; see Fig. 2. Moreover, the control parameters 𝛼𝑆 and 𝜔𝑆 are the gain and cutoff frequency of the filter, respectively. In this case, the frequency sub-index S indicates secondary layer. It is possible to deactivate the secondary layer by setting 𝛼𝑆=0; see Fig. 2. Thus, the standard control in (6) operates only with the droop-based primary layer due to 𝛿𝑖(𝑡𝑖)=0. Table II lists the nominal parameter values of the standard control. These values were designed following the guidelines reported in [3] for the primary layer (𝑚𝑖 and 𝜔𝑃) and in [20] for the secondary layer (𝛼𝑆 and 𝜔𝑆). D. Problem Formulation A procedure to determine the static characteristics of the standard control was presented in [28]. From this study, the steady-state errors in active power and frequency as a function of the clock drift rates can be written as: 𝑒𝑃𝑖,𝑠𝑠 =𝜔0(1+𝛼𝑆)∑(𝑑𝑖−𝑑𝑗 𝑚𝑗) 𝑛 𝑗=1 ∑(𝑚𝑖 𝑚𝑗) 𝑛 𝑗=1 ⁄ (9) 𝑒𝑓𝑠𝑠 =−𝑃𝐿 2𝜋(1+𝛼𝑆)∑(1 𝑚𝑗) 𝑛 𝑗=1 ⁄ . (10) The performance characteristics of the droop control can be derived using 𝛼𝑆=0 in (9) and (10). Fig. 3 illustrates them as a function of load using the parameters listed in Tables I and II. Note that the difference in the active power delivered by each inverter is negligible, which confirms that clock drifts have an insignificant effect on the droop-based power sharing, as announced in [25]. However, there is a large deviation in the microgrid frequency, which increases with load. In particular, the frequency deviation is 147 mHz at full load (FL). In real applications, this deviation is not enough to activate the under-frequency protection of the inverters, which is normally set at 600 mHz below the nominal frequency [5]. Consequently, the frequency deviation is not a relevant problem in the microgrids deployed to operate only in islanded mode. However, in those applications operating in both gridconnected and islanded mode, it is advised not to have large frequency deviations in islanded mode to facilitate a smooth transition to grid-connected mode [2]. Fig. 4 shows the active powers and the frequency errors as a function of load for the standard control. Two values of 𝛼𝑆 are considered in this figure. With 𝛼𝑆= 40 (nominal value), the error in the frequency is significantly reduced compared to the results of the droop control, as seen in Fig. 3(a). In fact, the frequency deviation at FL is only 3.5 mHz. With this value, the transition from islanded to grid-connected mode is greatly facilitated. The price to pay for this low frequency deviation is a deterioration in power sharing with a constant deviation of 4% for all load conditions. A second value of 𝛼𝑆 higher than the nominal one is considered to observe the deterioration of power sharing produced when 𝛼𝑆 is increased. With 𝛼𝑆= 160, although the error in frequency becomes insignificant (0.9 mHz at FL), the error in active power is 16% for all the load range; see Fig. 4(b). This feature is particularly negative at high load conditions, when the practical consequences of the power deviation such as excessive stress and poor thermal management aggravate. Therefore, the problem of power sharing deviations produced by the clock drifts is more relevant in scenarios at high load conditions. II. PROPOSED LOCAL SECONDARY CONTROL The aim of this study is to introduce a local secondary control with accurate power sharing and good frequency regulation in high load conditions. This section presents the proposed control and an analysis that reveals its static and dynamic features. A. Control Architecture A new control scheme is derived starting from the standard control expressed in (6). Since the goal is to reduce the Fig. 2. Diagram of the local control without communications. TABLE II NOMINAL PARAMETER VALUES OF THE STANDARD CONTROL Symbol Quantity Nominal value 𝑚𝑖 Slope of the droop function 1 mrad/(Ws) 𝜔𝑃 Primary-layer cutoff frequency 2 rad/s 𝜔𝑆 Secondary-layer cutoff frequency 20 rad/s 𝛼𝑆 Gain of the secondary layer 40 i* 𝜔 + _ 𝐿𝑃𝐹 P 𝜔+ 0 𝜔 𝐿𝑃𝐹 S 𝜔 _ +0 𝜔 i 𝑃 i 𝑝𝑚i 𝛼S i 𝛿 P S Fig. 3. Active powers and frequency errors in steady-state versus load for the droop control (i.e., the standard control with 𝛼𝑆=0). 0.0 0.25 0.5 0.75 1.0 Active Power (kW) P1,ss P2,ss P3,ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -160 -120 -80 -40 0 Freq. error (mHz) PL (kW) efss This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS deviations in power sharing, a new error equation for the active power is considered 𝑒𝑃𝑖=𝑘𝑆𝑃𝑖𝑚𝑎𝑥 −𝑃𝑖(𝑡𝑖) (11) where 𝑘𝑆 is a control parameter. This error is zero at the desired active power according to the value of 𝑘𝑆. This property is used to obtain an accurate power sharing under high load conditions by including (11) in (6) and by properly setting the 𝑘𝑆 parameter. The design of this parameter is presented in Section IV. In particular, the error term in (11) is multiplied by the output of the DLPF in (8), resulting in the new reference frequency, leading to 𝜔𝑖∗(𝑡𝑖)=𝜔0−𝑚𝑖𝑃𝑖(𝑡𝑖)+𝛿𝑖(𝑡𝑖)(𝑘𝑆𝑃𝑖𝑚𝑎𝑥−𝑃𝑖(𝑡𝑖)) (12) In (12), the averaged active power 𝑃𝑖 and the output of the DLPF 𝛿𝑖 are calculated using (7) and (8), respectively. A diagram of the proposed control is shown in Fig. 5. B. Static Characteristics The static performance of the proposed control is determined by the steady-state errors in active power and frequency. The error expressions are derived by applying the analysis procedure presented in [28] to (7), (8) and (12). The results are written as 𝑒𝑃𝑖,𝑠𝑠 = (13) 𝜔0(1+𝛼𝑆(𝑘𝑆𝑃𝑖𝑚𝑎𝑥 −𝑃𝑖,𝑠𝑠 𝑖𝑑 ))∑(𝑑𝑖−𝑑𝑗 𝑚𝑗) 𝑛 𝑗=1 ∑(𝑚𝑖 𝑚𝑗) 𝑛 𝑗=1 ⁄ 𝑒𝑓𝑠𝑠 =−𝑃𝐿 2𝜋(1+𝛼𝑆(𝑘𝑆𝑃𝑖𝑚𝑎𝑥 −𝑃𝑖,𝑠𝑠 𝐼𝐷)) ∑(1 𝑚𝑗) 𝑛 𝑗=1 ⁄ . (14) Fig. 6 shows the active powers and frequency errors using the parameters listed in Table I and in the figure caption. The proposed control has the ability to improve the power sharing as the load increases, reaching negligible errors at FL. The price to pay for this improvement in power sharing is a larger deviation in frequency compared to the standard control. Both accurate power sharing at FL and small frequency deviation are guaranteed by the design of the proposed control with the systematic procedure presented in Section IV. C. Dynamic Characteristics The phase margin and the control bandwidth are the metrics considered in this study to evaluate the dynamic performance of the proposed control. Below a procedure to derive the open loop transfer function 𝑇𝑖(𝑠) for the standard and the proposed control is presented. The dynamic characteristics are measured from this transfer function. (a) (b) Fig. 4. Active powers and frequency errors in steady-state versus load for the standard control with (a) 𝛼𝑆=40 and (b) 𝛼𝑆=160. Fig. 5. Diagram of the proposed control. 0.0 0.25 0.5 0.75 1.0 Active Power (kW) P1,ss P2,ss P3,ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -12.0 -9.0 -6.0 -3.0 0 Freq. error (mHz) PL (kW) efss 0.0 0.25 0.5 0.75 1.0 Active Power (kW) P1,ss P2,ss P3,ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -12.0 -9.0 -6.0 -3.0 0 Freq. error (mHz) PL (kW) efss i* 𝜔 + _ 𝐿𝑃𝐹 P 𝜔+ 0 𝜔 𝐿𝑃𝐹 S 𝜔 _ +0 𝜔 i 𝑃 i 𝑝𝑚i 𝛼S _ + S 𝑘i 𝛿 i max 𝑃S P (a) (b) Fig. 6. Active powers and frequency errors in steady-state versus load for the proposed control with (a) 𝛼𝑆=0.03, 𝑘𝑆=1.41 and (b) 𝛼𝑆=0.16, 𝑘𝑆=1.08. 0.0 0.25 0.5 0.75 1.0 Active Power (kW) P1,ss P2,ss P3,ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -12.0 -9.0 -6.0 -3.0 0 Freq. error (mHz) PL (kW) efss 0.0 0.25 0.5 0.75 1.0 Active Power (kW) P1,ss P2,ss P3,ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -12.0 -9.0 -6.0 -3.0 0 Freq. error (mHz) PL (kW) efss This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 7 shows the small-signal model of an inverter with hierarchical control. The transfer functions 𝐺𝑖(𝑠) and 𝐻𝑖(𝑠) represent the small-signal models of the inverter and the control, respectively. In Fig. 7, the hat ^ denotes small-signal variables and s is the Laplace operator. Small-signal models of droop-controlled inverters have been extensively studied in the literature for stability analysis [3], [10]. In particular, dynamic phasor modeling provides accurate models by preserving dynamics neglected by other approaches [29]. This study uses the dynamic phasor model reported in [30] for an inverter connected to a microgrid. The transfer function of the inverter 𝐺𝑖(𝑠)=𝑝𝑖(𝑠) 𝜔𝑖∗(𝑠) ⁄ can be written as 𝐺𝑖(𝑠)= 𝜔0𝐿𝑖𝑉𝑖2 ((𝐿𝑖𝑠+𝑅𝑖)2+(𝜔0𝐿𝑖)2)𝑠 (15) where 𝑅𝑖 and 𝜔0𝐿𝑖 are the real and imaginary parts of the impedances seen from the output side of the inverters. These values are calculated from Fig. 1 and listed in Table III. The digital processors that implement the local hierarchical control have individual clocks. Therefore, the transfer functions of the control system will rely on the drift rates of these clocks. These functions are derived as follows: 1) Write the model in the time domain as a function of the local clock that generate time 𝑡𝑖. 2) Rewrite the model in the time domain as a function of the global clock t using (1). 3) Write the model in the frequency domain using the Laplace transform. From (7) and (8), the transfer function of the low-pass filters in the primary and secondary layers can be expressed as 𝐿𝑃𝐹𝑃(𝑠)=𝑃 𝑖(𝑠) 𝑝𝑖(𝑠)=(1+𝑑𝑖)𝜔𝑃 𝑠+(1+𝑑𝑖)𝜔𝑃 (16) 𝐿𝑃𝐹𝑆(𝑠)=𝛿󰆹𝑖(𝑠) 𝜔0(𝑠)−𝜔𝑖∗(𝑠)=𝛼𝑆(1+𝑑𝑖)𝜔𝑆 𝑠+(1+𝑑𝑖)𝜔𝑆. (17) For the standard control, the reference frequency is obtained by inserting (17) in the frequency domain version of (6) 𝜔𝑖∗(𝑠)=𝜔0(𝑠)−𝑚𝑖𝐿𝑃𝐹𝑃(𝑠) 1+𝐿𝑃𝐹𝑆(𝑠)𝑝𝑖(𝑠). (18) From (18) and Fig. 7, the transfer function of the standard control 𝐻𝑖𝑠𝑡(𝑠) is identified as 𝐻𝑖𝑠𝑡(𝑠)=𝜔𝑐(𝑠) 𝑝𝑖(𝑠)=𝑚𝑖𝐿𝑃𝐹𝑃(𝑠) 1+𝐿𝑃𝐹𝑆(𝑠). (19) Following a similar procedure for the proposed control and using (12) instead of (6), the transfer function 𝐻𝑖𝑝𝑟(𝑠) can be written as 𝐻𝑖𝑝𝑟(𝑠)=𝜔𝑐(𝑠) 𝑝𝑖(𝑠)=(𝑚𝑖+𝛼𝑆(𝜔0−𝜔ss))𝐿𝑃𝐹𝑃(𝑠) 1+(𝑘𝑆𝑃𝑖𝑚𝑎𝑥 −𝑃𝑖,𝑠𝑠)𝐿𝑃𝐹𝑆(𝑠). (20) The open-loop transfer function of the standard and proposed controls can finally be written as 𝑇𝑖𝑠𝑡(𝑠)=𝐺𝑖(𝑠)𝐻𝑖𝑠𝑡(𝑠) (21) 𝑇𝑖𝑝𝑟(𝑠)=𝐺𝑖(𝑠)𝐻𝑖𝑝𝑟(𝑠). (22) From (21), the phase margin and the control bandwidth of the standard control are measured using the parameters listed in Tables I and II. The dynamic characteristics of the droop control can also be obtained using 𝛼𝑆=0 in (17). Table IV collects these measures for both control schemes. Note that the impact of clock drifts on the dynamic characteristics is negligible. This fact is clearly seen in Table IV where the measures of the three inverters show a very small deviation for each control. In addition, the phase margin increases and the control bandwidth decreases when 𝛼𝑆 is changed from 0 to 40 and, therefore, it is expected to observe a slower transient response in the standard control compared to the droop control. Fig. 8 shows the dynamic characteristics as a function of load for both control schemes. Note that the phase margin and the control bandwidth are constant, thus maintaining the dynamic properties for all load conditions. Fig. 9 shows the phase margin and the control bandwidth for the proposed control. These measures are obtained from (22) using the parameters listed in Tables I and II (only 𝑚𝑖 and 𝜔𝑃). For low load conditions, the dynamic characteristics coincide with those obtained in the standard control; see also Table IV. Even more interesting is to observe that the control bandwidth improves as load increases (see Fig. 9), thus guaranteeing a faster transient response. Table IV shows that the control bandwidth is almost a decade larger at FL than at NL. This is an advantage of the proposed control, which is Fig. 7. Diagram of the small-signal model of an inverter with local hierarchical control. TABLE III IMPEDANCE SEEN FROM THE OUTPUT SIDE OF THE INVERTERS Symbol Quantity Nominal value 𝑅1+𝑗𝜔0𝐿1 Impedance seen at inverter 1 0.90 + j 7.02 Ω 𝑅2+𝑗𝜔0𝐿2 Impedance seen at inverter 2 0.93 + j 6.45 Ω 𝑅3+𝑗𝜔0𝐿3 Impedance seen at inverter 3 1.38 + j 6.55 Ω i 0i * 𝜔 𝑝 𝜔 +- 𝐻𝑖(𝑠) 𝐺𝑖(𝑠) c 𝜔 TABLE IV PHASE MARGIN (º) AND CONTROL BANDWIDTH (RAD/S) USING DROOP, STANDARD AND PROPOSED CONTROL Control 𝑃𝑀1 𝑃𝑀2 𝑃𝑀3 𝐵𝑊1 𝐵𝑊2 𝐵𝑊3 Droop 55.9 54.3 55.0 4.22 4.49 4.36 Standard 89.0 88.9 88.9 0.12 0.13 0.13 Prop. (NL) 89.0 88.9 88.9 0.13 0.14 0.13 Prop. (FL) 80.1 79.3 79.6 1.21 1.31 1.26 This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS achieved at the price of slightly reducing the phase margin. The above theoretical analysis shows that the phase margin of the three inverters shown in Fig. 1 is positive; see Table IV. This is true for all loading conditions (from NL to FL). As a consequence, the inverters present a stable operation for all the operating points of the microgrid. In Section V, the stability of the microgrid is validated experimentally. III. CONTROL DESIGN This section presents a systematic procedure to design the parameters of the proposed secondary control layer (𝛼𝑆, 𝑘𝑆 and 𝜔𝑆); see Fig. 5. The parameters of the primary control layer (𝑚𝑖 and 𝜔𝑃) were designed following the guidelines reported in [3]. The procedure is illustrated with a numerical example. A. Design Specifications Table V lists the design specifications of the proposed control and the values used in the numerical example. The maximum error in active power and frequency are the static specifications. In the proposed control, these maximum errors are obtained at NL and FL, respectively, as shown in Fig. 6. The dynamic specifications are the desired phase margin and control bandwidth. To guarantee enough relative stability, the specified phase margin must be analyzed for all the load range conditions. The control bandwidth specification is provided for FL and it is set a decade above the bandwidth of the standard control. B. Design Procedure First, the parameters 𝛼𝑆 and 𝑘𝑆 are designed according to the specifications for the maximum errors in power and frequency. From (13) and (14), these errors can be written as 𝑒𝑃𝑖,𝑁𝐿 𝑚𝑎𝑥 =𝜔0(1+𝛼𝑆𝑘𝑆𝑃𝑖𝑚𝑎𝑥)∑(𝑑𝑖−𝑑𝑗 𝑚𝑗) 𝑛 𝑗=1 ∑(𝑚𝑖 𝑚𝑗) 𝑛 𝑗=1 ⁄ (23) 𝑒𝑓𝑠𝑠 𝑚𝑎𝑥 =−𝑃𝐿𝑚𝑎𝑥 2𝜋(1+𝛼𝑆(𝑘𝑆−1)𝑃𝑖𝑚𝑎𝑥)∑(1 𝑚𝑗) 𝑛 𝑗=1 ⁄ . (24) Note that the maximum error in power sharing takes place at NL (i.e., when 𝑃𝑖,𝑠𝑠 𝑖𝑑 =0), as shown in Fig. 6. Conversely, the maximum deviation in frequency is obtained at FL (i.e., when 𝑃𝑖,𝑠𝑠 𝑖𝑑 =𝑃𝑖𝑚𝑎𝑥). The values of 𝛼𝑆 and 𝑘𝑆 are calculated from (23) and (24) using the parameters shown in Tables I, II (only 𝑚𝑖 and 𝜔𝑃) and V. The results are listed in Table VI. Second, the parameter 𝜔𝑆 is designed according to the dynamic specifications. Fig. 10 shows the phase margin and control bandwidth as a function of this parameter. Note that there is a wide range of values that meet the specifications. In particular, for 𝜔𝑆 > 5 rad/s, it is simultaneously achieved the scenario where the phase margin is higher than 60º and the control bandwidth is 1.3 rad/s. The value 𝜔𝑆 = 20π rad/s is chosen because it belongs to this range and coincides with the Fig. 8. Phase margin and control bandwidth versus load for the droop control (discontinuous lines) and the standard control (continuous lines). Fig. 9. Phase margin and control bandwidth versus load for the proposed control (𝛼𝑆=0.03 and 𝑘𝑆=1.43). 0 20 40 60 80 100 Phase margin (º) PM1PM2PM3PM1PM2PM3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.1 1 10 Bandwidth (rad/s) PL (kW) BW1BW2BW3BW1BW2BW3 0 20 40 60 80 100 Phase margin (º) PM1PM2PM3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.1 1 10 Bandwidth (rad/s) PL (kW) BW1BW2BW3 TABLE V DESIGN SPECIFICATIONS OF THE PROPOSED CONTROL Symbol Quantity Nominal value 𝑒𝑃𝑖,𝑁𝐿 𝑚𝑎𝑥 Maximum error in active power 4% (at NL) 𝑒𝑓𝑠𝑠 𝑚𝑎𝑥 Maximum error in frequency 12 mHz (at FL) 𝑃𝑀 Phase margin Higher than 60 º 𝐵𝑊𝐶 Control bandwidth at full load 1.3 rad/s TABLE VI SOLUTION TO THE DESIGN EXAMPLE OF THE PROPOSED CONTROL Symbol Quantity Nominal value 𝑚𝑖 Slope of the droop function 1 mrad/(Ws) 𝜔𝑃 Primary-layer cutoff frequency 2 rad/s 𝜔𝑆 Secondary-layer cutoff frequency 20 rad/s 𝛼𝑆 Gain of the secondary-layer filter 0.03 W-1 𝑘𝑆 Parameter of the secondary layer 1.43 Fig. 10. Phase margin and control bandwidth vs 𝜔𝑆 for the proposed control (𝛼𝑆=0.03 and 𝑘𝑆=1.43). 30 50 70 90 110 130 Phase margin (º) PM1PM2PM3 0.01 0.1 1.0 10 100 1000 1 10 Bandwidth (rad/s)  S (rad/s) BW1BW2BW3 This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS design of 𝜔𝑆 for the standard control [20]; see Table II. From Fig. 10, it is worth mentioning that there is a range of values, 0.3 rad/s < 𝜔𝑆 < 5 rad/s, in which the control bandwidth is higher than 1.3 rad/s while the phase margin meets the specification. In this case, a faster transient response is expected. However, the design of 𝜔𝑆 inside this range causes undesired interactions between the operation of the primary and secondary control layers. Traditionally, to avoid these interactions, the secondary control bandwidth is designed lower than the primary control bandwidth [3], [4]. This is the control guideline used to specify the value of 𝐵𝑊𝐶 in Table V. IV. EXPERIMENTAL VALIDATION This section validates the theoretical results with a selection of experimental tests that were conducted in the laboratory microgrid shown in Fig. 1. A. Description of the Laboratory Microgrid Fig. 11 shows a photo of the laboratory microgrid. In Fig. 11(a), the blue boxes are three-phase IBGT full-bridge inverters (Guasch, MTL-CBI0060F12IXHF) controlled by dual-core DSPs (TI, Concerto F28M36P63C). The control schemes shown in Fig. 2 and Fig. 5 were programmed in the DSPs with the control gain values listed in Tables II and VI. The inverters supply the load with the power delivered by a DC source (Amrel, SPS800-19) programmed at 𝑉𝐷𝐶 = 350 V. Fig. 11(b) shows a detail of a DSP card, sensing boards and a three-phase inverter. The nominal values of the setup, including microgrid voltage, line impedances and clock drift rates of the DSPs are listed in Table I. The measured results were exported from the DSPs to MATLAB© to achieve a high-quality representation of the figures with experimental results. B. Validation of the Static Characteristics The first test consists on measuring the active powers and frequency errors when the load changes slowly from 10% to 100% of FL. Fig. 12 shows the results of the droop control. As predicted by the theoretical analysis, the impact of clock drifts on the active power is negligible in this control approach. However, the use of a secondary layer is necessary to avoid the large deviation in frequency at FL. Fig. 13 shows the results of the standard control. In this case, the frequency errors are drastically reduced, with a maximum value of 3.2 mHz at FL. This frequency regulation improvement caused by the secondary layer magnifies the deviation in power sharing. In particular, the error in active powers are almost constant for all the load range, being its maximum value 5.9 %. Therefore, the impact of clock drifts is noticeable in the standard control and can be a relevant problem in power sharing under high load conditions. This problem is solved by the proposed control, as shown in Fig. 14. Note that excellent power sharing is reached at high load conditions. In addition, the static specifications are met with a maximum error in active power of 3.9 % at NL and a maximum frequency deviation at FL of 9.3 mHz. Note that at NL the error in active power is similar to that obtained with the standard control. The reason is that the proposed control in (a) (b) Fig. 11. Photo of the laboratory microgrid: (a) complete setup and (b) detail of the DSP card, sensing boards and three-phase inverter. Fig. 12. Experimental active powers and frequency errors for soft load changes using the droop control. Fig. 13. Experimental active powers and frequency errors for soft load changes using the standard control. 0 250 500 750 1000 Active Power (W) P1P2P3 010 20 30 40 50 60 -160 -120 -80 -40 0 error in freq (mHz) Time (s) f1-f0f2-f0f3-f0 0 250 500 750 1000 Active Power (W) P1P2P3 010 20 30 40 50 60 -10 -7.5 -5 -2.5 0 error in freq (mHz) Time (s) f1-f0f2-f0f3-f0 This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS (12) exactly coincides with the standard control in (6) at NL. In other words, the error in (11) does not eliminate the power sharing deviations at NL. It is worth mentioning that this feature is not a relevant problem given that at low load conditions the inverter currents are small, thus the poor termal distribution has a insig-nificant impact on the inverters performance. C. Validation of the Dynamic Characteristics The second test involves changing the load abruptly during the experiment from 10% of FL to FL at t = 5 s and from FL to 10% of FL at t = 35 s. Fig. 15 and 16 show the experimental results for the standard and the proposed control, respectively. As announced above, the transient response of the standard control does not rely on the load. The settling time is 15.2 s for both load changes. In the proposed control, this measure practically coincides with the load change from FL to 10 % of FL, as shown in Fig. 16. The most interesting point is the fast transient response that is achieved with the proposed control during the load change from 10 % of FL to FL with a settling time of only 5.1 s. The static characteristics are confirmed by the results shown in Fig. 15 and 16. In the standard control, the deterioration in power sharing due to the clock drifts does not change for different load conditions. In the proposed control, the error in power sharing is negligible at FL while it nearly coincides with the error in the standard control at 10% of FL. The improvement in power sharing is reached at the price of a largest deviation in frequency. In practice, this maximum deviation is limited by a proper design of the control parameters. It is worth mentioning that the protection algorithms play an important role in the proposed control. If the power approaches its maximum value, then the frequency deviates exponentially, as shown in Fig. 6. Therefore, the protection must ensure that the maximum power is never exceeded. V. WORST CASE ANALYSIS: POWER SHARING AT FL The active power sharing at FL is the main point considered in this study. The proposed control clearly reduces the error in power sharing for the measured values of the clock drift rates, as verified experimentally. This section analyzes the deviations in the active power sharing at FL for the worst case. Recommendations on control design to reduce these deviations are also included. A. Deviations on Active Power Sharing at FL Theoretically, from (13), the error in active power sharing at FL is written as: 𝑒𝑃𝑖,𝐹𝐿 = (25) 𝜔0(1+𝛼𝑆(𝑘𝑆−1)𝑃𝑖𝑚𝑎𝑥)∑(𝑑𝑖−𝑑𝑗 𝑚𝑗) 𝑛 𝑗=1 ∑(𝑚𝑖 𝑚𝑗) 𝑛 𝑗=1 ⁄ . In practice, variations in clock drift rates 𝑑𝑖 and 𝑑𝑗 depend on technological, mechanical and environmental tolerances [31], that may be upper bounded by a given limit of ±𝑑𝑚𝑎𝑥. Environmental changes are caused by temperature, aging and mechanical effects (including shock, vibration and gravity). Normally, the dominant differences in clock drift rates are caused by these tolerances, especially in high-quality crystal oscillators such as temperature compensated and oven controlled devices [25], [31]. Assuming this type of oscillators, the maximum error in active power sharing at FL in terms of these tolerances can be written for the worst case as 𝑒𝑃𝑖,𝐹𝐿 𝑚𝑎𝑥 =𝜔0(1+𝛼𝑆(𝑘𝑆−1)𝑃𝑖𝑚𝑎𝑥)2(𝑛−1)𝑑𝑚𝑎𝑥 𝑛 𝑚𝑖. (26) This expression is obtained by considering the worst case in which all clock drift rates 𝑑𝑖 and 𝑑𝑗 in (25) take the value 𝑑𝑚𝑎𝑥 or −𝑑𝑚𝑎𝑥. It is worth mentioning that the probability that these upper limit values are given at the same time for all processors in a practical scenario is extremely low. Fig. 15. Experimental active powers and frequency errors for abrupt load changes using the standard control. Fig. 16. Experimental active powers and frequency errors for abrupt load changes using the proposed control. 0 250 500 750 1000 Active Power (W) P1P2P3 010 20 30 40 50 60 -11.2 -8.4 -5.6 -2.8 0 error in freq (mHz) Time (s) f1-f0f2-f0f3-f0 0 250 500 750 1000 Active Power (W) P1P2P3 010 20 30 40 50 60 -11.2 -8.4 -5.6 -2.8 0 error in freq (mHz) Time (s) f1-f0f2-f0f3-f0 Fig. 14. Experimental active powers and frequency errors for soft load changes using the proposed control. 0 250 500 750 1000 Active Power (W) P1P2P3 010 20 30 40 50 60 -10 -7.5 -5 -2.5 0 error in freq (mHz) Time (s) f1-f0f2-f0f3-f0 This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TIE.2018.2844846 Copyright (c) 2018 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].