A tunable Butterworth low-pass filter with digitally controlled DDCC

RADIOENGINEERING, VOL. 22, NO. 2, JUNE 2013 511 A Tunable Butterworth Low-Pass Filter with Digitally Controlled DDCC Yuh-Shyan HWANG 1, An LIU 1, San-Fu WANG 2, Ssu-Che YANG 1, Jiann-Jong CHEN 1 1 Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan 2 Department of Electronic Engineering, Ming Chi University of Technology, Taipei 243, Taiwan [email protected], [email protected], [email protected], hen[email protected], [email protected] Abstract. This paper presents a 6th-order tunable Butterworth low-pass active filter with Digitally Controlled Differential Difference Current Conveyor (DDCC). This active filter is synthesized using the systematic method of voltage-mode linear transformation (VMLT) which enables the filter to use fewer active components, grounded capacitors and grounded resistors to avoid the parasitical effects. The bandwidth of the filter can be tuned by digital switches to adjust the output current of the DDCC. The specifications of the filter are based on 3G standard, and the filter is controlled by 8-bit digital signals. The tunable bandwidth of the filter is from 12 kHz to 2.6 MHz. The filter chip layout is realized by TSMC 0.18 μm CMOS 1P6M mixed-mode technology. The supply voltage is 1.8 V and the power consumption is 3.6 mW. Keywords Differential difference current conveyor (DDCC), voltage-mode linear transformation (VMLT), current division network (CDN), active filter. 1. Introduction In recent years, CMOS circuits have become the main building blocks of VLSI circuits. In analog IC design, active filters have been used for communication and RF front-end processing such as channel selection filter [1], [2]. There are many methods to synthesize high-order active filters [3], [4], [5]: Follow-the-leader feedback, cascade synthesis, Bruton's transformation, active inductor approach, Leapfrog, Linear transformation, etc. Because the linear transformation method may be applied to prevent monolithic integrated filters from the effect of unpredictable variations of process parameters, it is applied in this study not only to simplify the design and to reduce the number of components but also to use grounded capacitors and resistors to avoid parasitical effects. The result is a simple but effective design of a high-order active filter. Section II discusses the basic theory of Voltage-Mode Linear Transformation (VMLT), and digitally controlled differential difference current conveyor (DDCC). The design of an active filter and the implementation of the proposed filter are given in Section III. The simulation results are shown in Section IV, and the conclusions are given in Section V. 2. The VMLT and the Digitally Controlled DDCC This section explains the concepts of the VMLT and the digitally controlled DDCC. 2.1 The VMLT A conventional cascaded two-port network is shown in Fig. 1. N1 N2 I11 I21 I12 V11 V21 V12 I22 V22 Nn I1n V1n I2n V2n Fig.1. A conventional two-port network. The variables of input and output are in the forms of voltage and current. The equation is shown in (1). » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª 2i 2i ii ii 2i 2i i 1i 1i I V DC BA I V T I V (1) where Ti is the transfer matrix. The variables can be changed into voltage variables (x1i, x2i, y1i, y2i) through the VMLT method by the transfer matrices S1i and S2i as shown in (2) and (3). » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª 1i 1i 1i1i 1i1i 1i 1i 1i 1i 1i I V I V S y x GJ ED , (2) » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª 2i 2i 2i2i 2i2i 2i 2i 2i 2i 2i I V I V S y x GJ ED . (3) xji and yji are voltage variables, αji and γji are dimensionless, and the unit of βji and δji is mho; j = 1, 2 and i = 1 ... n, where n is the order of the two-port network. 512 Y. HWANG, A. LIU, S. WANG, S. YANG, J. CHEN, A TUNABLE BUTTERWORTH LOW-PASS FILTER WITH … (4) can be derived from (1)~(3): » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª ' » ¼ º « ¬ ª » ¼ º « ¬ ª 2i 2i 2i2i 2i2i ii ii 1i1i 1i1i i 2i 2i 12ii1i 1i 1i y x - - DC BA 1 y x STS y x DJ EG GJ ED » ¼ º « ¬ ª » ¼ º « ¬ ª 2i 2i ii ii y x dc ba . (4) The yji’s can be represented by the xji’s. If the xji’s represent the inputs and the yji’s represent the outputs, a new cascaded two-port ladder prototype network can be developed. Equations (5) and (6) are introduced to simply the interconnection between the two-ports: 2112 S 01 10 1-0 01 S» ¼ º « ¬ ª » ¼ º « ¬ ª , (5) » ¼ º « ¬ ª » ¼ º « ¬ ª » ¼ º « ¬ ª 21 21 12 12 y x 01 10 y x . (6) These equations can be called the cross-cascaded interconnection which means that the connection is crosscascaded between every two of the new two-port networks as shown in Fig. 2. N1 N2 y 11 Nn y 21 y 12 y 22 y 1n y 2n x 12 x 22 x 1n x 2n x 11 x 21 Fig. 2. The cross-cascaded two-port network after VMLT. 2.2 The Digitally Controlled DDCC The symbol of the DDCC [6], [7], [8] is shown in Fig. 3. The DDCC is an active component that has four ports marked Y1, Y2, X and Z. The DDCC is an active component which is basically a second generation current conveyor combined with a differential difference amplifier. The small signal model of DDCC is shown in Fig. 4. There are two types of DDCC. The relationships among the variables are IY1 = IY2 = 0, VX = VY1 - VY2 and IZ = IX for the positive type of DDCC as expressed by (7), or IY1 = IY2 = 0, VX = VY1 - VY2 and IZ = -IX for the negative type of DDCC, » » » » ¼ º « « « « ¬ ª » » » » ¼ º « « « « ¬ ª  » » » » ¼ º « « « « ¬ ª Z X Y Y Z X Y Y I I V V I V I I 2 1 2 1 0100 0011 0000 0000 (7) We use the DDCC configuration proposed in [9] and add four current-shunt transistors M1A, M2A, M3A and M4A at the input stage, as shown in Fig. 5. Such arrangement can improve the input common mode range as well as enhance the linearity of the DDCC. The component parameters of the proposed DDCC are listed in Tab. 1. V Y1 V Y2 Y1 Y2 Z DDCC V X X I X I Z Fig. 3. Symbol of DDCC. DDCC Z Y 1 X V Y1 V X V X =V Y1 -V Y2 I Z =I X I Z I X Y 2 V Y2 Fig. 4. Ideal model of DDCC. VDD Y1X Cc Y2 Vb1 M1 VSS Rc M2 M3 M4 M1A M2A M3A M4A M5A M5B M5C M5D M6 M7 M8 M9 Vout Fig. 5. The schematic of the DDCC. Transistors (DDCC) Sizes (W/L), μm M5A, M5B, M5C, M5D 20/0.5 M1, M2, M3, M4 48/0.5 M1A, M2A, M3A, M4A 12/0.5 M6, M7 6/0.5 M8, M9 6.2/0.5, 30.4/0.5 Resistor and Capacitor Value Resistor (RC) 2 kΩ Capacitor (CC) 0.25 pF Tab. 1. The component parameters of the proposed DDCC. Current division networks (CDNs) [10]-[14] are added in order to widen the range of the output current IZ of the proposed DDCC. The CDNs can modify the current relationship from IZ = IX to IZ = αIX for the positive type of DDCC and IZ = -αIX for the negative type of DDCC, where the digital control factor α is the digital value corresponding to the CDN binary switches with 0 < α ʀ 1. Thus a positive type digitally controlled DDCC can be represented by (8), RADIOENGINEERING, VOL. 22, NO. 2, JUNE 2013 513 » » » » ¼ º « « « « ¬ ª » » » » ¼ º « « « « ¬ ª  » » » » ¼ º « « « « ¬ ª Z X Y Y Z X Y Y I I V V I V I I 2 1 2 1 000 0011 0000 0000 D . (8) The block diagram of a 4-bit digitally controlled CDN is shown in Fig. 6 which consists of 4 current division cells (CDCs). According to the current division principle, each CDC has one input current Iin and three output currents Io1, Io2 and Io3. Their relationships are expressed as follows: 2 _ _1 iin iio I dI , (9) 2 _ _2 iin iio I dI , (10) 2 _ _3 iin io I I (11) where di is the digital control bit of the ith CDC. As also shown in Fig. 6, the two output currents Io1 and Io2 of the 4bit CDN are given by ¦¦   3 0 3_ 3 0 4 _10_31 )21( 2 1 i i in i i i i iooo IdIII , (12) ¦¦ 3 0 3_ 3 0 4 _22 )2( 2 1 i i in i i i i ioo IdII (13) and )21( 2 1 3 0 4 3_ 1 ¦  i i i i in o d I I D . (14) Hence the current gain of the 4-bit CDN is controlled digitally. CDC3 d3d2d1d0 Iin_3 Io1_3 Io2_3 Io1_2 Io1_1 Io1_0 Io2_2 Io2_1 Io2_0 Io2 Io1 CDC2CDC1CDC0 I o3_0 (I o3_3 )(I o3_2 )(I o3_1 ) (I in_2 =2I o3_2 ) d3(Iin_3/2) d3(Iin_3/2) Iin_2 Iin_1 Iin_0 (=16Io3_0)(I in_3 =2I o3_3 )(I in_1 =2I o3_1 )(I in_0 =2I o3_0 ) Fig. 6. The block diagram of a 4-bit digitally controlled CDN. In this study, an 8-bit digitally controlled CDN is divided into two such 4-bit CDNs, each capable of mirroring and shunting the currents in the ratios 16:8:4:1, which are determined by the W/L sizes of the MOS transistors. The schematic of the 8-bit digitally controlled CDN is shown in Fig. 7. The currents from the previous stage are mirrored by M13 and M18 which are controlled by the most significant (MSB) 4 bits and the least significant (LSB) 4 bits, respectively. As explained above, the currents are divided in the ratio 16:1 determined by the W/L sizes of M13 and M18, and each of M13 and M18 are connected to 8 MOS transistors with appropriate W/L sizes to shunt the current in the ratios 16:8:4:1. The two currents flow through M22 and M16 respectively and finally merge as the digitally controlled output current IZ. The operations of the NMOS network are complementary to those of the PMOS network, and the two currents flow through M25 and M26 to merge as IZ. The component parameters of the CDN are listed in Tab. 2. Transistors (CDN) Sizes (W/L)μm M13a(b), M13c(d), M13e(f), M13g(h) 32/0.5, 16/0.5, 8/0.5, 4/0.5 M19a(b), M19c(d), M19e(f), M19g(h) 20.8/2, 10.4/2, 5.2/2, 2.6/2 M28a(b), M28c(d), M28e(f), M28g(h) 10.4/0.5, 5.2/0.5, 2.6/0.5, 1.3/0.5 M34a(b), M34c(d), M34e(f), M34g(h) 3.2/2.4, 1.6/2.4, 0.8/2.4, 0.4/2.4 Tab. 2. The component parameters of the CDN. Finally, the DDCC and the CDN are combined to form a digitally controlled 8-bit DDCC. The symbol of the digitally controlled 8-bit DDCC is shown in Fig. 8, and the full schematic is shown in Fig.9. In next section, we will describe how VMLT is applied to the design of a high order filter by the digitally controlled DDCC circuit. 3. The Design of an Active Filter To demonstrate the effectiveness and the flexibility of the proposed design, a 6th-order tunable Butterworth lowpass active filter using digitally controlled DDCCs is presented. The application of linear transformation and the realization of the filter using digitally controlled DDCCs are illustrated in this section. The passive part of the filter is divided into three different portions: input portion, output portion, and middle portion. The middle portion is further divided into L series with αji = δji = 0 and C shunt with βji = γji = 0 to reduce the complexities of transformation matrices. Furthermore, we can choose either αji or γji = ±1, and either βji or δji = ±R to reduce the number of the digitally controlled DDCCs. Take the 6th-order Butterworth low-pass ladder filter shown in Fig. 10 for example. The transformation matrix of its input portion (the R-C shunt arm connected to the voltage source) can be expressed as » ¼ º « ¬ ª r r » ¼ º « ¬ ª 01 R0 2121 2121 GJ ED . (15) Its output variables x21 and y21 can be expressed as 1sRC Ex y 1 21 21  r r . (16) The transfer functions can be derived for the digitally controlled DDCC circuits (DCDDCC-based circuits) and are also shown in Tab. 3 by D D aa 21 aa 21 21 CR s1 Ex CsR1 Ex y  r #  r r . (17) 514 Y. HWANG, A. LIU, S. WANG, S. YANG, J. CHEN, A TUNABLE BUTTERWORTH LOW-PASS FILTER WITH … VDD VSS M13 M13a M13b M13c M13h M14c M14a M14b M15 V3a1+ V2a1V2a1+ V0a1Vp1 Vp2 V1a1V0a1+ V2a1+ V3a1M13d M13e M13f M13g V3a0+ V2a0V2a0+ Vp1 Vp2 V1a0V0a0+ V2a0+ V3a03a 3b 3c 3d 3e 3f 3g 3h Vp2 Vp2 VDD VSS Z M25 M26 M27 M28a M28b M28c M28h M29a M29b M30 V3a1+ V2a1V1a1+ V0a1Vn1 Vn2 V1a1V0a1+ V2a1+ V3a1M28d M28e M28f M28g M29c Vn2 28a 28b 28c 28d 28e 28f 28g V3a0+ V2a0V2a0+ V0a0Vn1 Vn2 V1a0V0a0+ V2a0+ V3a0Vn2 M18 V0a019a 19b 19c 19d 19e 19f 19g 19h M19a M19b M19c M19d M19e M19f M19g M19h M20a M20b M20c M21 28h M33 M34a M34b M34c M34d M34e M34f M34g M34h 34a 34b 34c 34d 34e 34f 34g 34h M35a M35b M35c M36 M14c1 M14c2 M29c1 M29c2 V3a1 M22 M16 Fig. 7. The schematic of the 8-bit digitally controlled CDN. Digitally controlled DDCC Y 1 X Z DDCC± I X ±I Z V Y1 V X Y 2 V Y2 CDN ±αI X Fig. 8. The symbol of the digitally controlled 8-bit DDCC. VDD VSS M13 M13a M13b M13c M13h M14c M14a M14b M15 V3a1+ V2a1V2a1+ V0a1Vp1 Vp2 V1a1V0a1+ V2a1+ V3a1M13d M13e M13f M13g V3a0+ V2a0V2a0+ Vp1 Vp2 V1a0V0a0+ V2a0+ V3a03a 3b 3c 3d 3e 3f 3g 3h Vp2 Vp2 VDD VSS Z M25 M26 M27 M28a M28b M28c M28h M29a M29b M30 V3a1+ V2a1V1a1+ V0a1Vn1 Vn2 V1a1V0a1+ V2a1+ V3a1M28d M28e M28f M28g M29c Vn2 28a 28b 28c 28d 28e 28f 28g V3a0+ V2a0V2a0+ V0a0Vn1 Vn2 V1a0V0a0+ V2a0+ V3a0Vn2 M18 V0a019a 19b 19c 19d 19e 19f 19g 19h M19a M19b M19c M19d M19e M19f M19g M19h M20a M20b M20c M21 28h M33 M34a M34b M34c M34d M34e M34f M34g M34h 34a 34b 34c 34d 34e 34f 34g 34h M35a M35b M35c M36 M14c1 M14c2 M29c1 M29c2 V3a1 M22 M16 VDD Y1X Cc Y2 Vb1 M1 VSS Rc M2 M3 M4 M1A M2A M3A M4A M5A M5B M5C M5D M6 M7 M8 M9 Vout Fig. 9. The full schematic of the digitally controlled 8-bit DDCC. RADIOENGINEERING, VOL. 22, NO. 2, JUNE 2013 515 The transformation matrix of the L series arm of the middle portion is » ¼ º « ¬ ª 1212 1212 GJ ED » ¼ º « ¬ ª 2222 2222 GJ ED = » ¼ º « ¬ ª r r R0 01 » ¼ º « ¬ ª r r R0 01 . (18) It can be shown that R L s xx yy 2 i1i2 i2i1 r r r # (19) Its corresponding digitally controlled DDCC lossless integrator circuit can also be listed in Tab. 3 with its transfer function D D aa i1i2 aa i1i2 i2i1 CsR xx ) sC 1 R xx (yy r  r r r ## . (20) The transformation matrix of the C shunt arm of the middle portion is » ¼ º « ¬ ª 1212 1212 GJ ED » ¼ º « ¬ ª 2222 2222 GJ ED = » ¼ º « ¬ ª r r 01 0R » ¼ º « ¬ ª r r 01 0R . (21) It can be shown that 3 i1i2 i2i1 sRC xx yy r r r # . (22) Its corresponding digitally controlled DDCC lossless integrator circuit can also be listed in Tab. 3 with its transfer function D D aa i1i2 aa i1i2 i2i1 CsR xx ) sC 1 R xx (yy r  r r r ## . (23) The transformation matrix of the output portion (the R-L series arm) can be expressed as » ¼ º « ¬ ª 1212 1212 GJ ED = » ¼ º « ¬ ª r r 01 0R . (24) It can be shown that O 6 61 61 V 1 R L s x y  r r . (25) Its corresponding digitally controlled DDCC lossless integrator circuit can be presented in Tab. 3 with its transfer function O aa 16 aa a a 16 61 V RC s1 x ) 1RsC R R x (y  r #  r r D D . (26) In summary, we can divide the filter prototype into six sections and choose appropriate transformation matrices to obtain their x-y domain transfer functions. EC 1 R s L 2 C 3 V o R L C 5 L 4 L 6 Fig. 10. The 6th-order Butterworth low-pass ladder filter. E R C L C L R » ¼ º « ¬ ª r r 01 R0 1sRC Ex y 21 21  r r » ¼ º « ¬ ª r r R0 01 » ¼ º « ¬ ª r r R0 01 R L s xx yy i1i2 i2i1 r r r # » ¼ º « ¬ ª r r 01 R0 » ¼ º « ¬ ª r r 01 R0 sRC xx yy i1i2 i2i1 r r r # » ¼ º « ¬ ª r r R0 01 O 61 61 V 1 R L s x y  r r D a a CR C R  D aa CR R L D a a CR C R  D aa CR R L Y 1 Y 2 X DCDDCC Z R a R a C a E 21 x# 21 yr Y 1 Y 2 X DCDDCC Z R a C a i2 x# i1 x# i2i1 yy r r Y 1 Y 2 X DCDDCC Z R a C a i2 x# i2i1 yy r r i1 x# Y 1 Y 2 X DCDDCC Z R a R a C a 61 xr O61 Vy r Passive filter section circuit Transformation matrix & transfer function Digitally controlled DDCC-based circuit & design equation Tab. 3. The transformation blocks. X Y 1 Z Y1= Ra1 Ra2 Ca1 Y 2 DCDDCCr Y2 r } z X Y 1 Z Y1= Rb1 Ca2 Y 2 r Y2 r X Y 1 Z Y1= Rc1 Ca3 Y 2 r Y2 r X Y 1 Z Y1= Rd1 Ca4 Y 2 r Y2 r X Y 1 Z Y1= Re1 Ca5 Y 2 r Y2 r X Y 1 Z Y1=Vo Rf1 Ca6 Y 2 r Rf2 X2 # X2 # X2 # X2 # X2 # X1 r X1 r X1 r X1 r X1 r DCDDCCDCDDCCDCDDCCDCDDCCDCDDCCFig. 11. A digitally controlled DDCC-based 6th-order tunable Butterworth low-pass active filter. Then, we can cross-cascade their corresponding digitally controlled DDCC circuits to construct the filter. A 6th-order tunable Butterworth low-pass active filter using digitally controlled DDCCs, grounded resistors and grounded capacitors is presented as an example in this study. In this filter, VDD = 1.8 V, Ra1 =Rf1 ɼ5.3 kΩ, Ra2 = Rf2 = 5.3 k:/α, Rb1 = Re1 ɼ7.3 k:, Rc1 = Rd1 ɼ9.9 k:, Ca1 = Ca6 = 6pF, and Ca2 = Ca3 = Ca4 = Ca5 = 12 pF [15], [16]. Its configuration with six digitally controlled DDCCs is shown in Fig. 11. 516 Y. HWANG, A. LIU, S. WANG, S. YANG, J. CHEN, A TUNABLE BUTTERWORTH LOW-PASS FILTER WITH … CDN 8-bit SW (α) Bandwidth Output voltage (VP-P) THD (%) 11111111 (1) 2.6 MHz 206 mV 1.09 01111111 (0.5) 1.25 MHz 218 mV 0.74 00111111 (0.25) 680 k Hz 236 mV 0.69 00011111 (0.125) 363 k Hz 261 mV 1.58 00001111 (0.0625) 187 k Hz 225 mV 1.57 00000111 (0.03125) 93.2 k Hz 235 mV 1.51 00000011 (0.015625) 48.4 k Hz 265 mV 0.99 00000001 (0.0078125) 25.4 k Hz 302 mV 5.35 00000000 (0.00390625) 12 k Hz 326 mV 8.80 Tab. 4. The simulation results at an input voltage of 600!mV(VP-P). Filter type Butterworth active low-pass filter Order 6 Frequency Range 12 kHz ~ 2.6 MHz Ripple 0 dB THD 1.09 % @ 2.6 MHz Voltage Supply 1.8 V Power Consumption 3.6 mW Chip Size 0.482×0.435 mm2 (without PAD) Technology TSMC 0.18μm 1P6M mixed-mode process Tab. 5. The specifications of the proposed filter. 4. Simulation Results The proposed filter is tuned by a 8-bit CDN switch (the digital control factor α). Nine simulations with different values of α are conducted at an input voltage of 600 mV (peak-to-peak), and the range of the tuned frequencies is from 12 kHz to 2.6 MHz. The simulation results are shown in Tab. 4 and the frequency responses are shown in Fig. 12. The filter is implemented in TSMC 0.18 Pm 1P6M process with supply voltage VDD = 1.8 V. The chip layout is shown in Fig. 13, and the specifications of the filter are shown in Tab. 5. The chip area without PAD is 0.482 × 0.435 mm2. 5. Conclusions The design of a tunable differential difference current conveyor (DDCC) active filter using voltage-mode linear transformation (VMLT) method is presented. The bandwidth of such a filter can be tuned by the α factor (the digital value corresponding to the CDN binary switches) to adjust the output current value of the DDCC. A 6th-order tunable Butterworth low-pass active filter with digitally 1 2 KHz~2.62MHz -6.02dB 1111 1111 0000 0000 Fig. 12. The simulation frequency responses. Fig. 13. The chip layout of the proposed filter. controlled DDCC is fabricated using 6 digitally controlled DDCCs along with 6 grounded capacitors and 8 grounded resistors. Its CDN circuits allows the bandwidth of the filter to be tuned by adjusting the α factor. The proposed filter has the following merits: easy and systematic design procedures are available, all capacitors and resistors are grounded, and the equations are simple. Furthermore, the design and circuits can be extended and applied to other applications. Acknowledgements The authors would like to thank National Science Council (NSC) and Chip Implementation Center (CIC) of Taiwan for the financial and technical support. References [1] ALZAHER, H. A., ELWAN, H. O., ISMAIL, M. A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers. IEEE Transactions on Solid-State Circuits, 2002, vol. 37, no. 1, p. 27 - 37. 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V. Design of Analog Filters. 2nd ed. New York (USA): Oxford University Press, 2009. [16] CHANG, C. M., LEE, C. N., HOU, C. L., HORNG, J. W., TU, C. K. High-order DDCC-based general mixed-mode universal filter. IEE Proceedings Circuits, Devices and Systems, 2006, vol. 153, no. 5, p. 511 - 516. About Authors ... Yuh-Shyan HWANG was born in Taipei, Taiwan, in 1966. He received the Ph.D. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, in 1996. During 1991–1996 and 1996–2003, he was a Lecturer with the Department of Electrical Engineering, Lee-Ming Institute of Technology, New Taipei City, Taiwan and an Associate Professor with the Department of Electrical Engineering, Hwa Hsia Institute of Technology, New Taipei City, Taiwan, respectively. In 2003, he joined the Department of Electronic Engineering and the Graduate Institute of Computer and Communication Engineering, National Taipei University of Technology, Taipei, where he is currently a Full Professor and the Chairman of the Department of Electronic Engineering. He joined the Editorial Board of Active and Passive Electronic Components in 2010. His current research interests include analog integrated circuits, mixedsignal integrated circuits, power electronic integrated circuits, and current-mode analog signal processing. An LIU was born in Taipei, Taiwan, R.O.C. in 1970. He received his M.S. degree in electronic engineering from National Taiwan University of Science and Technology (NTUST), Taipei, Taiwan, R.O.C. in 1996. He is currently working toward his Ph.D. degree in the Department of Electronic Engineering and Institute of Computer and Communication of National Taipei University of Technology, Taiwan, R.O.C. He has been with St. John’s University, New Taipei City, Taiwan since 1997, where he is currently an instructor in the Department of Computer Science and Information Engineering. San-Fu WANG was born in Changhua, Taiwan, in 1976. He received the M.S. and Ph.D. degrees from the Department of Electronic Engineering, Institute of Computer and Communication, National Taipei University of Technology, Taiwan, in 2003 and 2010, respectively. He is now an assistant professor in the Department of Electronic Engineering, Ming Chi University of Technology, Taiwan. His research interests include network communication systems and analog integrated circuits. Ssu-Che YANG received the M.S. degree from the Department of Electronic Engineering, Institute of Computer and Communication, National Taipei University of Technology, Taiwan, in 2008. His research interests include analog integrated circuits and signal processing. Jiann-Jong CHEN was born in Keelong, Taiwan, in 1966. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, R.O.C., in 1992 and 1995, respectively. From 1994 to 2004, he was on the faculty of Lunghwa University of Science and Technology, Taiwan. Since August 2004, he has been with the Department of Electronic Engineering, National Taipei University of Technology, where he is now a Professor. His research interests are in the area of mixedsignal integrated circuits and systems for power management.