InGaAs Capacitor-Less DRAM Cells TCAD Demonstration

Received 3 May 2018; revised 28 June 2018 and 19 July 2018; accepted 21 July 2018. Date of publication 24 July 2018; date of current version 14 August 2018. The review of this paper was arranged by Editor P. Pavan. Digital Object Identifier 10.1109/JEDS.2018.2859233 InGaAs Capacitor-Less DRAM Cells TCAD Demonstration CARLOS NAVARRO 1, SANTIAGO NAVARRO 1, CARLOS MARQUEZ 1, LUCA DONETTI1, CARLOS SAMPEDRO 1,SIEGFRIEDKARG 2,H.RIEL 2, AND FRANCISCO GAMIZ 1 1 Computer Electronics and Technology Department, University of Granada, 18071 Granada, Spain 2 Science and Technology Department, IBM Research – Zurich, 8803 Rüschlikon, Switzerland CORRESPONDING AUTHOR: CARLOS NAVARRO (e-mail: [email protected]) This work was supported by H2020 REMINDER European under Grant 687931, and in part by the Spanish National Projects under Grant TEC2014-59730 and Grant PCIN-2015-146. ABSTRACT 2D numerical TCAD simulations are used to infer the behavior of III-V capacitor-less dynamic RAM (DRAM) cells. In particular, indium gallium arsenide on insulator technology is selected to verify the viability of III-V meta-stable-dip RAM cells. The cell performance dependence on several parameters (such as the back-gate voltage, semiconductor thickness, indium/gallium mole fraction or interface traps) and simulation models (like ballisticity or spatial quantum confinement) is analyzed and commented. Functional cells are presented and compared with analogous silicon 1T-DRAM memories to highlight the advantages and drawbacks. INDEX TERMS 1T-DRAM, III-V, capacitor-less, DRAM, fully depleted, InGaAs, MSDRAM, SOI. I. INTRODUCTION Nowadays, the Dynamic RAM (DRAM) industry is approaching fundamental limitations since the DRAM capacitor scaling is becoming extremely complex in 2D architectures. The migration from 6F2to 4F2cells is very challenging and new DRAM concepts or 3D cell stacking are currently being explored [1]. Basic dynamic cell requirements include at least low-cost, low-power and fast operation. Several SOI (Silicon-On-Insulator) capacitor-less cells, getting rid of the capacitor integration, have been proposed in the present and last decades [2]–[4], each of them featuring its own advantages. Among this breed of memory cells, the MSDRAM (Meta-Stable-Dip RAM) [5] stands out due to its simplicity of operation and cheaper manufacturing process where only a standard silicon fully-depleted (FD) SOI transistor is required. Nonetheless, capacitor-less memory cells using III-V materials have not been thoroughly studied yet. Previous works on III-V 1T-DRAM cells have been mainly focused on simulations [6]–[8] or on co-integrating source and drain (S/D) gallium phosphide (GaP) side terminals on silicon body transistors [9] to enhance the floating body effect (FBE) [10], hence the DRAM performance. In this work, III-V n-type transistors are built using 2D TCAD simulations in Synopsys [11] and their operation as MSDRAM memory cell is demonstrated and compared with analogous silicon cells. In order to test if III-V singletransistor DRAM cells are feasible, indium gallium arsenide (InGaAs) is selected as semiconductor due to the increasing interest of implementing this material with CMOS logic [12], [13]. Concretely, InGaAs features extremely high electron mobility [14] motivating its application for ultra-fast and low-power electronics [15]. II. CAPACITOR-LESS DRAM CELLS PRINCIPLES The original concept of capacitor-less DRAM cell was first experimentally demonstrated in [16] by using the intrinsic floating body effect [10] of partially-depleted (PD) SOI devices. The charge, defining the logic ‘0’ or ‘1’-state, is stored in the body of the transistor, modulating its conductance and avoiding the need of an external capacitor. Instead of sensing the bitline voltage (increase/drop due to the discharge/charge of the storage capacitor) as in common DRAM memories, the logic state discrimination in 1T-DRAM cells is based on reading the current through the cell: charged bodies typically enhance the current flow by reducing the threshold voltage while discharged bodies do the opposite. These operation principles generally apply to most capacitor-less cells [2], [3] with few exceptions [17]–[19]. 2168-6734 c 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. 884 See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. VOLUME 6, 2018 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION TAB LE 1. Default MSDRAM biasing conditions for each memory operation. Normally VBG >0.0VandVS=0.0V. Regarding the MSDRAM [5], the memory operation is based on inter-gate coupling [20] and non-equilibrium state [21]. The back-gate terminal, acting as ground-plane (GP), is constantly biased to positive values, typically over threshold, VBG >0V, to obtain a virtual n-type back channel. Likewise, the front-gate voltage is generally (but not always) negative, VFG <0V, to induce a potential well below the top-gate oxide. This mechanism mimics the inherent FBE of PD-SOI devices in fully depleted cells: subsisting holes within the body are collected and modify the cell inner electrostatics. By modulating the hole density, distinct vertical electric fields are achieved originating a change in the back electron-channel regime via coupling. Different conductance values are thus obtained defining the logic ‘1’- and ‘0’-states. The ‘1’-state programming, W1, is carried out by injecting holes typically through impact ionization or, more likely to prevent reliability issues [22], by band-to-band tunneling at the drain edge (VFG <0V and VDS >0V). On the other hand, the logic ‘0’-state is stored, W0, evacuating holes via top-gate capacitive coupling (VFG ≥0V with VD≤0V and VS=0V). The cell reading, R, is achieved by simply sensing the drain current (VDS >0V): high (low) current values imply a large (low) hole population corresponding to the ‘1’ (‘0’) state. Finally, on holding, H, the cell current is blocked while available holes are preserved underneath the topgate(VFG <0V and VDS =0V) for as long as possible in order to enhance the retention time. The non-steady ‘0’- state is gradually lost due to thermal generation and carrier leakage: mainly tunneling (either direct gate or band-to-band tunneling) and junction leakage. Typical biasing conditions are summarized in Table 1. III. SIMULATION FRAMEWORK A 2D n-type FD-SOI transistor built in Synopsys tool [11] is used as basic MSDRAM memory cell structure. A homogeneously beryllium low p-type doped InGaAs film is employed as active layer. The semiconductor lies on-top of a silicon dioxide buried sheet with a p-type ground plane as back-gate terminal underneath. The simplified gate stack, horizontally isolated with wide Si3N4lateral spacers, is made of a thick high-k dielectric with a metal featuring close to mid-gap metal work-function above. The high-k layer thickness guarantees negligible gate tunneling while providing good electrostatics. The lateral regions are raised and implanted with n-type silicon (where the concentration is limited as in [23]) to induce the S/D side terminals. The resultant structure and its corresponding net doping profile are illustrated in Fig. 1. A very FIGURE 1. a) Default InGaAs-OI MSDRAM cell with its b) net doping profile. LG=100 nm and tS=30 nm. Other parameters match those found in Table 2. The ground plane is simulated as a metal contact directly below the BOX with a workfunction matching p-type 1018 cm−3doped silicon as if it were a ground-plane. TAB LE 2. Memory cell physical parameters. similar silicon cell is used for the aim of comparison. The main difference resides in the doping profile and its species, using boron (p-type) and arsenic (n-type). The essential physical parameters are summarized in Table 2 for both cells. The employed default semiconductor mole fraction corresponds to In0.53Ga0.47As, one of the most commonly studied compounds [12], [13], [15], [23]. Material parameters such as energy band-gap, intrinsic carrier concentration or dielectric constants agree with those found in [24]. Parameters and electrical simulation models include: room temperature (300 K), Fermi statistics, band-to-band tunneling generation and SRH (Shockley-Read-Hall), Auger and radiative recombination processes (only SRH in silicon). Regarding the mobility models, high-field saturation, doping dependence and normal field contributions are considered. The channel length-modulation model to account for ballistic mobility (with Fermi correction) [25], [26] is included when indicated. The ballistic length, Lch, was chosen to match each device gate length, LG. Density gradient quantization model [11], [27], [28] in the InGaAs film was also considered for thin films (tS≤20 nm) to account for spatial confinement. Default double-gate 10/20 nm <100>InGaAs parameter sets were employed. VOLUME 6, 2018 885 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION FIGURE 2. a) Reverse anode voltage sweeps as a function of the back-gate bias for the InGaAs cell. b) Detail of the hysteresis cycle (reverse and forward senses) and comparison with the DC curve for VBG =2V. Corresponding vertical electron c) back and d) front densities. Front e) hole population and f) surface potential. All densities and potentials are extracted at mid channel and 0.1 nm away from the interfaces. Transient sweeps last 1 μs for each sense. LG=100 nm and tS=30 nm. VDS =1V. IV. III-V MSDRAM CELL A. HYSTERESIS MEMORY CYCLE Figure 2a depicts the reverse ID(VFG)sweeps for several back-gate voltages to observe the transistor switching characteristics. The typical threshold voltage coupling dependence according to VBG is found: increasing the back-gate voltage shifts the current onset to lower VFG [20]. A hysteresis cycle, as in [5], is observed at negative VFG enabling the memory operation, Fig. 2b. Notice, by comparing with the DC ID(VFG)sweep, that the hysteresis cycle arises as a consequence of the cell being out of its steady-state. This hysteresis can be explained as follows: at high front-gate voltages, points A and B, the strong electron volume inversion [29] (Fig. 2c and d) impedes the presence of many holes in the body (Fig. 2e). As VFG is reduced towards negative values, the front-channel electron population is reduced and the channel leaves inversion limiting the drain current, point C. Up to this point the cell is in steady-state since the DC and transient curves coincided. From this point, the cell enters in non-equilibrium regime [21] when further reducing VFG. The DC front hole accumulation layer (Fig. 2e) cannot be instantly achieved due to three reasons: i) there is no available reservoir (p+region nearby) to supply holes; ii) the p−body is depleted from free carriers and iii) its volume is limited to rapidly obtain the carriers via thermal generation. This means the required holes to recover the steady-state need to be injected by band-to-band (BtB) tunneling at the drain edge. The reduced hole population in non-equilibrium results in a body potential decrease with respect to DC, Fig. 2f. This electrostatic potential drop gradually cuts, via inter-gate coupling [20], the back-channel inversion reducing even more the current, point D. At a given VFG,the top-gate induced vertical field, not sufficiently screened by the front-hole accumulation channel, completely depletes the back interface from electrons as well, point E, and then the current reaches its minimum. As time passes and VFG goes more negative, holes are gradually introduced in the body (both via thermal generation and band-to-band tunneling) and the front-channel hole density increases toward its equilibrium concentration, point F. Once the hole population is recovered, the body potential increases allowing once again the back channel inversion, i.e. the first current onset before point G. A further increase of the top-gate voltage allows the recovery of a high electron concentration also at the front interface, point H, which finally results in the second current onset corresponding to the front interface inversion, point C. In summary, the lack of holes at the front-interface yields a potential drop that, through coupling, limits the back-channel inversion and the current flow. Once the hole density increases, the back-channel electron population rises and the current is recovered. B. TRANSIENT OPERATION A generic W0-R-W1-R-W0-R memory sequence is employed to test the basic DRAM operation for the default cell in Fig. 1. The employed bias pattern is shown in Fig. 3a. The resultant drain current readout, Fig. 3b, successfully demonstrates the valid memory operation: after any W0operation, the driven current remains much lower than after W1.The ‘1’-state current can be easily enhanced by increasing the drain bias while reading (the ‘0’-state and current ratio and margin would be degraded though). Figure 3c proves the MSDRAM operation detailed in last section. It represents the InGaAs body electron and hole densities after the first W1 and last W0, respectively. After collecting holes generated by band-to-band tunneling at the front interface during W1, the electron back-channel population is reinforced enabling a larger current readout when sensing afterward. On the other hand, following a W0, the hole density is limited underneath the top dielectric. The resultant body is deeply out of equilibrium and allows a strong vertical field to deplete the back-channel from electrons. The low electron density yields a drastic drop in the conductance and thus in the drain current. 886 VOLUME 6, 2018 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION FIGURE 3. a) Transient bias pattern composed of a W0-R-W1-R-W0-R sequence and b) resultant current readout demonstrating the memory operation. c) Hole and electron densities after programming operations, W1and W0at t=1.26 μsandt=2.10 μs, respectively. Pulses feature 200 ns width and 10 ns rising/falling times. VBG =3VandVS=0V. Same structure as Fig. 1. In the following subsections, the cell is analyzed as a function of different parameters. B.1. BACK-GATE VOLTAGE AND GATE LENGTH These two metrics are closely related to each other. The optimum back-gate voltage to enhance the memory performance, i.e., current ratio between logic levels, strongly depends on the length due to the short-channel effects (SCE). Figures 4a,b show the logic current levels and their ratio for different back-gate voltages at distinct gate lengths. Observe that the current ratio peaks at different VBG according to the length: it moves to higher VBG when increasing the S/D distance. As the gate length is downscaled, SCE gradually facilitates the back-interface inversion reducing the need of a high ground-plane bias. For example, at LG=100 nm the back-interface remains depleted up to 1.5 V when the back-channel arises. However, for LG=60 nm the channel appears even for a grounded ground plane. The current ratio comparison, accounting for all analyzed gate lengths and further demonstrating the peak shift, is illustrated in Fig. 4c. Notice that the peak displacement to larger ground plane biases for longer gate channels is gradually reduced denoting the mitigation of SCE. A similar scenario including the ballistic mobility model [26] is represented in Fig. 4d. A degradation that ranges between 5-20% is observed when including the ballistic mobility due to the limited time to accelerate electrons from the source to the drain. As a result the effective mobility drops and the current during the ‘1’- state becomes smaller (the ‘0’-state is barely affected when FIGURE 4. Logic current levels (‘1’ and ‘0’ obtained at t=1.6μsand t=2.4μs, respectively) and current ratio as a function of the back-gate voltage for a) LG=60 nm and b) LG=100 nm. Current ratios as a function of the back-gate voltage for distinct channel length ranging from 60 nm to 200 nm c) without or d) with the ballistic model included. the current is very small) which yields the reduction in the current ratio. Nevertheless, the memory operation is still possible. Although state-of-the-art buried oxides can sustain very large voltages [30], in order to prevent any reliability concern the back-gate voltage is limited to +5 V where usual operating voltages are even lower. B.2. SEMICONDUCTOR FILM THICKNESS Another important tradeoff is observed with the semiconductor channel thickness. Reducing the InGaAs film enhances the inter-gate coupling and benefits the memory effect. Figure 5 shows that the current ratio increases for thinner films. However, this mechanism cannot be sustained in ultra-thin films where the supercoupling effect takes place, as observed in other semiconductors such as silicon [31], [32]. This effect impedes the presence of an electron inversion film facing a hole accumulation layer when the semiconductor is too thin, preventing the FBE single transistor DRAM operation. For InGaAs, the critical thickness seems to be, as in silicon, around 10 nm. Due to SCE, the supercoupling phenomenon arises earlier for shorter cells [33], as can be inferred from the comparison between LG=60 nm and LG=100 nm in Fig. 5a,b where all the peaks are again displaced to lower VBG. Insets in Fig. 5a,b illustrate the current ratio when accounting for quantum mechanics corrections in the charge density distribution (exclusively for tS=10 nm and tS=20 nm). Fig. 5c,d shows the vertical charge profiles at mid-channel for electrons and holes after W0and W1. Notice that, when VOLUME 6, 2018 887 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION FIGURE 5. Current ratio as a function of the ground-plane bias for several channel thicknesses at a) LG=60 nm and b) LG=100 nm. Insets show the results for tS=10 nm and tS=20 nm when accounting for density gradient models (default parameters for InGaAs in double gate configuration for the corresponding body thickness). Vertical c) electron and d) hole density profiles at mid-channel after programming both logic states with and without quantum confinement (LG=100 nm, tS=20 nm and VBG =4.5V). spatial confinement is active, the charge profile peaks appear separated from the interface as if the semiconductor film was thinner. This effective thinning of the film induces a slight shift of the current ratio peak to higher VBG (approximately 0.5 V) as occurs without quantum mechanics. Moreover, the current ratio peaks become much larger due to several reasons: i) coupling increase between interfaces; ii) reduced surface scattering and, especially, iii) notably larger electron density after the ‘1’-state programming (the ‘0’-state remains essentially the same). All these contributions enhance the ‘1’-state current by one order of magnitude leading to the current ratio increase. Finally, it is worth mentioning that the default InGaAs quantization parameters, available exclusively for double-gate and bulk device configurations with 10 or 20 nm film thickness, might not be convenient in this structure (neither bulk or symmetric double gate) yielding an overestimation of the memory performance. B.3. INTERFACE DENSITY OF STATES Interface density of states have been considered both at the top (InGaAs/front oxide) and bottom (InGaAs/BOX) semiconductor surfaces to analyze the impact on the memory operation affected by the electrostatic change. The assumed back-interface density of states is similar to that found for Al2O3[34]. It comprises a donor uniform distribution of 1.5×1012 cm−2/eV and a donor Gaussian distribution close to the valence band of 3×1013 cm−2/eV. At the top interface FIGURE 6. Current ratio peak (between VBG =−1VandVBG =+5V) for different a) donor and b) acceptor uniform front Dit concentrations. Dashed lines represent the current ratio peak without any Dit. Current ratio against VBG with several models activated simultaneously for c) ts=30 nm and d) ts=20 nm. The back donor Dit as in [34] is always present. an uniformly distributed density of states along the energy bandgap, with variable concentration, is considered. No trapassisted tunneling or any other generation/recombination mechanism, such as surface recombination, is enabled. Figure 6 shows the current ratio for several a) donor and b) acceptor Dit concentrations. Besides the influence on the subthreshold swing characteristics [10] (not shown), Dit does not seem to extremely degrade the memory characteristics. Depending on the traps nature, the current ratio can be even improved reflecting a beneficial effect in the electrostatic control. Acceptor distributions (negatively charged when occupied) at the front interface contribute to storing holes underneath the gate dielectric, therefore enhancing the memory effect. On the other hand, donor densities (positively charged when fully occupied) counterbalance the negative VFG degrading the FBE. It is worth noting that even for a reduced front Dit, the current ratio drops with respect to the default scenario (dashed lines in Fig. 6a,b) because of the donor back-interface density, which is constantly present and reduces the vertical back-gate-induced electric field. As a final remark, since trap distributions are stochastic, the main challenge Dit introduces, even for the best acceptor scenario, is the variability from device to device. Figures 6c,d illustrate the current ratio when accounting for several models simultaneously. Spatial quantization has not been considered for tS=30 nm since no default InGaAs parameters are available for such thickness. The current ratio strongly depends on quantum mechanics as previously 888 VOLUME 6, 2018 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION TAB LE 3. III-V cell current ratio peak summary, I1/I0[A/A]. FIGURE 7. a) Current ratio as a function of the back-gate voltage for different In1−xGaxAs gallium mole fractions. b) InGaAs energy bandgap [24] and peak current ratio (for any VBG) as a function of the gallium mole fraction. observed in Fig. 5a,b and confirmed in Table 3. This table summarizes the current ratio peak dependence on the different models considered for several cell geometries (length and semiconductor thickness). The peak ratio is extracted from the range −1≤VBG ≤5V. In all cases, the Dit presence accounts for the default back-interface state density as in [34] whereas the front-interface features an uniform donor (worst case) 5×1012 cm−2/eV distribution. Ballistic and Dit distributions slightly degrade the performance whereas density gradient strongly benefits the ratio. B.4. MOLE FRACTION IMPACT Different mole fractions are tested attending to the In1−xGaxAs relation. From InAs (x=0%) to GaAs (x=100 %), the MSDRAM operation for distinct indium/gallium ratios, following parameters in [24], is verified. The default structure mimics the one in Fig. 1a. Figure 7 shows the current ratio as a function of VBG. Notice that only few mole fractions enable the memory operation where a value close to x=40 % seems to be the optimum approach (for the considered parameters and cell architecture). The current ratio peak (for any back-gate bias) and the energy band-gap are depicted in Fig. 7b. It is worth observing that memory capabilities disappear for very low/high bandgaps. If EGis reduced, parasitic injection of holes via BtB tunneling occurs while storing the logic ‘0’. As a result, the current after any programming operation is high (as for the ‘1’-state) and the current ratio drops. Likewise, if the bandgap is too large, the BtB tunneling becomes inefficient and the current during the ‘1’-state resembles a logic ‘0’ and thus the current ratio tends to 1 as well. Other biasing conditions and/or architectures (different channel thickness, doping profiles or spacers for example) might exhibit functional memory operations. FIGURE 8. a) Reverse anode voltage sweeps as a function of the back-gate bias for the Si cell. The transient ramping (falling or rising) times are fixed to 1 μs. b) Transient current readout to test the memory operation with a W0-R-W1-R-W0-R sequence (identical bias pattern as in Fig. 3a) and c) logic levels and current ratio for several GP biases. The optimum InGaAs cell found, featuring the largest current ratio, corresponds to In0.6Ga0.4As with LG=100 nm and tS=30 nm (other lengths and thicknesses have not been tested) at VBG =2V, Fig. 7. V. SILICON MSDRAM COMPARISON For the aim of benchmarking, a similar FD-SOI silicon transistor is build in Synopsys. The corresponding architecture is totally analogous and features the parameters in Table 2 unless explicitly stated. A. SILICON MSDRAM CELL ID(VFG)switching and transient characteristics are depicted in Fig. 8 for analogous silicon cells. They replicate the same biasing conditions as for the InGaAs cell previously presented in Fig. 2 (switching curves) and 3 (transient operation). Fig. 8a shows the transient reverse drain current sweeps as a function of the front-gate voltage. A significant difference, at very low front-gate voltages, is observed with respect to Fig. 2a for InGaAs. The drain current rises earlier in silicon due to the enhanced BtB hole generation as will be discussed later. Figure 8b,c represent the Si cell memory operation (same biasing as in Fig. 3a) and the current levels and ratios as a function of VBG. Results demonstrate that the silicon MSDRAM outperforms the InGaAs cell in terms of current ratio: at same biasing, VBG =3V, the silicon cell current ratio (≃2×106A/A) exceeds the InGaAs (≃103A/A) in about 3 orders of magnitude. VOLUME 6, 2018 889 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION FIGURE 9. a) Front-interface band-to-band tunneling generation rate per second for the different MSDRAM cells during W1(at t=1.20 μs for the pattern in Fig. 3a) and corresponding b) vertical hole density at mid channel after W1(at t=1.26 μs). B. BAND-TO-BAND TUNNELING GENERATION The main MSDRAM hole injection mechanism is based on gate-induced drain leakage (GIDL). It enables holes to tunnel from the conduction band to the valence band and gather in the body thanks to the strong electric field at the drain edge (VFG <0V and VD>0V). Due to the lower InGaAs energy bandgap compared to Si, approximately 0.74 eV against 1.12 eV (room temperature), the band-to-band tunneling generation rate is expected to be more effective (at equivalent conditions). This fact could be employed to reduce the programming voltage and thus the power consumption. Figure 9a shows the band-to-band generation rate along the front-interface (0.1 nm away from the top insulator) during W1for the InGaAs and Si memory cells. It is worth noticing that, in order to be fair, a silicon cell featuring lower S/D doping, 1019 cm−3, as in the InGaAs cell has been also considered. It can be observed that the generation rate is larger in InGaAs than in silicon when the cells feature the same source/drain doping concentration. Specifically, by integrating the BtB generation throughout the whole 2D structure at t=1.2µs (middle of the W1operation pulse), it turns out that InGaAs is more than 27 times the BtB generation in silicon (at same doping, NS/D=1019 cm−3) and about 22% for the silicon default doping NS/D=1021 cm−3. This extreme difference implies that the Si cell with lower doping is not able to adequately repopulate the body with holes after W1, Fig. 9b, and the memory operation fails, Fig. 8b. As a negative point, the InGaAs BtB generation slightly occurs not only at the drain edge but along the front-interface as well and, more importantly, also during the hold operation (not shown). This means that the logic ‘0’-state retention time would be degraded faster than in silicon. Another important difference with respect to silicon is the direct bandgap (regardless the considered mole fraction): the generation of electron-hole pairs is more effective. This fact is expected to negatively impact on the cell retention time. The ‘0’-state would be compromised earlier limiting the performance. FIGURE 10. Electrostatic potential well at equilibrium (all device terminals are short-circuited) for the InGaAs and silicon cells at mid channel (y=tS/2). For a fair comparison, all devices feature the same front-gate workfunction, FG =4.95 eV. LSp =20 nm and tBOX =30 nm. FIGURE 11. a-d) Different bias patterns to test the low voltage MSDRAM memory operation in Si and InGaAs cells (pattern a corresponds to Fig. 3a). Current ratio results for e) InGaAs and f) Si cells with default S/D doping concentrations. At low voltages, InGaAs cells present larger memory performance. LG=100 nm and tS=30 nm, other parameters match those from table 2. C. FRONT-GATE INDUCED POTENTIAL WELL The front-interface horizontal electrostatic potential cut at equilibrium, with all terminals short-circuited, is depicted in Fig. 10 for similar InGaAs and Si memory cells. It can be observed that, when the S/D regions are less doped, the potential profiles are smoother due to the extended space charge region. The lower S/D doping and, especially, the larger III-V intrinsic carrier density, ni,In0.53Ga0.47As ≃ 6.3×1011 cm−3at room temperature [24], combine and yield reduced potential wells for the InGaAs cells with respect to silicon. This means the floating body effect is less intense in InGaAs cells: they are less effective storing holes which 890 VOLUME 6, 2018 NAVARRO et al.: InGaAs CAPACITOR-LESS DRAM CELLS TCAD DEMONSTRATION hardens the memory operation with respect to traditional silicon memories. This result partly motivates the lower InGaAs performance as capacitor-less DRAM. D. LOW-VOLTAGE OPERATION Several patterns, Fig. 3a (pattern a) and Fig. 11a-d (patterns b-e), were tested on both cells to study the memory performance at low front-gate and drain voltages. Results are summarized in Fig. 11e-f. Notice that the silicon cell is much more affected by the bias lowering than the InGaAs one (even with larger S/D doping concentrations). It turns out that the InGaAs cell is almost insensitive to the W1drain or anode voltage reduction by a 50% (compare patterns a with b and c) while the silicon cell is severely affected. Even when reducing all biases (including the holding gate voltage, pattern e), the InGaAs cell still operates as memory, although the performance is degraded. A reduction in the energy consumption for the InGaAs cell can be expected when matching the cells performance at low voltage operation. VI. CONCLUSION 2D TCAD results suggest the feasibility of implementing capacitor-less memories on III-V materials, particularly MSDRAM cells on In0.53Ga0.47As and close mole fraction compounds. Distinct logic states are demonstrated according to the previous biasing conditions (programmed state). Similar operation with respect to silicon cells is observed. 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Galy, “Evidence of supercoupling effect in ultrathin silicon layers using a four-gate MOSFET,” IEEE Electron Device Lett., vol. 38, no. 2, pp. 157–159, Feb. 2017, doi: 10.1109/LED.2016.2637563. [33] C. Navarro et al., “Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors,” J. Appl. Phys., vol. 118, Oct. 2015, Art. no. 184504, doi: 10.1063/1.4935453. [34] G. Brammertz et al., “On the interface state density at In0.53Ga0.47As/oxide interfaces,” Appl. Phys. Lett., vol. 95, no. 20, Nov. 2009, Art. no. 202109, doi: 10.1063/1.3267104. CARLOS NAVARRO received the Ph.D. degrees in electrical engineering from the University of Granada, Granada, Spain, in 2014, and the Institute of Microelectronics, Electromagnetism and Photonics, Grenoble, France, in 2015. He is currently a Post-Doctoral Researcher with the University of Granada. He has authored or coauthored over 60 journal articles or conference abstracts. His current research interests include SOI devices and capacitor-less memory cells. SANTIAGO NAVARRO was born in Granada, Spain, in 1984. He received the B.Sc. degree from the University of Granada in 2011 and the M.Sc. degree from the University of Seville in 2013. He is currently pursuing the Ph.D. degree in electronics engineering with the University of Granada. His research interest is on SOI devices and 1T-DRAM cells. CARLOS MARQUEZ received the M.Sc. degree in telecommunication engineering, the M.S. degree in electrical engineering, and the Ph.D. degree in electronics from the University of Granada, Granada, Spain, in 2012, 2014, and 2017, respectively. He has authored or co-authored 11 peerreviewed international journal articles, two book chapters, and 12 conference proceedings. His research interests include the electrical characterization of semiconductor devices, MOSFET front-end-of the line reliability, one-transistor dynamic-random-access-memory cells, and 2-D materials. LUCA DONETTI received the M.Sc. degree in physics from the University of Parma, Parma, Italy, in 1998 and the Ph.D. degree in physics from the Università degli Studi di Milano, Milan, Italy, in 2002. Since 2005, he has been with the Department of Electronics, Faculty of Sciences, University of Granada, Granada, Spain. His current research interests include the simulation of electron and hole transport properties in nanoscale electronic devices, including SOI and multigate devices, focussing on carrier band-structure effects including simple nonparabolicity models, k˚up Hamiltonians up to ab-initio calculations, and on quantum effects. CARLOS SAMPEDRO received the Ph.D. degree from the University of Granada, Granada, Spain, in 2006. Since 2011, he has been an Associate Professor with the Nanoelectronics Research Group, University of Granada. His current research interest includes advanced numerical simulation and modeling of ultimate scaled multigate, advanced silicon-on-insulator, and nonconventional devices. SIEGFRIED KARG received the Ph.D. degree in physics from University of Bayreuth, Germany, in 1995. He has been a Research Staff Member with IBM Research—Zurich since 2000. He was a Post- Doctoral Fellow with IBM Research—Almaden from 1995 to 1996 and an Research Assistant with the Darmstadt University of Technology from 1997 to 1999. He worked on the physics and materials science of organic and polymer devices (OLEDs, OFETs, and electrochemical cells) and memory applications (resistive oxide RAM). He has authored about 90 publications and holds over 30 patents. His current research fields are 1-D electronic properties of nanostructures, applications of III-V semiconductor devices and brain-inspired computing. H. RIEL photograph and biography not available at the time of publication. FRANCISCO GAMIZ received the B.S. degree (Hons.) in physics and the Ph.D. degree (Hons.) from the University of Granada, in 1991 and 1994, respectively. Since 2005, he has been a Full Professor of electronics and since 2008, the Head of the Nanoelectronics and Graphene Research Labs. He was a recipient of Best Student Award from the University of Granada. He has co-authored over 350 refereed papers in major journal and international conference proceedings and several book chapters. He is a co-holder of several international patents related to multibody 1T-DRAM. 892 VOLUME 6, 2018