Document [original]

GaN-HEMT Power Amplifiers and

Smart Transmitters for Ku-Band Satellite

Communication

vorgelegt von

Master of Science

Daniel Maaßen

geb. in Simmerath

von der Fakultät IV - Elektrotechnik und Informatik

der Technischen Universität Berlin

zur Erlangung des akademischen Grades

Doktor der Ingenieurwissenschaften

- Dr.-Ing. -

genehmigte Dissertation

Promotionsausschuss:

Vorsitzender: Prof. Dr.-Ing. Clemens GÜHMANN

Gutachter: Prof. Dr.-Ing. Georg BÖCK

Gutachter: Prof. Dr.-Ing. Arne JACOB

Gutachter: Prof. Dr. techn. Peter WEGER

Tag der wissenschaftlichen Aussprache: 08.03.2018

Berlin 2018

Abstract

Daniel Maaßen

GaN-HEMT Power Amplifiers and

Smart Transmitters for Ku-Band

Satellite Communication

Within this contribution the design, implementa-

tion, and experimental results of a satellite com-

munication (SatCom) power amplifier (PA), block

upconverter (BUC) as well as an evaluation within

the satellite link are described. Three Ku-band

GaN-HEMT PAs are presented.

A two stage design approach with two 250nm

bare-die devices has been chosen to achieve a

considerably high saturated gain of 15dB over

the whole extended Ku-band (13.75-14.5GHz).

The circuit is realised in a hybrid microwave in-

tegrated circuit (MIC) technology on an alumina

substrate. The PA shows a measured performance

of more than 50W output power for a continuous

wave (CW) signal with a power added efficiency

(PAE) higher than 23%. Modulated measurements

(QPSK) demonstrate an average output power of

more than 30W (70W peak) and 21% PAE, while

holding the Eutelsat linearity requirements.

The design procedures used were extended to a

second PA in a lower frequency range of 12.75-

13.25GHz achieving more than 80W output power

for pulsed RF signals with 34% PAE. This thesis

proposes a third PA design which covers both up-

link frequency bands (12.75-14.5GHz) and achieves

more than 55W output power with 20% PAE. This

achieved 14% fractional bandwidth (FBW) design

is equal to the theoretical limit of a broadband

matching at f0=13.25GHz for the chosen bare-

dies.

The developed BUC is supposed to work within a

very small aperture terminal (VSAT). Here an inte-

gration of either a developed 10W or a 50W am-

plifier within this BUC is shown that comes along

with a small size and low weight, paired with a

low amount of dissipated power. Additionally, the

BUC is equipped with a linearisation technique

that automatically improves the spectral regrowth

for common modulation schemes (QPSK, 8PSK),

as well as for future higher order modulation like

16APSK, 32APSK (DVB-S2X).

Finally, the BUC is tested with a VSAT in a satellite

link and demonstrates its function with data rates

of up to 1Mbit/s.

Zusammenfassung

Daniel Maaßen

GaN-HEMT Power Amplifiers and Smart Transmitters

for Ku-Band Satellite Communication

Diese Arbeit beschäftigt sich mit der Entwick-

lung, dem Aufbau sowie der messtechnischen

Evaluierung von Leistungsverstärkern (PA) und

einem Block Up-Converter (BUC) für die Satelliten-

kommunikation. Im Verlauf der Arbeit werden

drei verschiedene GaN-HEMT PA’s im Detail auf-

geführt.

Ein zwei-stufiges Verstärkerdesign, welches zwei

gleich große 250nm bare-dies GaN-HEMTs ver-

wendet, wurde ausgewählt, um einen akzept-

able Verstärkung von 15dB im extended Ku-band

(13.75-14.5GHz) zu erreichen. Die Schaltung

wurde als microwave integrated circuit (MIC) auf

einem Aluminiumoxid Trägerkeramik entwickelt.

Mit diesem Verstärkerkonzept wurden mehr als

50W Ausgangsleistung, mit einer power added

efficiency (PAE) von mehr als 23%, für eine contin-

uous wave (CW) Anregung erreicht. Auch mod-

ulierte Signale (z.B. QPSK) wurden verwendet,

wodurch eine Ausgangsleistung von 30W (70W

peak) und 21% PAE erreicht wurden, während

die Linearitätsbestimmungen der Eutelsat Reg-

ulierung erfüllt wurden.

Die beschriebenen Entwicklungstechniken wur-

den des Weiteren dafür verwendet, einen zweiten

Leistungsverstärker für den Frequenzbereich von

12.75-13.25GHz aufzubauen. Dieser zeigt mehr

als 80W Ausgangsleistung bei einer PAE ≥34%

für gepulste Signale. Eine dritte Entwicklung

zielte darauf ab, einen einzigen Verstärker in bei-

den Frequenzbereichen verwenden zu können

(12.75-14.5GHz). Dieser definiert mit 14% frac-

tional bandwidth (FBW) die theoretisch maximale

Bandbreite bei f0=13.25GHz und erreicht eine

Ausgangsleistung von 55W bei einer reduzierten

PAE von 20%.

Zur Verwendung der PA’s in einem very small

aperture terminal (VSAT) wurde ein BUC entwick-

elt, der durch eine geringe Größe, ein geringes

Gewicht und eine niedrige Leistungsaufnahme

besticht. Außerdem konnte eine aktive Lineari-

sierung implementiert werden, die eine signifikante

Verbesserung von Schulterabständen erreicht. Diese

Technik wurde sowohl für aktuelle Modulation-

sarten (QPSK, 8PSK) als auch für künftige mit

höherer Ordnung wie 16APSK, 32APSK (DVB-

S2X) evaluiert.

Abschließend wurde der BUC in Kombination mit

einem VSAT im Satelliten Link getestet und zeigt

Sende-Datenraten von bis zu 1Mbit/s.

Acknowledgements

I wish to express my sincere gratitude to Prof.Dr.-

Ing.Georg Böck who gave me the opportunity to

pursue my Ph.D. through his grants at the Mi-

crowave Engineering Lab of the Berlin Institute of

Technology. I would also like to thank Prof.Dr.-

Ing.Arne Jacob, and Prof.Dr. techn. Peter Weger

who agreed to be a second and third examiner for

this Ph.D. thesis, as well as Prof.Dr.-Ing. Clemens

Gühmann being the chairman of the dissertation

committee.

I would especially like to thank my officemate Felix

Rautschke for his attention to detail concerning

analysis, measurements and being a good friend. I

also extend my gratitude to my other colleagues at

the Microwave Engineering Lab, including Zihui

Zhang, Chi-Thanh Nghe, Sönke Vehring, Yaoshun

Ding, Markus Rose, Dr.-Ing. Andrea Malignaggi,

Mhd. Tareq Arnous, Dr.-Ing. Amin Hamidian and

Dr.-Ing. Paul Saad for their kind support and com-

radeship. In addition, I would like to thank Orkun

Konc, Stefan May and Sebastian Drews who sup-

ported me with their work.

Moreover, my thanks goes to Dr.-Ing.Simon Otto

and Prof.Dr.-Ing. Matthias Geissler from IMST

who participated within a joint research project.

In addition, I’m also grateful for the guidance of

Lothar Schenk, Martin Müssener, Dr.-Ing.Florian

Ohnimus and Uwe Dalisda during an internship at

Rohde&Schwarz. I could not write this acknowl-

edgements without mentioning the mechanical

manufacturing work done by Christian Birr as

well as substrate and mounting related work done

by Klaus Beister and Thomas Janda.

A special thanks goes to Sebastian Preis and An-

thony Ash for their review and proofreading.

This work was partially financed by the German

Space Agency DLR under the framework of the

Project ISISTAR.

Finally, I would like to thank my friends and family

and, especially Jennifer for tolerating my second

home on campus.

Contents

Zusammenfassung

List of Figures iv

List of Tables ix

List of Abbreviations x

List of Symbols and Nomenclature xii

1 Introduction 1

2 Fundamentals 4

2.1 Substrates .............................................. 4

2.2 Semiconductors ........................................... 8

2.3 Power Amplifier Theory ...................................... 12

2.4 SatCom Signals ........................................... 16

2.5 Measurement Techniques ..................................... 18

3 Power Amplifier 21

3.1 Combined MMIC PA ........................................ 22

3.2 250 nm GaN-HEMT Analysis ................................... 23

3.2.1 Manufacturing Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.2 Optimum Impedances ................................... 25

3.2.3 Ideal Matching Limits ................................... 25

3.2.4 Device Model ........................................ 27

3.3 Upper Ku-band MIC PA ...................................... 32

3.3.1 PA Design Approach .................................... 32

3.3.2 Design of Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3.3 Simulation Approach ................................... 37

3.3.4 Realisation .......................................... 40

3.3.5 Measurement Results ................................... 41

3.3.6 Summary .......................................... 45

3.4 Lower Ku-band MIC PA ...................................... 46

3.4.1 PA Design Approach .................................... 46

3.4.2 Design of Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.3 Simulation Approach ................................... 46

3.4.4 Realisation .......................................... 48

3.4.5 Measurement Results ................................... 48

3.4.6 Summary .......................................... 51

iii

3.5 Extended Ku-band MIC PA .................................... 52

3.5.1 PA Design Approach .................................... 52

3.5.2 Design of Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.3 Simulation Approach ................................... 52

3.5.4 Realisation .......................................... 55

3.5.5 Summary .......................................... 56

3.6 Efficiency Enhancement ...................................... 57

3.6.1 Envelope Tracking ..................................... 57

3.6.2 Doherty Amplifier ..................................... 60

3.6.3 Summary .......................................... 61

3.7 Discussion .............................................. 62

4 Block Up-Converter 63

4.1 Frequency Generation ....................................... 64

4.2 Hybrid Filter ............................................. 66

4.3 Amplifier ............................................... 70

4.4 dc/dc Conversion .......................................... 75

4.5 Realisation .............................................. 77

4.6 Simulation / Evaluation ...................................... 79

4.7 BUC Summary ............................................ 82

4.8 BUC Discussion ........................................... 83

5 Satellite Link 84

5.1 Link Budget ............................................. 86

5.2 Link Test ............................................... 89

5.3 Summary ............................................... 91

6 Conclusion 92

A Appendix 94

A.1 S-Parameter ............................................. 94

A.2 Transmission line Theory ...................................... 95

A.3 Amplifier Nomenclature ...................................... 97

A.4 Simulation Techniques ....................................... 98

A.5 Measurement Uncertainty ..................................... 101

A.6 Link Nomenclature ......................................... 102

Bibliography 106

Own Publications ............................................. 113

Co. Authored Publications ........................................ 114

Authored Workshops ........................................... 114

Own Publications not cited in this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

List of Figures

1.1 Available market for GaN related products. ................................. 1

1.2 View of the realised low-profile Ku-band VSAT called EASYSTAR. .................... 3

2.1 Layer stack of the Al2O3substrate (a) with the equivalent skin depths per metal layer (c). ....... 6

2.2 Substrate losses divided into (a) the αddielectric, (b) αcconductive as well as (c) the αttotal losses

for a MS-line (50Ω) over various frequencies. ................................ 6

2.3 Conductive αc, dielectric αdas well as the total losses αtfor a MS line with various impedances for

14GHz. ...................................................... 7

2.4 (a) shows the Qrradiated, Q0conductive and dielectric as well as Qttotal quality factor for an open-

ended λ/4MS line (50Ω) over various frequencies, and (b) various impedances for 14GHz. ...... 7

2.5 Cross sectional view of the GaN-HEMT with additional field plate technique. .............. 9

2.6 Cross sectional view of the Nf=6 gate finger GaN-HEMT of Wolfspeed (CGHV1J006D). ........ 10

2.7 Top view of the 6 gate finger GaN-HEMT. .................................. 10

2.8 Cross sectional view of the GaN-HEMT with equivalent circuit elements. ................ 11

2.9 Simulated example of ac gm behaviour as a function of VGS for a 250 nm GaN-HEMT (CGHV1J006D;

VDS =40V; 1 GHz). ............................................... 14

2.10 Simulated example of ac large-signal gm behaviour as a function of VGS and Pin for a 250nm GaN-

HEMT (CGHV1J006D; VDS =40V; 1 GHz). .................................. 15

2.11 Simulated example of (a) two-tone gain (b) harmonics (c) IMD3 (d) IMD5 for a 250nm GaN-HEMT

(CGHV1J006D; VDS =40V; 1 GHz; 1 MHz spacing). ............................. 16

2.12 Constellation Diagram of modulation schemes for DVB-S2 transmission (a) 8PSK (b) 16APSK. . . . . 17

2.13 Theoretical analysis of (a) BER vs. SNR (b) BER vs. EVM for various modulation scheme (DVB-S2;

α=0.25) (c) Spectral Efficiency vs. SNR (DVB-S2; B=6MHz; α=0.25; BER=10−6). ........... 17

2.14 Definition of the reference planes used within a probed measurement setup. ............... 18

2.15 Schematic view of the large-signal measurement setup. ........................... 19

2.16 Illustration of the pre-transformed Load-Pull setup. ............................. 20

3.1 Flow chart of the PA design procedure. .................................... 21

3.2 PA schematic with two packaged GaAs p-HEMT transistors combined via capacitive loaded branch-

line combiner. .................................................. 22

3.3 Picture of the PA with two packaged GaAs p-HEMT transistor combined via capacitive loaded

branch-line combiner. .............................................. 22

3.4 Large-signal measured output power, PAE and gain at different frequencies within the band for the

1dB compression point; VDS =8.5V; Idq=4A. ................................. 22

3.5 Top view of the Nft=4x6 gate finger GaN-HEMT of Wolfspeed (CGHV1J025D) representing 4 transis-

tor cells....................................................... 23

3.6 Top view of the Nft=12x6 gate finger GaN-HEMT of Wolfspeed (CGHV1J070D) representing 12 tran-

sistor cells...................................................... 24

3.7 (a) Sideview of FEM simulated mounting heat flow density of 100W dissipated power (b) Top view

of the 3-D EM simulation with 24 bond wires. ................................ 24

3.8 De-embedding from the intrinsic dc impedance to the optimum load impedance. ............ 25

3.9 Analysed theoretical matching limit (Bode Fano) of the complex Zin{Rin;CGS;Lpad}(top) and

Zout{Rdc;CDS;Lpad}(bottom) impedances for (a) various centre frequencies (b) for f0at 14GHz. . . . . 26

3.10 Simulated (a) ac transconductance gm, ID(b) 2nd and 3rd derivative of conductance for 14 GHz and

3.11 Simulated parasitic capacitances of the Die for (VGS = -8 V) and (a) 1 MHz (b) 10 GHz. ......... 27

3.12 Simulated optimum Load-Pull impedances ZLoad for Pout,max = 48dBm within 13.75;14;14.25;14.5GHz.

Furthermore, multi-frequency Load-Pull contours (MuFLoC) are shown for Pout and PAE that repre-

sent the least-intersection within Fup (VDS =40V; IDq ={300}mA; Pin =39 dBm). ............. 29

3.13 Simulated (a) IMD3 and (b) IMD5 related load impedances for various quiescent currents (VDS =40V;

IDq ={50; 150; 300}mA; Pin =30dBm). ..................................... 29

3.14 Simulated (a) IMD3 and (b) IMD5 related load impedances for various power levels (VDS =40V;

IDq =300mA; Pin ={30; 33; 36}dBm). ...................................... 30

3.15 Simulated (a) IMD3 and (b) IMD5 related load impedances for various baseband impedances

(VDS =40V; IDq = 300 mA; Pin = 30 dBm). .................................... 30

3.16 Simulated phase dependency of second (2·f0= 28 GHz) and third (3·f0=42GHz) harmonic reflection

coefficient Γ=0.95 on PAE, Pout at f0=14 GHz (a) 70 W device (b) 6 W device (VDS = 40 V; IDq =2% Imax). 31

3.17 Proposed (a) two stage PA topology with (b) theoretical total PAE considerations. ............ 32

3.18 Schematic of the initial output matching circuit. ............................... 33

3.19 (a) Measured and simulated radial stub with λ/4-line line and (b) additional gate resistor. ....... 34

3.20 (a) Calculation of characteristic impedance from two coupled MS lines (b) Calculation of characteris-

tic impedance from ncoupled MS lines (each with w=310µm), both for a Al2O3substrate with 5mil

thickness at 14GHz. ............................................... 35

3.21 (a) Schematic visualisation of the parallel MS-line concept with (b) added a Bus Bar in between. Step

by step visualisation of the virtual open in a Bus Bar. Starting with an open stub (c), double open stub

(d) resulting in interconnected symmetrical stubs (e). ............................ 36

3.22 Measured and simulated capacitance (a) lumped equivalent model (b) and layout (c) of Interdigital

capacitor. ..................................................... 37

3.23 (a) Schematic of the proposed two-stage amplifier divided into three matching circuits (IMN, ISMN,

OMN). Each transmission line (TL) is parallelised by n-times written underneath in green. Simulated

EM-based impedances realised by the matching circuits within Fup for the input sides of Q1(IMN)

and Q2(ISMN) (b) and for the output sides of Q1(ISMN) and Q2(OMN) (c). The plotted multi-

frequency Load- and Source-pull contours (MuFLoC) represent the minimum value over the desired

frequency range Fup............................................... 38

3.24 (a) Simulated small-signal (b) large-signal behaviour of the amplifier (VDS1,2 =40V; IDq1,2 =300 mA). . 39

3.25 Simulated (left) magnitude imbalance (right) phase imbalance of the transistor cells referenced to

(Q2.1...Q2.12). .................................................. 40

3.26 Simulated intrinsic load-lines (a) and power distribution over power bar (b). .............. 41

3.27 Example of an analysed amplifier large-signal transfer function by the STAN TM-Tool for an odd mode

injection in the (a) ISMN, (b) OMN. ...................................... 41

3.28 Simulated output spectrum with different (a) baseband impedance (b) biasing conditions (QPSK

4MSyms; 14GHz; Pout,avg =30W). ....................................... 41

3.29 Realisation of the amplifier. Side-view illustration of the MIC (a). Top view of the MIC (b). X-Ray

pictures of the bare-die Q1 (c), Q2 (d). ..................................... 42

3.30 Comparison between measured (sample #1) and simulated small-signal behaviour of the amplifier

(VDS1,2 =40V; IDq1,2 = 300 mA) (a). Comparison between six measured amplifiers within small-signal

condition (VDS1,2 =40V; IDq1,2 = 300 mA) (b). .................................. 42

3.31 Large-Signal measurement setup. ....................................... 42

3.32 Comparison between measured and simulated large-signal behaviour of the two-stage amplifier.

Power-sweep at 14.2GHz (VDS1,2 =40V; IDq1,2 =300mA). .......................... 43

3.33 Comparison between measured and simulated large-signal behaviour over frequency (VDS1,2 =40V;

IDq1,2 =300mA). ................................................. 43

3.34 Comparison between measured (a) and simulated (b) thermal behaviour (VDS1,2 =40V; IDq1,2 =300 mA;

Pout,avg =40W). .................................................. 43

3.35 Measured gain compression (a) and AM-PM conversion (b) with a 32APSK modulation (α=0.25;

16MSym/s) at an un-linearised amplifier for 14.25GHz. (VDS1,2 =40V; IDq1 = 300 mA; IDq2 = {300;

50}mA). ...................................................... 44

3.36 Measured modulation schemes of common SatCom signals for Pout, peak -PAPR, 14.25 GHz. (a) QPSK

(α=0.35; 16 MSym/s; DVB-S1) (b) 32APSK (α= 0.25; 16MSym/s; DVB-S2) (c) 64APSK (α= 0.05;

16MSym/s; DVB-S2X). ............................................. 44

3.37 Output spectrum of the PA for Pout,avg = 30 W and a QPSK signal with 16 MSym/s; α=0.35 (w)

and (w/o) a RFPAL at 14.375GHz (VDS1,2 = 40 V; IDq1 = 300 mA; IDq2 = 50 mA; RBW=200kHz; RMS;

VBW=10MHz; 300ms sweep; 100MHz span). ................................ 44

3.38 Measurement results for a QPSK signal with 16MSym/s; α=0.35 and a RFPAL at (VDS1,2 = 40 V;

IDq1 =300mA; IDq2 =50mA). .......................................... 44

3.39 (a) Schematic of the proposed two-stage amplifier divided into three matching circuits (IMN, ISMN,

OMN). Each transmission line (TL) is parallelised by n-times written underneath in green. Simulated

EM-based s-parameters while the ports are loaded with the conjugate optimum impedances for (b)

IMN (c) ISMN (d) OMN. ............................................ 47

3.40 Simulated EM-based impedances realised by the matching circuits from 12.5-13.5GHz (Flow) for the

output sides of Q1(ISMN) and Q2(OMN). The plotted MuFLoCs represent the minimum value over

the desired frequency range Flow........................................ 47

3.41 Simulated pulsed RF-behaviour of the amplifier for 10% duty cycle with 1 µs period at 13 GHz. . . . . 48

3.42 Realisation of the amplifier. Side-view illustration of the MIC (a). Top view of the MIC (b). X-Ray

pictures of the bare-die Q1 (c), Q2 (d). ..................................... 48

3.43 (a) Comparison between measured and simulated small-signal behaviour over frequency (VDS1,2 =40V;

IDq1,2 =300mA) with additional Monte-Carlo analysis (b) Measured small-signal behaviour in de-

pendency to IDq1,2 (VDS1,2 =40V) (c) Measured small-signal behaviour in dependency to VDS1,2

(IDq1,2 =300mA). ................................................. 49

3.44 Probed Large-Signal measurement setup. ................................... 50

3.45 Comparison between measured and simulated pulsed RF-behaviour (a) over the input power level

at 13GHz and (b) over frequency (VDS1,2 =40V; IDq1,2 =300mA). ...................... 50

3.46 Measured pulsed RF-behaviour at 13GHz(a) gain (b) PAE (c) saturated output power and PAE for

various biasing conditions of (Q1,Q2) (10% duty cycle VDS1,2 =40V). ................... 51

3.47 Analysed theoretical matching limit (Bode Fano) of the complex Zout{Rdc;CDS;Lpad}(bottom) impe-

dances for various supply voltages at f0=13.2 GHz. ............................. 52

3.48 Simulated EM-based impedances realised by the matching circuits from 12.5-14.5GHz (Fext) for the

output sides of Q1(ISMN) and Q2(OMN). The plotted MuFLoC represent the minimum value over

the desired frequency range Fext at VDS1,2 =50V. ............................... 53

3.49 Simulated EM-based S-Parameters while the ports are loaded with the conjugate optimum impedan-

ces for (b) IMN (c) ISMN (d) OMN. ...................................... 54

3.50 CW simulated (a) intrinsic voltage-swing (b) channel temperature for saturation operation (VDS1,2 =50V;

IDq1,2 =100mA; Pin =34dBm). .......................................... 54

3.51 (a) Top view of the extended Ku-band MIC (b) wedge-wedge bond-wire interconnection for Q1(c)

bond and ribbon interconnection for Q2.................................... 55

3.52 Comparison between measured and simulated small-signal behaviour over frequency (VDS1,2 =50V;

IDq1,2 =100mA) with additional Monte-Carlo analysis. ........................... 55

3.53 Comparison between measured and simulated large-signal behaviour (a) over the input power level

at 13GHz and (b) over frequency (VDS1,2 =50V; IDq1,2 =100mA). ...................... 56

3.54 Measured saturated pulsed output power and PAE for various supply voltages (10% duty cycle

IDq1,2 =100mA, Pin =34dBm). .......................................... 56

3.55 (a) Block diagram of the proposed ET system (b) Measured modulated RF and corresponding enve-

lope for a 470MHz DVB-T signal with 8.6MHz bandwidth measured at the drain. ........... 58

vii

3.56 Measured (a) PAE (b) gain of the Class-G PA at 13GHz (10% duty cycle, IDq1,2 = 300 mA). ....... 59

3.57 Measured (a) PAE (b) gain of the Class-G PA at 13GHz (10% duty cycle, IDq1,2 = 50 mA). ........ 59

3.58 (a) Schematic view of the 2-Way unequal Doherty using three Kuup MIC (b) simulation of the RF com-

pression (c) simulation of the current distribution between the main and peaking amplifier (14GHz;

CW, IMain =500 mA, VGS,Peak = -5 V). ....................................... 60

3.59 (a) Layoutview of the developed SIW coupler (b) de-embedded comparison between measurement

and simulation of the coupling [Kon+16]. ................................... 61

4.1 Schematic of the BUC including the predicted power levels and the power consumption. ....... 63

4.2 Layerstack of the HF circuit board. ...................................... 64

4.3 (a) Schematic of the multiplied PLO with its (b) measured SSB phase noise. ............... 64

4.4 (a) Schematic of the two-stage PLO with its (b) measured SSB phase noise. ................ 65

4.5 (a) Layout of the up-conversion with its (b) measured conversion gain. .................. 66

4.6 Transmission spectrum of the proposed transceiver in the Ku-band and block diagram of the up-

conversion path. ................................................. 67

4.7 Comparison between measurement and simulation of the proposed hairpin filter. ............ 67

4.8 Pictures of the realised filter on alumina substrate (a) hairpin (b) CLF (c) ringresonator (d) interdigital. 68

4.9 (a) 3D view of the ringresonator filter in CST with the appropriate coupling structure of the four

resonators, source and load. (b) Measured transmission and (c) reflection, as well as (d) group delay

results for the designed filters. ......................................... 69

4.10 (a) Layoutview of the ring resonator, the (b) SIW Filter as well as (c) the measurement results obtained. 71

4.11 (a) Layoutview of the realised dual directional coupler (b) measurement results. ............ 71

4.12 (a) Layoutview of the realised pre-amplifier with hybrid dual directional couplers and (b) measure-

ment results with de-embedded connectors. ................................. 72

4.13 Integration of the designed MIC PA into the hybrid stack. ......................... 72

4.14 Schematic of the IF linearisation. ........................................ 73

4.15 Normalised output power spectrum of the BUC at 14.35 GHz centre frequency with Pout=37.5 dBm.

A 10MSym/s 8PSK signal with 3.7dB PAPR is used and measured with RBW=300kHz; RMS;

VBW=3MHz; 2s sweep; 100MHz span. .................................... 74

4.16 Measured output constellation diagram for a 10MSym/s 8PSK signal with 3.7dB PAPR at Pout=36.7dBm

with a running RFPAL. ............................................. 74

4.17 (a) Schematic of the linearisation matching circuits (b) Layoutview of the realised IF linearisation

implemented in the BUC. ............................................ 75

4.18 (a) Schematic view of the realised dc/dc conversion with (b) a layoutview. ................ 75

4.19 Measured starting sequence for the dc/dc conversion with (a) the connector injection and (b) the PA

bias. ........................................................ 76

4.20 Measured reactance of four parallel dc-feeds. ................................. 76

4.21 Top view of the MS to WR75 transition (a) housing (b) with substrate (c) including the back short (d)

deembedded S-Parameter measurements of a transition. .......................... 78

4.22 (a) Layout view of hybrid integrated BUC (b) with housing. ........................ 78

4.23 Layoutview of RF-interconnection underneath the shielding walls. .................... 78

4.24 System simulation of the BUC for a varying input power level at the IF. ................. 79

4.25 CW measurements of the BUC (a) in saturation with dependency to the frequency and (b) to the input

power Pin...................................................... 79

4.26 Measured output of the BUC (w) and (w/o) linearisation for (a) gain compression (b) AM/PM (c)

spectrum for Pout, avg=39dBm, 32APSK 4 MSym/s. ............................. 80

4.27 Normalized measured power spectral density of the BUC (w) and (w/o) linearisation for (a) QPSK

1,5 MSym/s (b) QPSK 10 MSym/s (c) 16APSK 10MSym/s for Pout, avg = 39 dBm. ............. 81

4.28 Measured temperature behaviour within climate chamber of the BUC equipped with the 25W PA for

a QPSK signal with Pout,avg =39dBm. ...................................... 82

viii

5.1 (a) classical SatCom with broadcast FWL (b) data link via HUB and VSAT with additional RTL (Star-

or Mesh-Network). ............................................... 84

5.2 Launched transponders per year (data taken from [Sat]). .......................... 85

5.3 Various typical EIRP levels are calculated based on antenna gain versus PA output power. ....... 85

5.4 Link budget analysis calculating the equivalent power level (red) as well as the equivalent noise level

(blue) for a 4MHz QPSK signal displaying (a) the uplink (b) the transponder (c) the downlink. . . . . 86

5.5 FWL HUB to VSAT. ............................................... 89

5.6 RTL VSAT to HUB. ............................................... 90

5.7 FWL VSAT to VSAT. ............................................... 90

5.8 RTL VSAT to VSAT. ............................................... 91

A.1 Uncertainty analysis of probed TL (a) S21 (b) S11 (c) S21 unc. (d) S11 unc. (e) S21 phase unc. (f) S11

phase unc. ....................................................101

A.2 Statistical distribution for a RL = 20 dB and a RL = 14dB for (a),(b) input (c),(d) output coupler. . . . . 102

List of Tables

2.1 Properties of dielectric materials at 10GHz .................................. 5

2.2 Properties of conductor materials ....................................... 5

2.3 Properties of (compound) semiconductor materials ............................. 8

2.4 Parameters of GaN-HEMT scaling ....................................... 12

2.5 PAPR (dB)of different modulation schemes ................................. 17

2.6 Power measurement uncertainty related to mismatch conditions ..................... 19

3.1 Specifications of the 250 nm GaN-HEMTs process at10 GHz. ........................ 23

3.2 Bonding tolerances ............................................... 24

3.3 Simulated optimum source and load impedances (VDS =40V;IDq =0.3A) ................. 28

3.4 Schematic values of the proposed two-stage amplifier for f0=14GHz .................. 38

3.5 Linearity measurements for various modulation schemes .......................... 45

3.6 Schematic values of the proposed two-stage amplifier for f0=13GHz .................. 47

3.7 Schematic values of the proposed two-stage amplifier for f0=13.25GHz ................. 53

3.8 Comparison of state of the art PA in the Ku-band .............................. 62

4.1 Comparison of realised Ku-band filters .................................... 70

4.2 Measured average output power, EVM and minimum ACPR level (BW + 0.5MHz), without (w/o)

and with (w) RFPAL at 14.35 GHz for 8PSK modulation .......................... 74

4.3 Comparison of both PAs in the BUC ...................................... 81

4.4 Comparison to commercial BUC in the extended Ku-band (13.75-14.5GHz) ............... 83

5.1 (a) Uplink calculation within the FWL; (b) Downlink calculation within the FWL; (c) resulting

total link margin within the FWL (Berlin to AM44; 14.0722GHz(H) up; 11.5222GHz(V) down;

0.5MSym/s; QPSK; FEC 3/4; α=0.35; Pout =10W; 99.5% availability ITU-R) ............... 87

5.2 (a) Uplink calculation within the RTL; (b) Downlink calculation within the RTL; (c) resulting total link

margin within the RTL (Berlin to AM44; 14.0737GHz(H) up; 11.5237GHz(V) down; 0.3MSym/s;

QPSK; FEC 3/4; α=0.35; Pout =10W; 99.5% availability ITU-R) ...................... 88

5.3 Measured data-rate HUB to VSAT in FWL. .................................. 89

5.4 Measured data-rate HUB to VSAT in RTL. .................................. 90

5.5 Measured data-rate VSAT to VSAT in FWL. ................................. 90

5.6 Measured data-rate VSAT to VSAT in RTL. .................................. 91

A.1 Measurement uncertainty of 500 and 1000µm pitch GSG Z-ProbesTM ...................102

A.2 (a) Uplink calculation within the FWL; (b) Downlink calculation within the FWL; (c) resulting total

link margin within the FWL (Munich to Eutelsat 33E; 13.939087GHz(H) up; 11.13537GHz(V) down;

5MSym/s; QPSK; FEC 5/6; α=0.35; Pout =10W; 99.5% availability ITU-R) ................105

A.3 (a) Uplink calculation within the RTL; (b) Downlink calculation within the RTL; (c) resulting total link

margin within the RTL (Berlin to AM44; 13.93537 GHz (H) up; 11.113087 GHz(V) down; 1.2 MSym/s;

QPSK; FEC 2/3; α=0.35; Pout =10W; 99.5% availability ITU-R) ......................105

List of Abbreviations

2DEG Two Dimensional Electron Gas

2D Two Dimensional

3D Three Dimensional

3G 3rd Generation mobile communication

5G 5th Generation mobile communication

ACLR Adjacent chanel leakage ratio

ACPR Adjacent chanel power ratio

AM Amplitude Modulation

AM/AM Amplitude to Amplitude Modulation

AM/PM Amplitude to Phase Modulation

BB Base Band frequency

BER Bit Error Rate

BUC Block up-converter

BP Band Pass

CAD Computer-aided design

CAE Computer-aided engeneering

T-CAD Technology-Computer-aided design

CW Continous Wave

DPD Digital predistortion

DUT Device under Test

DVB-S Digital Video Broadcasting-Satellite

DVB-S2 Digital Video Broadcasting-Satellite 2nd Generation

DVB-S2x Digital Video Broadcasting-Satellite 2x future Generation

EIRP Effective Isotropic Radiated Power

ESR Equivalent Series Resistance

EVM Error Vector Magnitude

EM Electro Magnetic

ET Envelope Tracking

FBW Fractional Bandwidth

FDTD Finite-Difference Time-Domain Method

FEC Forward Error Correction

FEM Finite Element Method

FET Field Effect Transistor

FP Field Plate

FSS Fixed Satellite Services

FWL Forward Link

GaN Gallium Nitride

GaAs Gallium Arsenide

GEO Geosynchronous Earth Orbit

GND Ground Potential

GSG Ground Signal Ground

GSOLT General Short Open Load Thru calibration

HEMT High Electron Mobility Transistor

HP High Pass

HTS High throughput Satellite

IBO Input back off

IF Intermediate Frequency

IL Insertion Loss

IMD Inter modulation distortion

IMD3 3rd order Inter modulation distortion

IMD5 5th order Inter modulation distortion

IMN Input Matching Network

ISISTAR Integrated Satellite Terminal for stationary Networks

ISMN Inter Stage Matching Network

ISV Individual Source Via

LDMOS Laterally Diffused Metal Oxide Semiconductor

LEO Low Earth Orbit

LNB Low Noise Block converter

LO Local Oscillator

LP Low Pass

LVDS Low Voltage Differential Signal

MIC Microwave Integrated Circuit

MMIC Monolithic Microwave Integrated Circuit

MS Micro-Strip

MuFLoC Multi Frequency Load-pull Contours

OBO Output back off

OMN Output matching network

OMT Orthogonal mode transducer

PA Power Amplifier

PAE Power-added Efficiency

PDE PartialDifferential Equations

PCB Printed circuit board

PAPR Peak-to-average power ratio

PLL Phase Locked Loop

PLO Phase Locked Oscillator

PM Phase Modulation

PSD Power spectral density

PSK Phase shift keying

QAM Quadrature Amplitude Modulation

RL Return Loss

RTL Return Link

RF Radio Frequency

RFPAL Radio Frequency Power Amplifier Linearisation

RFPD Radio Frequency Pre Distortion

RHP Right Half Plane

RX Receive

SIW Substrate Integrated Wave-guide

SNR Signal Noise Ratio

SPICE Simulation Program with Integrated Circuit Emphasis

SRF Self Resonant Frequency

SSB Single Side Band

SSPA Solid State Power Amplifier

TCP Transmission Control Protocol

TDR Time Domain Reflection

TCAD Technology Computer Aided Design

TDMA Time Division Multiple Access

TL Transmission Line

TOI Third Order Intercept

TRL Thru Reflect Line calibration

TX Transmit

TWTA Travelling Wave Tube Amplifier

UHDTV Ultra High Devinition Tele Vision

VCO Voltage controlled Oscillator

VCXO Voltage controlled Crystal Oscillator

VGA Variable Gain Amplifier

VNA Vector Network Analyzer

VoD Video onDemand

VSAT Very Small Aperture Terminal

VSWR Voltage Standing Wave Ratio

xii

List of Symbols and Nomenclature

a, c lattice constant ˚

αroll-off factor

αcconductive attenuation constant dB/cm

αddielectric attenuation constant dB/cm

αiforward travelling wave quantity Np

αrradiated attenuation constant dB/cm

αttotal attenuation constant dB/cm

Attatm atmospheric attenuation dB

Attmis mispointing attenuation dB

Attrain rain attenuation dB

Attphys sum of physical link attenuation dB

Bbandwidth Hz

βeeven mode image impedance Ω

βoodd mode image impedance Ω

βireflected travelling wave quantity Np

Ccarrier power dBm

Cds intrinsic output capacitance F

Cgd intrinsic feedback capacitance F

Cgs intrinsic input capacitance F

CDS device output capacitance F

CGD device feedback capacitance F

CGS device input capacitance F

C/N Carrier to Noise distance dB

C/N (th) Carrier to thermal Noise distance dB

C/(N+I) Carrier to Noise distance including intermodulation Noise dB

δskin-depth µm

Ddie distance between pad centre to edge of die µm

Dgap distance between die and substrate µm

Dpad distance between gap and pad on substrate µm

Dtotal total distance pad to pad µm

Ebenergy per bit J

Esenergy per symbol J

EBbreak down field V/cm

EGbandgap eV

εrdielectric constant

εre effective dielectric constant

ηefficiency %

ηccombiner efficiency %

ffrequency Hz

f0fundamental centre frequency Hz

n·f0nthharmonic centre frequency Hz

fKNEE knee frequency (k≥1) Hz

fTtransit frequency Hz

fMAX maximum oscillation frequency Hz

Fin band frequency range Hz

Fup upper in band frequency range Hz

Flow lower in band frequency range Hz

Fext extended in band frequency range Hz

Γreflection coefficient

Γin input reflection coefficient of DUT

Γoutput output reflection coefficient of DUT

gm transconductance S

xiii

gmnnth derivative of transconductance S

gd conductance S

GA,TX antenna gain TX dBi

GA,RX antenna gain RX dBi

GSS small-signal gain dB

G/T Gain to Noise Temperature dB/K

hheight of substrate µm

I0additive noise

Iddrain current A

iD,f0fundamental output current A

iD,IMD33rd intermodulation products output current A

Idc direct current A

IDS drain-source current A

ID,max maximum drain-source current A

ID,sat saturated drain-source current A

IDQ quiescent current A

λ0free space wavelength m

Lbond bond inductance H

LGparasitic drain inductance H

lggate length µm

LGparasitic gate inductance H

Lpad pad inductance H

Lspace free-space attenuation dB

LSparasitic source inductance H

µelectron mobility cm2/V s

Nthermal noise power W

N0equivalent thermal noise power

Nfnumber of fingers

Nft total number of fingers

[PAEf1]PAE contour depending on f1,ZL%

[PAEF]PAE contour depending on F,ZL%

Pdiss,max max. dissipated power W

Pdc dc power consumption W

Pin input power dBm

Pin,1dB input 1dB compression point dBm

Pin,avg average input power dBm

Pin,pk peak input power dBm

Pin, unc mismatch related measurement uncertainty dB

Pout output power W or dBm

Pout,1dB output 1dB compression point W or dBm

Pout,avg average output power W or dBm

Pout,pk peak output power W or dBm

Pout,sat saturated output power W or dBm

Pout, unc mismatch related measurement uncertainty dB

[Pout, f1]output power contour depending on f1,ZLdBm

[Pout, F]output power contour depending on F,ZLdBm

Φelectrical length of transmission line ◦

PN single side-band phase-noise dBc/Hz

Qquality factor

Qcconductive quality factor (MS)

QCCharge eV

Qddielectric quality factor (MS)

Qrradiation quality factor (MS)

Qttotal quality factor (MS)

R∆max, JC max. temperature difference junction to case K/W

Ra Roughness µm

Rccode rate

Rgs Schottky gate source resistance Ω

Rgd Schottky gate drain resistance Ω

RGohmic gate resistance Ω

RDohmic drain resistance Ω

Rds drain source channel resistance Ω

Ron on resistance Ω

xiv

RSsheet resistance (MS) / ohmic source resistance Ω

RT H thermal conductivity W/mK

Rmmodulation rate Bd or S/s

ρelectrical resistivity Ω/m

[Stot]measured S-Parameter Matrix

[Ttot]measured T-Parameter Matrix

tthickness of metallisation µm

tan δloss angle

TTemperature K

TA,RX antenna noise temperature K

TReffective noise temperature K

TRX noise temperature of receiver K

Θconduction angle ◦

vsat,n electron saturation velocity cm/s

Vcc common collector voltage V

Vgs,trap gate source voltage traps gate-lag V

VGS static gate source voltage V

Vds,trap drain source voltage traps drain-lag V

VDS static drain source voltage V

VFIX fix supply voltage V

Vknee knee voltage V

VMOD modulated supply voltage V

Vp-off pinch off voltage V

VT H threshold voltage V

ωangular frequency rad

wwidth of MS line µm

Wgate width mm

Wttotal gate width mm

Z0characteristic impedance Ω

Z0,e characteristic even-mode impedance of MS Ω

Z0,en characteristic even-mode impedance of coupled MS Ω

Z0,o characteristic odd-mode impedance of MS Ω

Z0,on characteristic odd-mode impedance of coupled MS Ω

ZL,opt optimum load impedance Ω

ZS,opt optimum input impedance Ω

ZT L characteristic impedance of transmission line Ω

1 Introduction

Motivation and Objectives

In the early 1930s space researchers found a circu-

lar orbit above the equator following the earth’s

rotation. Within this ≈35786 km distance to the

ground, objects seem to be motionless above ground,

hence the name Geosynchronous Earth Orbit (GEO).

A signal directed to this position may be reflected

and directed back to earth, achieving a huge cov-

erage on earth, as C. Clarke stated in 1945 [Kra84].

Due to the high distance to the ground, signals di-

rected to this orbit are attenuated by the free-space

loss. It is for this very reason why a signal has to

be amplified and extraterrestrially relayed within a

satellite [Cla45]. This relaying was first carried out

by Syncom3, a GEO-satellite in 1964. Its aim was

to broadcast television coverage across the Pacific

for the Olympic games.

Nowadays, satellite services are widely used for

broadcasting as well as time-sensitive and critical

communication. Apart from new space satellite con-

stellations in the low earth orbit (LEO), traditional

Ku-band satellite communication (SatCom) in the

geostationary orbit (GEO) remains interesting. The

very small aperture terminals (VSATs) are a partic-

ularly growing market due to the increasing num-

ber of satellite launches and resulting reduced ca-

pacity costs. With the usage of these VSATs, it is

possible to provide network or internet connection

to remote regions. Nevertheless, VSATs are lim-

ited to a certain equivalent isotropically radiated

power (EIRP) either in terms of the antenna gain or

the output power of the block up-converter (BUC).

By increasing the antenna gain, which comes along

with increasing the size of a dish or planar antenna,

the VSAT gets bulky and impractical [Mar03]. In-

creasing the power of the BUC normally leads to a

very heavy housing with a higher power consump-

tion and a rapid growth of costs.

GaN-HEMT technology can play a major role in

VSAT

SATCOM

Wireless backhaul

CATV

1 2 4816 32 64

Frequency (GHz)

0.1

100

1000

Power (W)

Radars & avionics

Basestation

FIGURE 1.1: Available market for GaN related products.

lowering the costs of BUCs within VSAT, build-

ing a bridge between low power GaAs p-HEMT

devices and high power travelling wave tube am-

plifiers (TWTA). The available market for GaN

related products shown in Fig.1.1 clearly depicts

the VSAT as a major part in the SatCom market

[Dev16]. However, the SatCom market can serve

as a technological bridge between the already fo-

cussed mobile communication (Basestation) mar-

ket in the lower frequency range and the techni-

cally sophisticated wireless backhaul market.

Within the GEO satellite market the Ku-band fre-

quency range is becoming more and more attrac-

tive for VSAT applications. It can take advantage

of low capacity costs due to an increasing num-

ber of transponders. In comparison to Ka-band or

even V-band applications it benefits from a moder-

ate rain-margin.

Research Gap

With the upcoming device technology of GaN-

HEMT, a significant amount of effort was put into

developing power amplifiers for the mobile com-

munication market [Pen+12]. The trend of manu-

facturing GaN-HEMT on SiC and the advantages

considering the thermal conditions as well as the

lowered parasitics has led to great achievements

Chapter 1. Introduction

in efficiency enhanced power amplifiers in the mo-

bile communication market. This is particularly

the case with the popular 400nm GaN-HEMT de-

vice technology, nowadays manufactured by sev-

eral foundries, boosting power amplifiers to higher

efficiencies in their saturation as well as their back-

off operation. Nevertheless, the technologies are

limited to a certain usage of up to ≈6GHz due to

their parasitics.

Newer manufacturing technologies like 250nm

(quarter micron) further increase the usable fre-

quency range with transit frequencies of up to

40GHz. However, not only is the usable frequency

limited by the transistor’s intrinsic parasitics but

the mounting and bonding of the transistor to a

matching circuit are a hindrance as well. To ac-

commodate the demand towards higher frequen-

cies there are three common approaches within

research:

Firstly: The tolerances can be prevented

by designing monolithic microwave integrated cir-

cuits (MMIC) with the matching circuits directly

realised on the GaN/SiC substrates. This way, low

parasitic interconnections between the transistor

cells and its matching can be realised. However,

the development of a MMIC is extremely expen-

sive due to the costs of masks for the lithographic

manufacturing steps. Furthermore, the losses of

the SiC carrier substrate are a dominant part of the

MMIC losses, as can be seen in Sec.2.1. Neverthe-

less, power levels up to Pout ≈25 W are realised

by the usage of 250nm GaN-HEMT technology

[Kan+14], [Creb].

Secondly: With an increase in output

power the amplifiers are realised with high di-

electric matching circuits, mounting the bare-die

in between [Kaz+11], [Ima+14]. These microwave

integrated circuits (MIC) lower the costs of a pro-

cess run down to the bare-die size. Thanks to this

MIC techniques power levels up to Pout ≈80W

were obtained. While comparing the device sizes

of this second approach (MIC) to the first (MMIC),

one will recognize that the total gate-width which

is necessary for achieving an equal output power

level, is far higher for a MIC compared to a MMIC.

This can be explained by the higher losses of the

high dielectric matching circuits resulting in a

lower efficiency (Sec.2.1).

Thirdly: The mounting/assembling toler-

ances, and therefore the manufacturing tolerances,

can be reduced based on flip-chip mounting tech-

nologies. This method eases an integration into

hybrid substrate environments. However, packag-

ing always significantly reduces the performance

of the devices. The thermal connection between

the device and a sink is extremely reduced by the

package. Furthermore, the package reduces the up-

per frequency limit of the device due to parasitic

package capacitances. Nowadays, only low-power

devices are matched in the X-band with power lev-

els up to Pout ≈5W [Pav+15].

Approach

Within this thesis high power amplifiers have

been developed that rely on a hybrid matching

approach (MIC). Commercially available bare-

dies were used with far less expense compared

to MMICs. With an increased size of the bare-die

the optimum impedances of the devices lowers.

Special matching circuit techniques have therefore

been developed which are capable of providing

low impedance levels to the bare-die while reduc-

ing the transformation losses, when compared to

the high k substrates described in the second ap-

proach.

A key-component of these matching circuits is a

Bus Bar, first described by Marsh, for use with

MMIC technologies [Mar+99]. Within this present

work, the technique is enhanced by the use of mul-

tiple parallel microstrip (MS) lines for an even-

mode propagation, and applied within a MIC

design. A matching network with optimal load

impedances less than 1Ωis achieved by these par-

allelization (MS) lines.

All mounting and fabrication related parasitics, as

well as tolerances, were analysed through the use

of a 3-D EM-simulation. With regards to these

constraints, the theoretical bandwidth limitations

Chapter 1. Introduction

FIGURE 1.2: View of the realised low-profile Ku-band

VSAT called EASYSTAR.

of the bare-dies have been analysed in detail by

the techniques of Bode and Fano [Fan50]. These

ideal matching limits are proven by the usage of

Load-Pull simulations. This work enhances the

classical Load-Pull techniques to a definition of

Multi Frequency Load Pull Contours (MuFloC).

Furthermore, the manufacturing as well as device

constraints were taken into account for the design

of matching circuits.

As an outcome of this applied technique, power

levels of up to Pout= 70 W were achieved for three

different designs in the Ku-band.

Furthermore, these MICs have been implemented

into a hybrid planar BUC taking advantage of a

low power consumption. The implementation of

all parts of the BUC, namely the high power MICs,

the frequency generation as well as the dc/dc con-

version into one housing, eases the handling for a

user. Despite the lower power consumption of the

BUC, a GaN-HEMT typical soft compression was

cancelled by the usage of a change in the biasing

as well as an active RF-predistortion in real-time.

Finally, the BUC is connected to a planar TX-RX

aperture shown in Fig. 1.2 building a lightweight

thin VSAT. The VSAT is an outcome of the project

ISISTAR which combines all the components of a

VSAT, namely antenna, LNB, BUC and modem, to

one system. During SatCom link measurements,

the performance of the VSAT was evaluated.

Thesis Structure

This thesis is structured as follows. Each section

is divided into subsections which are introduced

in detail at the beginning of the section. These sub-

sections are summarized at the end, while a discus-

sion compares the developments of each section

with state of the art results.

Starting with the Fundamentals (Sec.2), a basic in-

sight is given to all themes that are related to mi-

crowave technology for the use in SatCom.

The main Sec.3focuses on the development of

MIC PAs where three designs are compared and

evaluated. At the end, the back-off efficiency of

the designs is enhanced, which finally leads to a

discussion.

Sec.4describes the design and measurements of a

block-up-converter.

Within, Sec.5all individually developed compo-

nents are proven towards their combined function-

ality in a satellite link.

Finally, the achievements are summed up in the

conclusion in Sec.6.

2 Fundamentals

This chapter will provide insight into the funda-

mentals which have been applied to this work.

Each subsection will provide a basic understand-

ing of general knowledge related to power ampli-

fier design with its application on the devices and

frequencies used in the circuits developed later on.

For a more detailed understanding, references to

the given literature are provided. In order to re-

duce the number of fundamentals required, there

are a number of descriptions located in the Ap-

pendix of this work. The definition of commonly

known equations is mainly given for nomenclature

purposes like for S-Parameters in Appx.A.1.

To determine the limitations of hybrid matching

circuits the substrate parasitics are introduced in

Sec.2.1. In relation to these calculations, the neces-

sary equations are given in Appx.A.2.

Fundamental aspects of the semiconductors and

especially GaN-HEMTs used in this work are given

in Sec.2.2.

Sec.2.3 introduces the Power Amplifier Funda-

mentals necessary for an understanding of the

work. Amplifier related nomenclature is given

in Appx.A.3. An introduction to simulation tech-

niques is given in Appx.A.4 for circuit as well as

electromagnetic-simulation.

An introduction to the commonly used SatCom sig-

nals and the necessary requirements for a system

design are given in Sec.2.4.

Sec.2.5 describes a basic understanding of HF mea-

surement techniques used within this thesis. The

uncertainties related to the small and large signal

measurements used in this work are explained in

Appx.A.5.

2.1 Substrates

Substrates are key-components for all HF circuits.

Their main application is for routing signals be-

tween active devices. By increasing the frequency

of the signals, the parasitics of these interconnec-

tions, namely their equivalent capacitance and

inductance, increase as well. It can therefore no

longer be assumed that these connections are ideal.

The common line-type for HF transmissions is the

microstrip (MS) line with its quasi-TEM behaviour.

For designing MS transmission-lines several pa-

rameters need to be determined. The characteristic

impedance Z0can be calculated based on the equa-

tions of Wheeler [Whe78]. They are related to the

permittivity of the substrate εrand to its effective

permittivity εre. Additional dispersion effects are

described by Kobayashi [Kob88]. Hammerstad et.

al. defined three factors that lead to losses within

a HF line [Ham+80]:

1. The losses related to the conductivity of the

metallisation are called αc. These metal

losses are in proportion to the square root

of frequency and different for various line-

types due to the different sheet resistances

in MS, coax or wave-guide. In addition, the

skin effect in combination with the rough-

ness Ra of the metallisation, increases ac.

2. αdconsiders the dielectric losses within the

substrate. Additional dispersion can further

increase this loss factor. It is in proportion

to frequency and constant over various line-

types.

3. The radiation losses αrincrease with fre-

quency and are mainly relevant to open-

ended structures.

Chapter 2. Fundamentals

TABLE 2.1: Properties of dielectric materials at 10GHz

εrtan δ Ra RT H h

(µm) (W/mK) (µm)

Al2O39.9 0.0001 0.1 37 127

4H-SiC19.66 0.003 0.1 350 100

DLI CD 38 0.004 ≤5 1.59 254

RO4003c 3.38 0.0027 520.71 220

FR4 4.7 0.01432-6 0.25 254

14H-SiC is a semiconductor

2Lo Profile

3at 10 MHz.

Dielectric Materials

A preliminary analysis of the substrates used in

this work should introduce parasitics and losses

within the Ku-band. Different types of dielectric

materials and their properties are shown in Tab. 2.1

with the substrate height hused in this work.

FR4 is a representative for a product in the low fre-

quency consumer market, whereas Al2O3are ce-

ramic or RO4003c are hydrocarbon-glass based HF

substrates. 4H-SiC is described because it is the

common choice for all GaN-HEMT related MMICs

that are grown on SiC substrates. Within this table

there is a representative of a high k substrate (DLI

CD) with a εr=38 which is used in single layer ca-

pacitors or for a hybrid pre-matching next to a bare-

die.

As a first comparison related to the suitability in

high frequency applications, their tan δ, which rep-

resents the dielectric losses, needs to be consid-

ered. Additionally, the selection of the substrate

is always related to the impedance-levels that are

needed and the losses that can be tolerated. For

example, to match extremely low ohmic impedan-

ces a high permittivity substrate can be helpful,

whereas a low height of the substrates halways

corresponds to a small width wof the MS-line

and as a result a high sheet resistance RS. Fur-

thermore, the roughness of the dielectric materials

(Al2O3, DLI CD) is a consequence of the manufac-

turing process. The ceramic based materials can

be polished before the metallisation gets sputtered.

Hence the Ra of the dielectric material is directly

related to the metal sputtered on top of it.

TABLE 2.2: Properties of conductor materials

ρ RT H t δ1

(Ωm) (W/mK) (µm) (µm)

Cu 1.67e-8 393 35 0.54

CuMoCu 2.4e-8 295 1500 0.65

Au 2.4e-8 297 10 0.65

Au-20% Sn 1.6e-7 57 20 1.67

Ti 5.5e-7 22 0.06 3.01

Pd 1.06e-7 70 0.2 1.35

NiCr 1.1e-6 74 0.06 2.18

1skin depth for 14GHz.

For hydrocarbon-glass or PTFE based substrates

the Ra is related to the copper foil that is applied

to the substrate. Within this work, only rolled in-

stead of electro-deposited copper is used which

is suitable for HF-application. For the RO4003c

substrate, chosen in here, a special LoPro copper

foil of Rogers is used that should further lower the

Ra. These foils have a thickness of 35 µm and its

conductivity can be observed from Tab.2.2.

Conductor Materials

Due to manufacturing limitations on top of a ce-

ramic based dielectric, some adhesive layers need

to be applied underneath the real conductor. For

the used Al2O3, this metallisation stack contains

different layers (NiCr, Ti, Pd, Au) that are neces-

sary for realising NiCr resistors on the substrate

(Fig.2.1(a)). Different conductivities and thick-

nesses of these materials lead to a layer depen-

dent analysis of skin depth in the metallisation

stack, shown on the right of Fig.2.1(c). This way

it can be determined that the thickness of the ad-

ditional layers is low compared to Au. However,

the conductivity (σ) of these additional layers is

low, which induces the skin depth to a fraction of

the wavelength. Equation 2.1 shows the accurate

calculation of the skin depth, where the second

part of the formula (in rectangle brackets) can be

neglected for frequencies below ω≪1

ρεr.

δ=2ρ

ωµ[√»1 + (ρωεr)2+ρωεr](2.1)

The skin depth δis calculated for each conductor at

14GHz and given in Tab.2.2. It can be calculated

Chapter 2. Fundamentals

FIGURE 2.1: Layer stack of the Al2O3substrate (a) with

the equivalent skin depths per metal layer (c).

per layer depending on the layer thickness from

Fig.2.1(a) and the resistivity from Tab. 2.2. With

these values shown in Fig.2.1(c) an equivalent con-

ductivity of the composite layer stack can be cal-

culated to σcomp =1.97e6S/m at 14GHz. This low-

ered conductivity is later lowered again by taking

the roughness of the dielectrics into account using

a Hammerstad approximation. The described ap-

proximation is especially useful for easing a mul-

tilayer field-simulation, which is incapable of solv-

ing a thin thickness and rough width of the mesh

simultaneous.

Loss Analysis

Based on the dielectric as well as metallic parame-

ters, the losses of a MS-line can be calculated, as de-

scribed in detail in [Bah03, 429ff.] and Appx.A.2.

The given parameters, namely the height of the

substrate hand the thickness of the conductor t

lead to a calculated width wof the MS-line to sat-

isfy ZT L =50 Ω. Then the αddielectric (Fig. 2.2(a))

αcconductive (Fig.2.2(b)) as well as the αttotal

losses (Fig.2.2(c)) for a MS-line over various fre-

quencies can be calculated. Within these total

losses the dispersive character of the dielectric

material, the roughness and therefore its lowered

sheet resistance is taken into account.

The αddielectric losses are low for the dielectrics

with the lowest tanδthat is the Al2O3(Fig.2.2(a)).

The dielectric losses for FR4 are in the order of 10−2

(dB/cm) higher compared to Al2O3. By consider-

ing the αcconductive losses, one must realise that

the FR4 metallisation represents the lowest losses

due to its high width wof the MS-line (Fig.2.2(b))

0 5 10 15 20 25 30

10−4

10−3

10−2

10−1

100

Frequency (GHz)

Loss (dB/cm)

αd RO4003c

αd AL2O3

αd SiC

αd DLI

αd FR4

(a) αd

0 5 10 15 20 25 30

10−2

10−1

100

Frequency (GHz)

Loss (dB/cm)

αc RO4003c

αc AL2O3

αc SiC

αc DLI

αc FR4

(b) αc

0 5 10 15 20 25 30

10−2

10−1

100

Frequency (GHz)

Loss (dB/cm)

αt RO4003c

αt AL2O3

αt SiC

αt DLI

αt FR4

FIGURE 2.2: Substrate losses divided into (a) the αddi-

electric, (b) αcconductive as well as (c) the αttotal losses

for a MS-line (50Ω) over various frequencies.

related to the low Ra. Hence the smallest wof

all substrates being the one of the DLI high εr

substrate with its moderate Ra, resulting in con-

ductive losses in the order of 10−1(dB/cm) higher

than the FR4 metallisation. The αttotal losses

Chapter 2. Fundamentals

0 50 100 150 200

10−3

10−2

10−1

100

Impedance (Ω)

Loss (dB/cm)

αc RO4003c

αd RO4003c

αt RO4003c

αc AL2O3

αd AL2O3

αt AL2O3

FIGURE 2.3: Conductive αc, dielectric αdas well as the

total losses αtfor a MS line with various impedances for

14GHz.

are the sum of both. The DLI high εrsubstrate

clearly produces the highest losses in the order

of 1.5dB/cm at 14GHz (Fig.2.2(c)). Furthermore,

the high conductive losses for the FR4 as well as

the SIC determines the total losses in the range of

0.4dB/cm at 14GHz. This analytical result indi-

cates that the RO4003c is the best choice when it

comes to losses related to the ZT L =50 Ωline impe-

dance with 0.2dB/cm at 14GHz.

By lowering the ZT L the wincreases and as a result

the sheet-resistance of a MS-line decreases. This

way the low impedance levels benefit from low-

ered conductive losses (αc) as shown in (Fig. 2.3)

for 14GHz. Approximately half of the energy is

dissipated in the conductor for a ZT L = 10 Ωline

impedance compared to the ZT L = 50 Ωline impe-

dance.

Quality Factor Analysis

An open-ended MS-line is a resonator with its qual-

ity factor Qsumming up the losses related to it.

The Qdescribes the ability of a combination (sub-

strate and metallisation) to be used for a HF fil-

ter or matching applications. In addition to the

already defined losses αc,αdthe radiation plays

a major role for open-ended structures and is de-

fined as αr.

4 6 8 10 12 14 16 18

101

102

103

104

Frequency (GHz)

Q0 RO4003c

Qr RO4003c

Qt RO4003c

Q0 AL2O3

Qr AL2O3

Qt AL2O3

(a)

0 50 100 150 200

100

101

102

103

104

Impedance (Ω)

Q0 RO4003c

Qr RO4003c

Qt RO4003c

Q0 AL2O3

Qr AL2O3

Qt AL2O3

(b)

FIGURE 2.4: (a) shows the Qrradiated, Q0conductive

and dielectric as well as Qttotal quality factor for an

open-ended λ/4MS line (50Ω) over various frequencies,

and (b) various impedances for 14GHz.

The relating quality factors [Bah03, 436 ff.] can be

defined with:

=λ0(αc+αd)

π√εre(f)(2.2)

(2.3)

The minor losses for an open-ended λ/4MS line

on the Al2O3as well as the RO4003c substrates are

clearly the αrradiation losses, which is why the re-

lated quality factor Qris high, decreasing towards

higher frequencies (Fig.2.4(a)). Furthermore, the

line width wof the RO4003c substrate is higher,

resulting in a lowered Qrcompared to the Al2O3.

Only the Qtdetermines the unloaded Qof the res-

onator and identifies the Al2O3substrate as the bet-

ter choice for 14GHz applications (Qt=45).

Chapter 2. Fundamentals

Although both substrates only represent moder-

ate quality factors the analysis can be extended

by lowering the ZT L line impedance as shown

in (Fig.2.4(b)). The Al2O3substrate shows an in-

creased Qtof up to 100. Paired with its high man-

ufacturing accuracy, it is the preferred choice for a

realisation of matching and filter structures. The

lowest losses were achieved by the RO4003c sub-

strate, additional shielding would also improve

the high radiation losses.

2.2 Semiconductors

Semiconductor materials

Semiconductor materials are the opposite of iso-

lators. Inserting additional impurity atoms into

the semiconductor lowers its specific resistance.

Nowadays only extrinsic semiconductors with IV

valent atoms inserted in an n-channel are used for

HF applications. The most significant properties

of semiconductors are shown in Tab.2.3. The elec-

tron mobility µespecially limits the upper transit

frequency, whereas a wide bandgap EGis suitable

for high power applications. The breakdown-field

EBlimits the maximum operation field in the semi-

conductor. A combination of the electron mobility

µand the breakdown-field EB, called the satura-

tion velocity (vsat,n=µ·

E) limits the semiconduc-

tor towards its high power and high frequency

applications. Thus GaN clearly outperforms GaAs,

enabling far higher current densities.

The compound semiconductors SiC, GaAs and

GaN are nowadays grown by a molecular beam

epitaxy (MBE) on a foreign substrate [Aae+11,

p. 23]. The foreign substrate needs to represent

as little lattice mismatch to the compound semi-

conductor as possible while its lattice constant is

described via a, c 1. The combination of GaN on Si

compromises between costs and power, whereas

GaN on SiC is a great fit for all high-power ap-

plications. The thermal conductivity RT H of SiC

1The hexagonal Wurtzide crystal structure needs to be repre-

sented by the lattice constant aand c.

TABLE 2.3: Properties of (compound) semiconductor

materials

Si 4H-SiC GaAs GaN

bandgap

EG(eV) 1.12 3.2 1.42 3.4

breakdownfield

EB(106V/cm) 0.3 3.5 0.4 2

mobility

µ(cm2/V s) 1300 260 5000 1500

sat. velocity

vsat,n (107cm/s) 1 2 0.72 2

th. conductivity

RT H (W/mK) 130 350 46 170

diel. const.

εr11.9 9.66 12.5 9.5

lattice const.

a(˚

A) 5.4 D13.1 H25.6 C33.2 H2

c(˚

A)- 10.1 - 5.7

1Diamond 2Wurtzide

(hexagonal)

3Zinc blende

(cubic)

is nearly in the range of metal – hence why this

foreign substrate is an almost perfect heat splay.

FET

Within a field-effect transistor (FET) a current

flows along a semiconducting path described as

the channel, connecting the electrodes called drain

and source. The current along the channel is mod-

ulated via a biasing voltage at the gate electrode.

The FET can be either driven by an insolated gate

electrode (e.g. a pn junction) or a Schottky junc-

tion, where the last one represents a MesFET. In

addition, FETs are separated by being operated in

depletion (normally ON) or enhancement mode

(normally OFF).

GaN-HEMT

A high-electron-mobility transistor (HEMT) oper-

ates like any other MesFET. However, within an

HEMT there are at least two semiconductor lay-

ers with different bandgaps grown on each other,

building the epilayers which represent a hetero-

junction.

Chapter 2. Fundamentals

Vertical Transistor

The vertical architecture of an HEMT consists of

layers with different materials, chosen to build a

channel in which the electrons are physically sepa-

rated from their parent donors [Rob+01]. The free

electrons provided by the n-type dopant are lo-

cated in between an undoped space layer and the

channel layer close to the heterojunction, building

an almost two-dimensional section [Mar06]. This

two-dimensional electron gas (2DEG) is located

away from the lattice atoms, so it will not collude,

lowering the impurity scattering and therefore giv-

ing the free electrons higher mobility. Less collu-

sion within the channel decreases the noise figure

of HEMTs compared to MesFETs.

The current flows, within the HEMT, from the

ohmic contacts of the source to the ohmic con-

tacts of the drain via the high mobility channel, as

can be seen in the cross sectional view of Fig.2.5

taken from [Pen+12]. This current is determined

by the sheet electron concentration underneath

the Schottky gate contact. The concentration can

be modulated by the bias and in consequence the

Schottky contact. The heterojunction underneath

the gate represents a capacitor with its gate metal

and 2DEG building the plates. In between, the

spacer, donor, barrier and Cap layers form the di-

electrics of this capacitor. The Barrier layer should

isolate the channel from the gate and is typically

made of AlN. The aluminium concentration con-

trols the charge capacity of the channel. The re-

sulting capacitance remains almost constant while

changing the bias, as the dielectric separation is

fixed by the thickness of these top epilayers. In

conclusion, the current modulation in this HEMT

is controlled by adding or removing charge QCof

the 2DEG in response to the variations in voltage

Vat the Schottky contact using a simple capacitor

equation QC=C·V.

For high power applications the electrical field be-

tween the drain and the source is limited by the

breakdown-field EB. Nevertheless, the same elec-

trical field is applied towards the gate through the

epilayers which may lead to a gate breakdown.

Consequently, the gate is located with a higher

FIGURE 2.5: Cross sectional view of the GaN-HEMT

with additional field plate technique.

offset to the drain than to the source, which fur-

ther decreases the source resistance. The strongest

electric field is located at the drain edge of the

gate where the gate can provide free electrons to

fill surface states. This enhancement of the gate

behaves as a virtual gate which results in an ex-

tended depletion region and gate-source voltage

variations (gate-lag) [Vet+01]. Furthermore, these

field related states may be improved by a passiva-

tion layer (SiN) on top of the epilayers as well as

a special design of the tee gate using field-plates

(FP). They are designed to lower the field peaks to-

wards the gate but, as a result, introduce a higher

capacity, which lowers the fMAX of the HEMT. To

lower the effect of an increased gate capacity, a

second field plate (FP2) can be connected to the

source potential which is called double field plate

technology. By introducing the second field plate,

the drain-source capacity is increased, which is

only a fraction of the gate capacity.

Underneath the channel, a buffer layer is added as

a barrier to restrict the movement of the electrons.

This is made of GaN doped with carbon or iron.

Given the high electric fields between drain and

source, the electrons moving in the 2DEG channel

could be injected into the buffer. Hence the exten-

sion of the electric field from the channel towards

the substrate, results in a leakage current called

traps [Flo12, p. 20]. These injections represent

extremely long trapping time constants, because

these electrons are no longer part of the conduction

for the HF signal. Moreover, the trapped electrons

produce a negative charge which also depletes the

2DEG and in consequence reduces the channel

current that finally results in a current collapse.

To reduce this trapping, an improved lattice match-

ing is realised by a nucleation layer (AlN) that

Chapter 2. Fundamentals

FIGURE 2.6: Cross sectional view of the Nf=6 gate finger GaN-HEMT of Wolfspeed (CGHV1J006D).

should reduce the piezoelectric field in between

the buffer and the substrate. Trapping effects

based on the buffer substrate are commonly known

as Drain lag because they are mainly influencing

the output conductance. In addition, these buffer

traps can result in a gate lag which can be obtained

as a delay between the start of a rising voltage

slope at the gate and the current slope at the Drain.

This extends the gate area by the virtual gate to an

increased gate-Drain region leading to a decreased

2DEG density defined by an increase of the access

resistance.

The semi-insulating substrate is used as mechani-

cal and thermal support. A thickness of ≈4 mil is

historically related to older GaAs processes. The

different crystal lattice of the 4H-SiC to the GaN

creates dislocations that lead to long time constant

traps. As a result, both the buffer as well as the

substrate technology used by the manufacturer de-

termine the linearity of the GaN-HEMTs.

Horizontal Device

Among the vertical semiconductor structure al-

ready described, the device itself becomes horizon-

tal with the use of multiple parallel fingers 2. One

gate finger refers to a single vertical structure, as

shown in Fig.2.5. The gate length lgdepends on

the resolution of the manufacturing process and

limits the fMAX of the device (Fig.2.7). With an

increased width of the gate, the dc and RF current

of the device increases until the width becomes a

fraction of the wavelength, resulting in gate modu-

lation effects. To further increase the output power

of a GaN-HEMT, the vertical structure can be paral-

lelized to Nfx the intrinsic GaN-HEMTs as shown

in Fig.2.6 and Fig.2.7 with Nf=6 gate fingers. The

2As an alternative, the vertical device can be scaled by the so-

called fishbone layout which is typically not used in RF-design

due to the necessary air-bridges.

Gate

Drain

Gate width

Gate length

Gate fingers (6)

Drain fingers (3)

Via hole

FIGURE 2.7: Top view of the 6 gate finger GaN-HEMT.

total gate width Wtrepresents the sum of all indi-

vidual gate finger widths. For example, the gate

width of one finger shown in Fig.2.7 is 200µm, re-

sulting in a total gate width of Wt=1.2mm. In total,

any device has at least two gate fingers feeding

one drain finger.

The gate periphery represents the total size of the

device. The device’s parameter can be scaled with

the gate periphery as shown in Tab.2.4. The gate

fingers are interconnected to the pad via the gate

bus bar. The drain bus bar serves as an intercon-

nection for the drain fingers, while the intercon-

nection length needs to stay a fraction of the wave-

length, like with the gate width. Fig. 2.7 also visu-

alizes individual source vias (ISVs) which provide

very low inductance source interconnection to the

backside of the device. A special oval shape of

the via reduces the necessary source contact pad

size and therefore decreases the size of one intrin-

sic HEMT. In addition, ISVs are used to improve

the heat spray of the device.

GaN-HEMT model

The described vertical structure of a GaN-HEMT

can be analysed by the manufacturers based on

technology CAD tools (T-CAD3) where the field

densities can be obtained and improved. Design

aspects like the gate capacitance can be optimized

3Technology CAD Tools, e.g. ISETMor SilvacoTM

Chapter 2. Fundamentals

Gate

Source Drain

CPG

Cgd

Cgs

Rgd

Rgs

Rds

Cds

CPD

LSLGLD

intrinsic

Ids

Igd

Igs

FIGURE 2.8: Cross sectional view of the GaN-HEMT

with equivalent circuit elements.

through the structure of the gate (e.g. tee-gate

with field plate). Furthermore, charge currents

and therefore channel resistances can be calcu-

lated. These models solve the non-linear partial

differential equations (PDE) for the 2D vertical

structure. They can be extended to, for example,

the width of the gate to represent a horizontal de-

vice, resulting in physical based compact models

based on time-consuming simulations. Neverthe-

less, the complexity of the models means they are

not usable by circuit designers.

For this reason, compact models are used for the

purpose of circuit design and are summed up in

[Rud+11]. Within the following summary only a

short description of one compact model extraction

technique is given, described in [Gas12]:

Linear model extraction through S-parameters

The behaviour of a device is measured based on S-

Parameters and extracted to a small-signal model

as in [Kon86]. A small-signal equivalent circuit of

a GaN-HEMT is shown in Fig.2.8 and corresponds

to the vertical structure of the device. First of all,

the extrinsic components that represent pad or in-

terconnection inductances (LG,LS,LD), as well

as series resistance of the ohmic contacts (RG,RS,

RD) or pad capacitances (CP G,CP D), are deter-

mined because they are independent to biasing

conditions. Subsequently, the S-Parameter mea-

surements can be de-embedded to the intrinsic

reference plane and transformed into Y-Parameter.

Based on the given equations in [Aae+11, 207ff.]

the drain current (Id), conductance (gd) as well as

transconductance (gm) are determined depending

on the parasitic capacitances (Cgs,Cgd,Cds), the

Schottky resistances (Rgs,Rgd) and the channel re-

sistance (Rds). The intrinsic components represent

the voltage controlled current source of the chan-

nel and all intrinsic elements are optimized to fit to

the measurements. Nevertheless, this approxima-

tion only represents valuable data for the device’s

state of the initial S-Parameter measurements.

Non-linear model extraction with pulsed IV

The model needs to be extended by large-signal

measurements. Pulses are the favoured method

for characterising a power device while main-

taining a constant thermal state. Based on short

pulses, the thermal resistance of a device can be

determined while avoiding self-heating. During

longer pulses a current decrease occurs in the de-

vice which can be used to determine its thermal ca-

pacitance. Both influence the equivalent transistor

junction temperature (T) and result in a non-linear

current (Ids =f(Vds, Vgs, T)) a non-linear conduc-

tance as well as transconductance (∂gs =f(Vgs, T),

∂gd =f(Vgd, T)). The thermal analysis can be ex-

tended by IR-thermography of the device’s top

side in comparison to its T-CAD model.

Non-linear model extraction with pulsed IV/RF

The parasitic capacitances of a GaN-HEMT depend

on its terminal voltages, which itself depends on

the timing as well as the thermal state of the device.

Moreover, a non-linear gate voltage behaviour of

the GaN-HEMT affects the feedback capacitance,

which is why it needs to be modelled for synchro-

nised voltage currents and RF states (Cgs =f(Vgs),

Cgd =f(Vgd)). In contrast to common lateral FETs,

the dependency of Cds to Vds is negligible for the

on-state. Various pulse-widths are used to rep-

resent various time constants of the trapping ef-

fects. A separation between surface trapping (gate-

lag) and buffer trapping (drain-lag) can be done

by a series of measurements while influencing

Chapter 2. Fundamentals

TABLE 2.4: Parameters of GaN-HEMT scaling

parameter No. finger gate width

NfW

gmNfW

CGS,CDS NfW

fMAX - 1/W

fT- -

ZL,opt 1/Nf1/W

RD,RS1/Nf

RGRG(Wt

W)(Nft

Nf)2

Vgs,trap or Vds,trap resulting in a non-linear current

(Ids =f(Vds,trap, Vgs,trap, T )).

Load-Pull for Model Validation

Load-Pull measurements of the device can be used

to validate its model beyond the ideal 50Ωloads.

Nowadays, active Load-Pull measurements are ap-

plied during pulsed power conditions with vector

receivers. Therefore, the already obtained com-

pact model can be used to determine the optimal

input impedance of the DUT, always resulting in

true power gain conditions. This is important be-

cause of the non-linear input impedance with de-

pendency to the input power level. Nevertheless,

Load-Pull measurements are limited to frequency

or the device-size, as described in detail in Sec. 2.5.

Consequently, a model validation based on Load-

Pull measurements can only be applied towards a

certain size of the device.

Scaling

For power devices that exceed the number of fin-

gers by a huge parallelisation, modelling is done

by scaling smaller devices [Aae+11, 203ff.]. To

be more precise: – a compact behavioural model,

based on the described techniques, needs to be

up-scaled to the real device size with the gate pe-

riphery. All parasitic elements of one transistor are

in parallel, resulting in the total parasitic elements.

Tab. 2.4 sums up the scaling rules for direct or indi-

rect dependencies of the gate width or the number

of fingers.

GaN-HEMT losses

The conduction losses of the GaN-HEMT are mainly

determined by the Ron characteristics. In addi-

tion to these frequency independent losses, several

losses need to be summed up to represent the so-

called switching losses. First, the device parameters

influence the high frequency switching ability that

are the gate length (lg) and the channel mobility

(µ), where the last one depends on the tempera-

ture. That said, not only the device parameters but

also the gate drive current, the stray inductances

and especially the non-linear device parasitic ca-

pacitances leads to a high frequency limitation.

With an increased frequency the gain decreases

up to the frequency where unilateral stability is

achieved (fKNEE).

To further improve the efficiency of devices one

has to eliminate the surface traps (either in passi-

vation or epitaxial), the bulk traps (growth condi-

tion tuning) and of course decrease possible leak-

age (low dislocation density). With an increased

gate-periphery the PAE decreases by:

•the voltage drop along the gate width

•phase differences between the gate fingers

•thermal coupling between devices increases

its temperature which results in a negative

slope of dc-characteristics

2.3 Power Amplifier Theory

For the application of solid state power amplifiers

(SSPA) in the microwave field only n-channel de-

vices are used, based on their higher electron mo-

bility. All used FET devices of this work are biased

in a common-source topology taking advantage of

the high power ability. Within these transconduc-

tance amplifiers the input voltage modulates the

amount of current flowing through the FET. For

a direct current operation the output current (Idc)

can be set in relation to the input bias (VGS) by the

knowledge of the transconductance (mutual gain)

Chapter 2. Fundamentals

gmdc:

Idc =gmdc ·VGS gmdc =∂Idc

∂VGS VDS =const.

(2.4)

For an alternating current the same applies for the

dependence of the output current iDto the input

voltage vGS for a fixed drain voltage.

gm =∂iD

∂vGS VDS =const.

(2.5)

Amplifier Biasing Class

By using a commonly known Class-A amplifier,

100% of the input signal passes through the ampli-

fier which continues to conduct. The amount of

output current to the input voltage can be set in

relation to the period of a sinusoidal input signal

(0-360◦). The conduction angle Θis 360◦while

the output current is an exact representative of

the input voltage. As a drawback, the amplifier

needs to be biased to half the input voltage swing

to remain conductive for the negative half of the

sinusoidal signal. In conclusion, a permanent cur-

rent occurs which limits the theoretical efficiency

of the amplifier to η=50%.

By lowering the conduction angle the waveform

of the output current is cut by its lower half in

relation to the conduction angle (Θ< 360◦) and

the efficiency increases. With Θ= 180◦the ampli-

fier is said to be in Class-B only conducting half

of the applied signal. The range in between is

defined as a Class-AB amplifier (180◦<Θ<360◦).

By conducting less than half of the applied signal

(Θ<180◦) the amplifier is said to be working in

Class-C mode.

In the literature, most of the definitions regarding

these amplifier classes are related to its devices

turn-on behaviour located at Θ=180◦, whereas the

ideal threshold voltage VT H defines the beginning

of the conducting region [Bow+07, 150 ff.]. VT H is

highly related to the VDS (Eq. 2.5) and, in addition,

to the saturation or the previous state of the device.

Especially for the highly scaled GaN-HEMT tran-

sistor, the VT H cannot be easily determined based

on its extrinsic control voltage due to short-channel

effects and therefore varies with temperature.

Nowadays, there is a huge variety of additional

classes of operation that are worth mentioning in

detail. Their intention is to reduce the overlap of

the current and voltage-swing at the devices in-

trinsic current plane. In conclusion, the amount

of dissipated power is reduced and the efficiency

increases, which is shown in detail in [Cri06].

Small-Signal approximated Amplifiers

The non-linearity of the output current can, accord-

ing to [Col+09, 358 ff.], be defined by a 3rd order

power series of:

iD=Idc +gm ·vGS +gm2·v2

GS +gm3·v3

GS (2.6)

with the small-signal definitions of the higher or-

der partial derivatives:

gm2=∂2iD

∂vGS2VDS =const.

(2.7)

gm3=∂3iD

∂vGS3VDS =const.

(2.8)

Taking advantage of the addition theorem this

equation can be changed to:

dc :iD=Idc+(2.9)

f0:gm ·vGS ·cos(ωt)+ (2.10)

2·f0:gm2·v2

GS ·cos2(ωt)+ (2.11)

3·f0:gm3·v3

GS ·cos3(ωt)(2.12)

The frequency dependency of the higher order

derivatives can clearly be observed. According to

this separation, Cabal et al. defines the beginning

of the conduction (Θ=180◦) by the zero of the third

order derivative gm3(Eq.2.8) [Cab+04]. This def-

inition of cut-off voltage clarifies the uncertainty

of the previously defined varying VT H and can be

obtained in Fig.2.9 for a simulated GaN-HEMT.

By inserting a fundamental wave into this non-

linear circuit a number of harmonics are generated

(2 for this example). With an increased saturation

of this amplifier, the compression increases and

Chapter 2. Fundamentals

−3.2 −3−2.8 −2.6 −2.4 −2.2 −2−1.8 −1.6 −1.4 −1.2

−0.1

0.1

0.2

0.3

VGS (V)

gm (S), ID(A)

gm2

gm3

VTH

gmmax

ϴ > 180°

FIGURE 2.9: Simulated example of ac gm behaviour as a

function of VGS for a 250nm GaN-HEMT (CGHV1J006D;

VDS =40V; 1 GHz).

therefore the amount as well as the power of the

harmonics increases.

Large-Signal approximated Amplifiers

Nevertheless, this approach relies on a small-signal

assumption of the gm which cannot sufficiently

represent the large-signal (saturated) conditions

of the gate of an GaN-HEMT. According to Pedro

et al. the compression behaviour of the transistor

cannot be modelled by the small-signal expansion

of Eq.2.6 because this memoryless assumption

relies on an isolated FET [Ped+03, 340 ff.]. For

an increasing high vGS the non-linear boundary

effects increase which is why a self-biasing effect

occurs. The iDis no longer only a function of the

static VGS (dc), but rather than the amount of the

varying ac vGS which is indirectly declared in Pin.

vin(t) = VGS +vGS (t)(2.13)

The Taylor series expansion can be increased to a

higher order:

iD[vin(t)] = Idc +gm ·vGS(t) + gm2·vGS(t)2

+gm3·vGS(t)3+gm4·vGS (t)4+gm5·vGS (t)5

(2.14)

as well as the coefficients:

gmn=1

∂niD[vin]

∂vinn

vin =VGS;VDS =const.

(2.15)

Self-biasing effects are especially critical for a GaN-

HEMT driven into saturation. The gate-collapse in-

creases the self-biasing for high input power ratios.

By considering a large-signal compact modelled

GaN-HEMT the large-signal transconductance can

be calculated as defined in Eq.2.15 for various in-

put power levels. The device is therefore biased

with various VGS in a stable power match condi-

tion at a rather low operation frequency of 1GHz

– not producing parasitic resonances. The static dc

output current of this simulation driven at 1 GHz

can be seen in Fig.2.10(a). The input power value

of Pin =-30dBm represents a small-signal condi-

tion equal to the Fig.2.9. By applying an increased

input power level the device starts self-biasing. An

input power level of Pin =15dBm represents the

saturation of the device (Pout =6W). It can be ob-

tained that the VT H lowers extremely down to -6V

with an increase of input power.

According to the previously analysed amplifier

classes of operation, the beginning of a Class-B

operation located at Θ=180◦changes during the

modulation. As a consequence, the class of oper-

ation cannot be determined for the used amplifier

because it depends on the input power modulation

rather than only the static bias.

In addition, the gm changes drastically with a de-

crease, while the output power achieves its maxi-

mum Pout,f1. The influence of the static gate bias

to the output power level of the second harmonic

is displayed in Fig.2.10(e) indicating only a 20dBc

distance to Pout,f1for the saturation case.

The previously stated definition of a correct VT H

located at the zero of gm3still works for the in-

creased driving level, while in Fig. 2.10(f) this zero

can no longer be obtained because of a huge de-

crease in gm3. It can be noted that also the amount

of third harmonics (Fig.2.10(g)) only varies in a

range of ±5dBc for the saturation case – mainly in-

dependent of the static biasing conditions - while

for less input power its level significantly changes.

Large-Signal IMD in Amplifiers

Nowadays, multi-tone excitation is the common

operation mode for a power amplifier within the

data-communication segment. The spacing in be-

tween the carriers depends on the signal type. Two

Chapter 2. Fundamentals

−7−6−5−4−3−2−1

0.05

0.1

0.15

0.2

0.25

0.3

VGS (V)

ID(A)

Pin= −30 dBm

Pin= 0 dBm

Pin= 5 dBm

Pin= 15 dBm

VTH, 15 VTH, -30

VTH, 5

ϴ15 > 180°

ϴ5> 180°

ϴ-30 > 180°

(a)

−7−6−5−4−3−2−1

0.05

0.1

0.15

0.2

0.25

0.3

VGS (V)

gm1 (S)

(b) gm1

−7−6−5−4−3−2−1

−40

−20

VGS (V)

Pout, f1 (dBm)

−7−6−5−4−3−2−1

−0.1

−0.05

0.05

0.1

0.15

0.2

VGS (V)

gm2 (S)

(d) gm2

−7−6−5−4−3−2−1

−40

−20

VGS (V)

Pout, f2 (dBm)

(e) Pout,f2

−7−6−5−4−3−2−1

−0.1

−0.05

0.05

0.1

0.15

0.2

VGS (V)

gm3 (S)

(f) gm3

−7−6−5−4−3−2−1

−40

−20

VGS (V)

Pout, f3 (dBm)

(g) Pout,f3

FIGURE 2.10: Simulated example of ac large-signal gm

behaviour as a function of VGS and Pin for a 250nm

GaN-HEMT (CGHV1J006D; VDS =40V; 1 GHz).

carriers with its power (A1,A1) can be defined as

follows:

vGS(t) = A1·[cos(ω1t) + cos(ω2t)]

+A2·[cos(2 ·ω1t) + cos(2 ·ω2t)](2.16)

By the excitation of multiple generated frequencies

into the non-linear circuit, like in Eq. 2.9, the num-

ber of harmonics as well as their mixing products

increase. This is called intermodulation. The mix-

ing order defines the order of intermodulation dis-

tortion, for example, IMD3 or IMD5. Unlike har-

monics, the IMD products cannot be filtered be-

cause they are located too close to the carrier. The

power of the IMD3 and IMD5 products is highly

related to the higher order transconductances. The

fundamental output current can be defined by:

iD,f0=cos(ω1)·{gm ·A1+gm2·A1A2+

gm3·[9

4A13+ 3A1A22]} (2.17)

By skipping the amount of harmonics the impor-

tant IMD3 products can be defined as:

iD,IMD3=cos(2ω2−ω1)·{gm2·A1A2+

gm3·[3

4A13+3

2A1A22]} (2.18)

By observing that gm3strongly depends on the

chosen bias point, we can reduce the amount of

IMD3 by choosing the right bias conditions. The

minimum of IMD3 is referred as a sweet spot condi-

tion [Car+99]. This sweet spot, or the beginning of

aClass-B operation, can be assumed to determine

the biasing conditions with the lowest amount of

IMD3 products. Note that this assumption varies

with the change of VDS as well as the temperature

conditions of the device. In addition, it depends

on the input power conditions as already shown

in Fig.2.10(a).

The distance between one of the two-tone carriers

to its IMD3 product is the intermodulation distor-

tion IMD3. It can be analysed by the previously

used large-signal simulation of the 250nm GaN-

HEMT device with two carriers separated with

1MHz spacing around 1GHz.

Chapter 2. Fundamentals

15 20 25 30 35

Pout (dBm)

Gain (dB)

VGS= −2.3 V

VGS= −2.5 V

VGS= −2.8 V

VGS= −3 V

VGS= −3.5 V

(a)

−10 −5 0 5 10 15 20

−10

Pin (dBm)

Pout lower (dBm)

2·f0

3·f0

4·f0

(b)

15 20 25 30 35

Pout (dBm)

IMD3 lower (dBc)

sweet spotVGS= -3.5V

(c)

15 20 25 30 35

Pout (dBm)

IMD5 lower (dBc)

(d)

FIGURE 2.11: Simulated example of (a) two-tone gain (b)

harmonics (c) IMD3 (d) IMD5 for a 250nm GaN-HEMT

(CGHV1J006D; VDS =40V; 1 GHz; 1 MHz spacing).

The operation point with a max. gm for small-

signal conditions can be determined with VGS =-

2.3V which is equal to 100mA quiescent current.

This operation condition is the one most equal

to a Class-A operation representing the highest

gain (Fig.2.11(a)) and a low amount of IMD3

(Fig.2.11(c)), particularly for lower output power

levels. By decreasing the biasing VGS =-3 V, the

gain decreases in the back-off with the positive ef-

fect of lowering the soft-compression. In addition,

the IMD3 increases for the back-off, but decreases

towards saturation. This sweet spot behaviour can

be clearly observed for a VGS =-3.5V in Fig. 2.11(c)

while for its gain an expansion can be observed.

By considering higher order intermodulation prod-

ucts the IMD5 is shown in Fig.2.11(d). The biasing

conditions of VGS =3V display a compromise of a

constant 30dBc distance to its carriers.

The appearance of IMD3 or IMD5 related sweet

spots depends furthermore on the tone spacing,

the harmonic match as well as the selected base-

band impedance. For use with modulated signals,

special care must be taken so that the chosen sweet

spot of the IMD3 doesn’t produce a sensitivity of

the IMD5 that results in an unwanted increase of

those side-band products.

In theory, the extrapolated increase of the IMD3

products results in the third order intercept point

(OIP3), crossing the linear extrapolation of the

power increase. This assumption can be done for

small-signal gm analysis. However, the assump-

tion that the slope of this IMD3 increase is constant

cannot be observed in Fig.2.11 for large-signal ob-

servations. In conclusion, an OIP3 or OIP5 anal-

ysis is not useful for power-amplifiers operating

towards the Class-C biasing conditions.

Additional calculations and nomenclature regard-

ing amplifiers are provided in Appx.A.3.

2.4 SatCom Signals

SatCom signals rely on an amplitude and/or phase-

shift keying technique. From the beginning of Sat-

Com a simple QPSK modulation was used. For

use within broadcasting applications, DVB-S1 de-

fines the common modulation schemes to be BPSK,

QPSK, OQPSK and 8PSK with various forward

Chapter 2. Fundamentals

TABLE 2.5: PAPR (dB)of different modulation schemes

DVB-S2

DVB-S1

αBPSK QPSK 8PSK 16APSK 32APSK

0.35 4.1 3.9 3.8 4.8 6.2

0.25 5.1 4.9 4.7 5.7 6.8

error corrections (FEC). Beginning with the DVB-

S2 definitions, optional modulation schemes of

16APSK with up to 32APSK can be used, while a

backward compatibility is granted [ETS09]. In ad-

dition, the necessary SNR of the signals decreases

within DVB-S2 due to the improved coding. The

roll-off factor can also be reduced down to α=0.2

to improve further the spectral efficiency. The in-

creased PAPR is displayed in Tab.2.5.

(a) (b)

FIGURE 2.12: Constellation Diagram of modulation

schemes for DVB-S2 transmission (a) 8PSK (b) 16APSK.

An example for the constellation diagram of an

8PSK and a 16APSK is given in Fig.2.12. Note that

in comparison to QAM a lower number of possible

amplitude levels is achieved. It is therefore known

to be more robust.

DVB-S2x is planned to be described within the

newer ETSI definitions. It will extend the pre-

vious DVB-S2 regulation by the usage of up to

a 256APSK with smaller roll-off factors down to

α=0.05 for streaming UHDTV. The choice of mod-

ulation scheme is related to the signal to noise ratio

(SNR), which is achieved at the satellite receiver.

With the usage of DVB-S2 signals, various modula-

tion schemes can be analysed regarding their nec-

essary SNR. Depending on the bit error rate (BER),

the SNR is shown in Fig.2.13(a) with an FEC of

5/6. With the knowledge of the PAPR (given in

Tab. 2.5), the error vector magnitude (EVM) can be

calculated (Fig.2.13(b)). It can be obtained that the

robust QPSK tolerates a high EVM ≥50% while

higher order modulation schemes degrade fast.

0 2 4 6 8 10 12 14 16

10−6

10−5

10−4

10−3

10−2

10−1

100

BER

SNR (dB)

QPSK 5/6

8PSK 5/6

16APSK 5/6

32APSK 5/6

(a)

0 10 20 30 40 50 60 70 80 90 100

10−6

10−5

10−4

10−3

10−2

10−1

100

BER

EVM (%)

QPSK 5/6

8PSK 5/6

16APSK 5/6

32APSK 5/6

(b)

0 2 4 6 8 10 12 14 16

SNR (dB)

Shannon limit

Spectral Eﬃciency (bit/s/Hz)

QPSK 1/2

QPSK 5/6

8PSK 5/6

16APSK 5/6

32APSK 5/6

(c)

FIGURE 2.13: Theoretical analysis of (a) BER vs. SNR

(b) BER vs. EVM for various modulation scheme (DVB-

S2; α=0.25) (c) Spectral Efficiency vs. SNR (DVB-S2;

B=6MHz; α=0.25; BER=10−6).

For an equivalent thermal noise power of N0=-174

dBm/Hz the various modulation schemes can be

obtained close to the Shannon-limit in Fig.2.13(c)

at BER=10−6.

Chapter 2. Fundamentals

2.5 Measurement Techniques

Microwave measurements are distinguished into

small-signal and large-signal measurements. A de-

tailed description of all measurement techniques

can be observed in [Dun12] while in the following

subsections only a brief introduction to the used

techniques is given.

Small-Signal Measurements

Small-signal measurements represent the situation

where all measured components are situated far

away from their saturation. Vector Network Anal-

yser (VNA) are commonly used to proceed this by

measuring the forward (ai) and reflected (bi) wave

quantities (Appx.A.6). Depending on the VNA the

number of measurement ports (i) varies while the

transmission and reflection from each port to each

other port can be displayed through the use of the

S-Parameters (Appx.A.13).

The analysis of the wave-quantities relies on the

detected voltage that itself depends on the refer-

ence plane where this voltage takes place. On

account of these reference plane dependent wave

quantities, calibration techniques are used, to shift

the reference plane along the measurement setup.

The General Short Open Load Thru-procedure

(GSOLT) is probably the most common calibration

technique relying on well-defined calibration stan-

dards [Heu03]. After measuring these standards,

its parasitic (known) behaviour is subtracted from

the measurement results. With the knowledge of

all measured standards and the measured device

under test (DUT) the S-Parameters of the DUT at

the defined reference planes (e.g. connector) can

be extracted.

An additional second tier calibration can shift the

reference plane along the measurement setup di-

rectly on the DUT substrate. Hence calibration

standards can be manufactured directly on the

substrate through the use of the Thru Reflect Line-

procedure (TRL) [Eng+79]. This technique can

take advantage of using no resistive match, which

Pad DUT

GSG

Probe

GSG

Probe

Pad

Substrate

Cable Cable

Probe-Station

Port 1 Port 2

TRL Cal.

GSOLT On-Wafer Cal.

GSOLT Coax Cal.

FIGURE 2.14: Definition of the reference planes used

within a probed measurement setup.

comes along with parasitics, but a TL with its de-

fined characteristic impedance. This technique is

especially useful for probed measurements, where

ground signal ground (GSG) probes are necessary.

The outer contact (ground) of the probe connects

to the substrate ground via the GSG pad. The in-

ner contact (signal) serves as connection to the TL

located on the substrate.

Fig.2.14 visualizes the separation of the various

calibration techniques related to a probed measure-

ment setup. The increased number of connections

from the port of the VNA to the DUT raises the

sources of error considering a loose connection,

phase instabilities or mismatch reflection. In view

of the fact that these sources of error are difficult

to obtain, a second-tier calibration TRL (e.g. on the

DUT substrate) after an already proceeded GSOLT

(e.g. On-Wafer calibration) makes sense. By con-

trast, each calibration technique can be used stand-

alone as well. A detailed analysis of the frequency

dependent uncertainties, caused by this measure-

ment setup, is given in Appx. A.5 and is related

to the Metas VNA-ToolsTMuncertainty calculation

[Wol+12].

De-embedding

A de-embedding of a connector or a probe-pad can

be realised by a TRL calibration directly within

the VNA or in MATLABTM. The combination of

the measured Thru, a Reflection and a Line is suf-

ficient for obtaining the feeding structure of the

probe-pad. A transformation from the derived

S-Parameter Matrixes (Stot) into a T-Parameter

structure [Ttot](Appx. A.12) displays a sequence

of multiplications, representing the series setup

Chapter 2. Fundamentals

(Pad - DUT - Pad).

[Stot]⇒[Ttot]=[TP ad]·[TDUT ]·[TP ad]−1(2.19)

According to the techniques defined in [Eng+79]

any pad structure can be de-embedded with the re-

maining TDUT that can be converted to the SDUT .

This principle is applied throughout this work. It

is especially useful for shifting the reference plane

from a coaxial to a WG reference plane.

Large-Signal Measurements

By considering large-signal conditions, in which

measured components are situated towards their

compression, the voltage level needed to be de-

tected increases. Particularly with the use of PAs,

a high amount of voltage and current swing needs

to be detected. Hence power detectors measure the

incoming and outgoing scalar power of the DUT.

A power measurement needs to be distinguished

into true RMS measurements related to the usage

of thermocouple or thermistor detectors and the

use of peak power meters, detecting the voltage.

For the case of distortion free CW signals, both

types of power meters deliver an equivalent value.

Since the diode voltage detectors are calibrated

by using the known relationship between RMS

and peak voltage (PAPR), they cannot be used

for AM and SSB (two tone) signals. Furthermore,

harmonic distortion will cause unpredictable re-

sults, while a distance of ≥50dBc can be toler-

ated. During a calibration of the power-head, the

power reference is certified with an uncertainty

PREF,unc =±0.6%, while the instrument itself adds

up to PREF,inst =±0.5%. The main cause of mea-

surement errors in power measurements is still the

uncertainty of the power meter, while an attached

source is connected within mismatch conditions

here defined as PPM,unc .

To achieve an appropriate power level at the power

head, the input as well as output power of a DUT

is extracted from the measurement setup via di-

rectional couplers (dc, shown in Fig.2.15). By

considering the various matching levels at all the

pre

amp

RFin RFout

load

Power-Meter spec

DUT

Source

RFin RFout

Γin Γout

FIGURE 2.15: Schematic view of the large-signal mea-

surement setup.

reference planes within the large-signal measure-

ment setup, the total measurement uncertainty

can be calculated. The RL, IL and directivity of

the coupler needs to be considered for a measure-

ment setup regarding a low measurement uncer-

tainty. For the use of a DUT with a low amount of

matching, the isolation of the coupler becomes the

most relevant value. To prevent failures related

to the mismatch uncertainty, the power that was

measured for the PAs of this work was obtained

through high directivity WG-couplers at the input

and output, respectively.

By the knowledge of the coupling (in: 30 dB, out:

40dB), matching (20dB) and isolation (60dB) of

the couplers, the measurement uncertainty of this

net-power can be calculated as in [Che+05]. By

assuming that all interconnections are matched to

≥20dB with a random phase, the only mismatch

is inserted by the DUT at the input (Γin) as well

as the output side (Γout). The obtained standard

deviations (Pin, unc, Pout, unc) is shown in Tab.2.6 for

both measurement positions (RFin, RFout). With a

decrease of the RL down to only 10dB the devi-

ation increases up to Pin, unc =0.23 dB at the input

and up to Pout, unc = 0.34 dB. Its statistical distribu-

tions are visualized in Appx.A.5.

TABLE 2.6: Power measurement uncertainty related to

mismatch conditions

VSWR 1 1.05 1.1 1.22 1.5 1.92

RL (dB) ∞30 25 20 14 10

PPM,unc (%) 0 0.1 0.25 1 4 10

Pin, unc (dB) 0.01 0.02 0.05 0.07 0.14 0.23

Pout, unc (dB) 0.01 0.02 0.05 0.12 0.31 0.34

Chapter 2. Fundamentals

Load-Pull Measurements

Load-Pull is originally a technique that is able to

measure performance values of a transistor while

constantly changing source and load impedances.

The DUT is therefore located within a test-bench

that ideally does not provide any matching to the

transistor, only the biasing. This test-bench needs

to provide as low losses as possible to realise a high

reflection coefficient on the transistors in and out-

put plane (Γ∗

in,Γ∗

out). Load-Pull tuners are realised

based on low loss coaxial airlines, equipped with

two motorized sliding open stubs. The open stubs

and the airline in between both build a π-network.

Due to well-chosen electrical lengths of the stubs as

well as the airlines, this Load-Pull tuner is able to

realise any arbitrary impedance among the Smith

Chart at the coaxial reference plane. During a cal-

ibration a certain amount of arbitrary impedances

can be positioned and measured with a VNA. By

each of these, the frequency dependent insertion

loss as well as return-loss is now saved within a

software that can later compute the forward and

reflected power to the DUT.

The outer area of the Smith Chart, which repre-

sents the highest reflection coefficient Γ, can only

be reached by extremely low loss Load-Pull tuners

due to the limited quality factor of the open stubs.

In addition, the amount of power that a Load-Pull

tuner is able to withstand is limited by its inher-

ent losses. This is why it changes its electrical

behaviour within high power applications, which

increases the measurement uncertainty while mea-

suring. The larger the transistor representing the

DUT, the lower its optimal impedances are. For

this reason it is increasingly difficult to provide

the high reflection coefficients to the transistors

reference plane. Additionally, the already limited

tuner-plane

transistor-plane

Zload Ztuner

RFin RFout

Z0 = 50Ω

load-tuner

source-tuner

pre-match

FIGURE 2.16: Illustration of the pre-transformed Load-

Pull setup.

amount of Γthat is realised on the coaxial reference

plane is further reduced by the pre-transformation

and the losses of the test-bench. By choosing a

well-known transformation network (pre-match)

within the test-bench, it is possible to transform

the discrete amount of Γat the coaxial tuner plane

to an area located more at the edge of the Smith

Chart boundaries for the transistor-plane which is

shown in [Maa+13] (Fig.2.16). The technique used

was able to improve the low-ohmic impedance ac-

curacy for a packaged 50W GaN-HEMT transistor

at 2.45GHz.

With an increased frequency towards the Ku-band,

the inherent losses of the tuner as well as the test-

bench will increase extremely. Hence the possible

amount of Γthat can be provided to the transis-

tors plane decreases further. Additionally, mount-

ing and bonding tolerances increase to the biggest

amount of uncertainty within the Load-Pull setup.

Consequently, higher frequencies transistors were

directly measured on its wafer with a probed Load-

Pull setup that is either active or passive. However,

the size of the transistors are limited by the pitch of

the probes and its power capability, while a higher

pitch of a (GSG)-probe lowers its upper frequency

limit, as shown in Appx.A.1.

3 Power Amplifier

This chapter will describe the design, analysis and

characterization of Ku-band power amplifiers. Ini-

tially, a commercially available GaAs MMIC PA

was combined to achieve matching as well as a suf-

ficiently high output power described in Sec.3.1.

It relied on a simple branch-line combining and

was used as a measurement amplifier as well as

for preliminary tests. The design had been previ-

ously published in combination with a linearisa-

tion setup in [Maa+15a].

In the following sections a design procedure for

GaN-HEMT MIC PAs is given following the flow

chart of Fig.3.1, which starts with a detailed pro-

cess description. The transistor technology and its

model are analysed in Sec.3.2. Optimum input-

output-impedances are found based on Load-Pull

simulations as well as theoretical assumptions.

These classical Load-Pull simulations are extended

to a new multi-frequency Load-Pull analysis tech-

nique.

The manufacturing of matching circuits leads to

certain parasitics that are analysed in correlation

with the device in Sec.3.2.1. Taking into account

the bandwidth, power and efficiency, ideal match-

ing limits are addressed as well. Finally, Load-Pull

related aspects concerning the linearity as well as

harmonic matching are analysed.

The first GaN-HEMT PA design is described in

Sec.3.3 which will fulfil the recommendations of

SatCom uplink PAs in the frequency range be-

tween 13.75-14.5GHz (Fup) while it is already

Transistor

ideal

matching

limits

simulation

Load-Pull

analysis measurements

matching

circuits

FIGURE 3.1: Flow chart of the PA design procedure.

published in parts [Maa+17a]. The explanation

includes the design steps of the matching circuits,

the simulation approach as well as the necessary

measurement techniques.

To prove the methodology another design was

proposed which should fulfil a lowered frequency

range from 12.5-13.5GHz (Flow) with a slightly

higher FBW and is described in Sec.3.4.

In addition one design was developed to provide

a sufficient uplink power within both frequency

ranges extending the previous designs to 12.75-

14.5GHz (Fext) (Sec. 3.5).

Finally, these amplifiers are analysed on their po-

tential to further improve its efficiency based on

efficiency enhancement techniques, like envelope

tracking or Doherty, in Sec.3.6.

A discussion compares the developed amplifiers to

previous state of the art work that can be either a

MMIC or a MIC (Sec.3.7).

Chapter 3. Power Amplifier

3.1 Combined MMIC PA

Within this design a high gain 0.25 µm gate GaAs

p-HEMT technology was chosen to focus on a mea-

surement pre-amplifier. The small signal gain of

one packaged chip is approx. 25dB and lowers to

less than 20dB in saturation. The PAE of one chip

in the 1dB compression is ≈18%.

To increase the output power of this commercially

available packaged amplifier, and therefore get

enough drive level for our own developments,

a two stage branch-line combining on a 228µm

RO4003c substrate with an εr=3.55 was chosen.

The losses in these high frequencies cause the

branch-line combiner not to be flat over the upper

Ku-band bandwidth (13.75-14.5GHz). The com-

biner is therefore capacitively loaded at the 50Ω

port side with a high Q and high SRF Capacitance

(ACCUP 0.1pF). This technique compensates for

the losses to higher frequencies (Fig.3.2).

The bias point needs to be chosen in a Class-A

range to overcome poor gain as well as low lin-

earity in the Ku-band. This of course results in a

low PAE and a higher power consumption. An

expansion in the modulation standard with an in-

creased PAPR drives the amplifier even more in

the back-off operation.

The final small signal gain of the two stage design

is higher than 22dB from 13.5GHz to 16.2 GHz

for a supply voltage of VDS=8.5 V and IDQ=4A qui-

escent current. The PA has an output power of

Pout,1dB=9 W with a moderate PAE of 16% around

14GHz. The PAE drops to approx.12% when

FIGURE 3.2: PA schematic with two packaged GaAs

p-HEMT transistors combined via capacitive loaded

branch-line combiner.

60 mm

45 mm

FIGURE 3.3: Picture of the PA with two packaged GaAs

p-HEMT transistor combined via capacitive loaded

branch-line combiner.

FIGURE 3.4: Large-signal measured output power, PAE

and gain at different frequencies within the band for the

1dB compression point; VDS =8.5V; Idq=4 A.

taking the complete frequency range into consider-

ation (Fig.3.4).

This low PAE results from both the combining

losses and the Class-A biasing as well (Fig.3.4).

Nevertheless, the sufficiently high gain paired

with the high drive level makes this amplifier an

attractive low-cost laboratory amplifier. The use

of the branch-line combining makes it withstand

possible mismatch conditions based on a fault mea-

surement setup or a DUT that is used behind this

pre-amplifier.

Chapter 3. Power Amplifier

3.2 250 nm GaN-HEMT Analysis

Based on the Wolfspeed 250 nm GaN-HEMT pro-

cess, there are several bare die sizes available. The

smallest represents a bare die, as shown in Fig.2.7,

with Nft=6 gate fingers giving a total gate width

Wt=1.2mm (CGHV1J006D) that should hereby

be defined as one transistor cell. In addition, an-

other bare die with Nft=4x6 fingers resulting in

a total gate width Wt=4.8mm (CGHV1J025D) is

available. Its layout represents exactly 4 times

the CGHV1J006D (one transistor cell) with a sim-

ple interconnection of the drain bus bar while still

keeping individual drain pads. To suppress odd-

mode instabilities, each transistor cell is separated

at the gate bus bar with Rodd=200 Ωgate stability

resistors (Fig.3.5). The bare die CGHV1J070D with

a further increased Nft=12x6 number of fingers

ends up with Wt=14.4mm total gate width (12x

transistor cell) and is shown in Fig.3.6.

The specifications resulting for the different bare

die sizes are summed up in Tab.3.1 while the satu-

rated power represents a typical value of 5W/mm

gate width for a modern 250nm GaN-HEMT pro-

cess.

Based on the double field plate technique the

break-down voltage of the device is very high,

defined with VBD ≥100 V. A pinch off with Vp-off

= -3.1V demonstrates the normally-on character-

istics of GaN-HEMTs. The max. ac - transcon-

ductance is gm≈580mS/mm for VGS =-2.65V at

14GHz. The parasitic capacitances are CGS =1.6 pF,

CDS = 0.29 pF and CGD = 0.41 pF per mm gate width

[Wol12].

To obtain a high output power of Pout ≈50 W the

largest device CGHV1J070D was chosen. It is spec-

ified with a Pout,sat =70W and an ID,max =7A for

a size of 4.8mmx0.8mm. Especially the high to-

tal in- and output capacitances of CGS =24pF and

CDS =4.2pF make the matching towards high fre-

quencies very challenging. Note that based on

the diel. parameters given in Tab. 2.1 the elec-

trical length is λ

4=2.3mm at 14GHz on the SiC

substrate. Therefore, the width of the SiC semicon-

ducting area (Mesa) of this large bare die exceeds

Gate

Drain

Gate

Drain

Gate

Drain

Gate

Drain

Gate stability resistors (3)

Drain bus bar interconnection

FIGURE 3.5: Top view of the Nft=4x6 gate finger GaN-

HEMT of Wolfspeed (CGHV1J025D) representing 4 tran-

sistor cells.

TABLE 3.1: Specifications of the 250 nm GaN-HEMTs

process at10 GHz.

Nft=6 Nft=4x6 Nf t=12x6

Wt1.2mm 4.8mm 14.4mm

Pout,sat (VDD=40 V) 6W 25 W 70W

ID,sat (VDS=6 V) 1.1 A 4.3 A 13A

ηmax (IDQ=5% ID,sat)60% 60% 60%

GSS (IDQ=5% ID,sat) 17dB 17dB 17dB

CGS (VGS=-8 V) 2pF 8pF 24 pF

CDS (VDS=40 V) 0.35pF 1.4pF 4.2 pF

CGD (f=1MHz) 0.5pF 0.2pF 0.6 pF

VBD (VGS =-8V) 100V 100V 100V

IG,max (VGS =2V) 2.1 mA 4.8 mA 14.4mA

R∆max, JC 25K/W 3.6K/W 1.1K/W

aλ

4dimension for 14GHz (Fig.3.6). Given that the

second harmonic frequency is located at 28GHz,

the die itself already has a width ≥3

4λ2·f0. The

R∆max, JC defines the maximum thermal resistance

of the bare die bottom to the case, not exceeding

the thermal limitations of the channel which drops

towards the largest bare die.

3.2.1 Manufacturing Limitations

Mounting

The source contact of the bare die acts as intercon-

nection to the GND potential of a matching circuit.

Furthermore, it is the connection to the heat sink.

The mounting of the bare die therefore needs to

be low ohmic for matching requirements and of a

minimum thermal resistance. In this work an eu-

tectic die-attach compromises between a thin AuSn

preform (20 µm) and a low amount of trapped air

in the die-attach. In order to allow a controlled

thermal expansion, the bare die was mounted on

Chapter 3. Power Amplifier

Gate

Drain

Gate

Drain

Gate

Drain

Gate

Drain

Gate

Drain

Gate

Drain

λ/4 at 14 GHz

λ/4 at 28 GHz

bare die

matching substrate

Ddie

Dgap

Pad

Dpad

gap 1 bond 2 bonds 3 bonds 1 ribbon 2 ribbons

FIGURE 3.6: Top view of the Nft=12x6 gate finger GaN-HEMT of Wolfspeed (CGHV1J070D) representing 12 tran-

sistor cells.

CuMoCu

Air SiC

AuSn

12 transistor cells

(a)

(b)

FIGURE 3.7: (a) Sideview of FEM simulated mounting

heat flow density of 100W dissipated power (b) Top

view of the 3-D EM simulation with 24 bond wires.

a 1.5mm thick CuMoCu flange. Thermal simu-

lations are based on the assumptions of [Pre+09]

and show that the resulting thermal resistance of

the junction to case is R∆JC =1.6◦K/W. The ther-

mal conductivity was adaptively varied for GaN

in relation to an increased channel temperature. By

considering a PAE of 45%, a significant amount of

dissipated power needs to be removed via the cool-

ing system. In reality, the PAE will be even lower

due to impedance mismatches and losses of the

load transformation networks. X-Ray pictures of

the mounting are finally taken to count the amount

of trapped air within the soldering. The channel

temperature of the device can be monitored with

the model and needs to stay below 320◦C, while

a higher temperature will cause the device to fail.

The theoretical possible cooling therefore limits the

dissipated power to Pdiss,max ≈86.4W. This possi-

ble cooling will be further degraded via a thermal

coupling of other heat dissipating components.

Bonding

Twelve gate and twelve drain pads needed to be

interconnected to the matching circuit. Thus, an

array of 24 bond wires was 3-D modelled and ap-

plied at the input and output respectively with two

parallel wires per pad. The resulting total equiva-

lent inductance is LBond =12.5pH including the mu-

tual coupling. This value is of certain tolerance

considering the bondheight, loop and distance. To

increase the height and loop accuracy, automatic

bonding is useful. It can achieve impressive results

even for the aim of coupling between bond wires

[CC+11].

However, the bond distance is mainly dependent

on the mounting accuracy Dgap=60±30 µm as can

be seen in Fig.3.6.Ddie is initially 177µm with the

size tolerances of the bare die itself (−50 µm), set

in relation to the total size of the die (800 µm), the

tolerances are going to be defined as (−12 µm). In

addition, the distance from the metallisation of the

TABLE 3.2: Bonding tolerances

value tol. max; min

distance (µm) (µm) (µm)

Ddie 177 -12 177; 165

Dgap 60 ±30 90; 30

Dpad 40 ±30 70; 10

Dtotal 277 +60; -72 340; 203

inductance (pH) (pH) (pH)

L2bonds 139 +30; -36 169; 103

L24bonds 11.6 +2.5; -3 8.6; 14.1

L3bonds 92 +20; -24 68; 112

L36bonds 7.6 +1.6; -2 9.2; 5.6

inductance EM (pH) (pH) (pH)

L2bonds 150 +50; -50.4 200; 99.6

L24bonds 12.5 +4.1; -4.2 8.3; 16.6

Chapter 3. Power Amplifier

matching substrate to the gap needs to be consid-

ered with Dpad=40±30 µm. These tolerances can

be summed up to a total distance between the pad

on the die and the pad on the matching substrate

as shown in Tab.3.2. With a simple approach of

choosing 2 bond wires per pad and the rule of

thumb that 100µm bond wire results in 100pH in-

ductance, we get the values of L2bonds for one pad

interconnection. All 12 pad interconnection reduce

the inductance to L24bonds ≈11.6±60 pH.

The EM-simulations have shown that the variabil-

ity of the total equivalent inductance is in the range

of LBond ={8.3pH...16.6pH}for the worst case sce-

nario. In reality, the tolerances can be reduced by

measuring the alignment accuracy and therefore

calculating the optimal bond wire distance and

loop respectively. This would reduce a possible

frequency shift of the matching circuits that is re-

lated to the inductive pre-transformation.

3.2.2 Optimum Impedances

The optimum load-line resistance that represents

the intrinsic current source (for Class A) can be cal-

culated [Cri06] as:

Rdc ˆ= Zoint =VDS,OP −Vknee

0.5·Imax =37 V

3.5A= 10.5 Ω

(3.1)

The additional intrinsic capacitance CDS as well as

the pad and interconnection inductance transform

the real Zoint to the optimum load impedances

Zoext. By considering a power match condition,

the impedances looking into the matching circuit

need to be Z∗

oext (Fig.3.8). This simple approach

represents a very good approximation to the sim-

ulated optimum source and load impedances that

are discussed later on and stated in Tab.3.3.

3.2.3 Ideal Matching Limits

The impedances of the bare die itself can be anal-

ysed based on the Bode Fano limits [Fan50]. By

using the simple transistor-schematic from Fig.3.8,

an equivalent impedance Z′

1(s)of the L, C, R for

the input as well as for the output can be stated and

FIGURE 3.8: De-embedding from the intrinsic dc impe-

dance to the optimum load impedance.

analysed towards a maximum achievable band-

width as in [Pre+13].

Z′

1(s) = sL +r

s2LC +srC +R(3.2)

A possible ideal matching circuit can be approxi-

mated by a Taylor series in the following form:

F(s) = ln1

ρ=jA0+A1

s+A3

s3+··· (3.3)

with s=σ+jω (3.4)

Transforming the impedance to an admittance,

building the logarithm and negation, leads to:

ln1

ρ=ln 



−

s2(R+r) + 1

s(L+rC) + LC

s2(R−r)−1

s(L−rC) + LC 





(3.5)

For 1

s= 0 follows:

jA0=jπ, (3.6)

A1=2

Cand (3.7)

A3=2(L−3C)

3LC3(3.8)

After Fano et al. [Fan50] an equivalent circuit with

two zeros has to fulfil the following two integrals

Chapter 3. Power Amplifier

at s=∞:

∫∞

ln1

ρdω =π

2ÄA1−2∑λriä(3.9)

∫∞

ω2ln1

ρdω =−π

2ÅA3−2

3∑λ3

riã(3.10)

Defining K=2

πln1

ρ, a centre frequency ω0, and the

bandwidth ba substitution of:

ω1=ω0(1 −b

2)(3.11)

ω2=ω0(1 + b

2)(3.12)

leads to the expression

K(ω3

2−ω3

1)+ 3A3−1

4[A1−K(ω2−ω1)]3= 0.

(3.13)

An insertion of A1and A3from the Taylor series

of (3.13) and replacing ω0Lwith XLand ω0Cwith

BCleads to the equation:

K3−6

K2+ [12

b2Å1 + 1

cã]K−24

b3XLB2

= 0

(3.14)

This equation can be analysed in Matlab TM for

the input Zin{Rin;CGS;Lpad}as well as the output

Zout{Rdc;CDS;Lpad}of the device. As a result, the

theoretically relative matching, which is a func-

tion of the bandwidth, was obtained. The parasitic

inductances become dominant for higher frequen-

cies. The possible FBW, which can be theoretically

matched, therefore depends on the operation fre-

quency. Given that a moderate bond wire distance

results in LBond ={12.5pH}the dependency of rel-

ative matching to the achievable FBW can be seen

in Fig.3.9(a) for various centre frequencies.

Given that a relative matching of 10dB will be suffi-

cient, the analysed device can be easily matched to

a FBW of 80% for a centre frequency of 2GHz for

the input (Fig.3.9(a) (top)). The output at 2GHz

is far easier to match to a FBW ≥150% because of

its lower parasitic capacitance CDS compared to the

input capacitance CGS. Furthermore, the Fig.3.9(a)

shows that for an operation frequency of 5GHz

only 20% FBW can be achieved on the input-side.

Therefore, the input capacitance of CGS =24pF is

0 20 40 60 80 100 120

−25

−20

−15

−10

−5

FBW (%) for the Input

rel. matching (dB)

2 GHz

5 GHz

10 GHz

14 GHz

20 GHz

0 20 40 60 80 100 120

−25

−20

−15

−10

−5

FBW (%) for the Output

rel. matching (dB)

2 GHz

5 GHz

10 GHz

14 GHz

20 GHz

(a)

(b)

FIGURE 3.9: Analysed theoretical matching limit (Bode

Fano) of the complex Zin{Rin;CGS;Lpad}(top) and

Zout{Rdc;CDS;Lpad}(bottom) impedances for (a) various

centre frequencies (b) for f0at 14GHz.

clearly the limiting factor towards higher frequen-

cies.

The theoretically possible relative matching can be

seen in Fig.3.9(b) on the bare die reference plane

itself, as well as with possible LBond inductances

for a centre frequency of 14GHz. The values of

LBond ={8.3pH; 12.5pH; 16.6pH}therefore cor-

respond to the variability of bond wires defined

in section3.3.2. Even by considering a relatively

poor matching of only 10dB, the input achieves

less than 2.5% FBW around f0. This is mainly

due to the extremely low Rin = 0.2 Ω with the high

CGS=24 pF.

This relative matching only represents the trans-

formation from the optimum source impedance to

Chapter 3. Power Amplifier

−3.5 −2.5 −1.5 −0.5

0.3

VGS (V)

gm (S), ID(A)

50 mA

150 mA

300 mA

(a)

−3.5 −2.5 −1.5 −0.5

−8

−6

−4

−2

VGS (V)

gm2, gm3(S)

gm2

gm3

14 GHz

1 GHz

(b)

Frequency

MAX or MSG / MAG (dB)

1 MHz 1 GHz 10 GHz 40 GHz

0.5

1.5

K−factor

MAX50 mA

MAX300 mA

K50 mA

K300 mA

fKNEE

(c)

FIGURE 3.10: Simulated (a) ac transconductance gm, ID

(b) 2nd and 3rd derivative of conductance for 14GHz and

50Ω. However, the Source-Pull contours, based

on the Source-Pull simulation, shows that a devia-

tion from these optimum values can be tolerated.

The output is, considering its higher values of

Rdc = 10.5 Ω with the high CDS =4.2pF, easier to

match to at least 8% FBW w/o the bond induc-

tances. Within this analysis neither the feedback

capacitance CGD nor a possible housing or pack-

age capacitance Cpack is included. A housing ca-

pacitance would further increase the CGS or CDS

because it is parallel. This means the package ca-

pacitance always lowers the theoretically possible

relative matching. By contrast, CGD acts as series

capacitance in between CGS and CDS. Its parasitic

character therefore mainly resonates with the par-

asitic inductances of Lpad and Lbond. This feedback

results in a lowered gain of the device - which cor-

responds to a higher Rdc. In addition to the already

used equivalent circuit, the CGD can be taken into

account, which will result in a lowered achievable

bandwidth for frequencies up to unconditional

stability (fKNEE).

0 10 20 30 40 50 60 70

VDS (V)

C (pF)

CGS

CDS

CGD

(a) 1 MHz

0 10 20 30 40 50 60 70

VDS (V)

C (pF)

CGS

CDS

CGD

(b) 10 GHz

FIGURE 3.11: Simulated parasitic capacitances of the Die

for (VGS =-8V) and (a) 1MHz (b) 10GHz.

3.2.4 Device Model

A large-signal device model has been supplied by

the manufacturer including non-linear behaviour

as well as self-heating. A detailed description

of the modelling techniques used by the manu-

facturer is given in [Pen+12]. The device shows

an extremely non-linear ac transconductance be-

haviour at 14GHz (Fig.3.10(a)). The strong de-

crease of gm after its maximum is related to the

high operation frequency and maybe the outcome

of the HEMTs so-called parasitic MESFET effect

[Gol91]. In addition, the second and third deriva-

tives of the conductance visualize the switching be-

haviour over VGS (Fig.3.10(b)). Small-signal anal-

ysis shows that the device gets unconditionally

stable above 12.5GHz (Fig.3.10(c)). Therefore, the

possible gain at an operation frequency of 14GHz

is already decreased to 9dB and degrades further

with 20dB/decade beginning from the knee fre-

quency (fKNEE at K=1). For the drain current of a

maximum gm (Fig.3.10(a)) the extrinsic transit fre-

quency is fT=40GHz with a maximum oscillation

frequency of fMAX =48GHz.

The parasitic capacitances of the transistor can be

analysed and they visualize a low VDS dependency

of CDS in Fig.3.11(a). In addition, it clarifies the

dominance of the input capacitance CGS with a

non-linear feedback capacitance CGD. For higher

frequencies than 1MHz the de-embedding of the

parasitic capacitances does not represent only the

capacitances but also the resonances of the com-

plex parallel structure (Fig.3.11(b)). It can be noted

Chapter 3. Power Amplifier

TABLE 3.3: Simulated optimum source and load impe-

dances (VDS =40V; IDq = 0.3 A)

fPout PAE ZS,opt ZL,opt

(GHz) (dBm) (%) (Ω) (Ω)

13.0 48.34 48.1 0.25 - j0.08 0.47 + j1.91

13.5 48.39 47.4 0.16 - j0.09 0.48 + j1.82

14.0 48.21 46.0 0.15 - j0.19 0.42 + j1.73

14.5 48.21 44.8 0.15 - j0.21 0.41 + j1.64

15.0 47.94 43.6 0.14 - j0.26 0.38 + j1.57

here that the input as well as feedback capacitance

increases, while the drain-source capacitance is

almost equal to its pendant at 1MHz.

The model of the 70W device with Wt=14.4mm

total gate width (CGHV1J070D) behaves exactly

like twelve times a Wt=1.2mm model in parallel

(CGHV1J006D). That leads to the assumption that

the model itself is up-scaled. Vice versa twelve

times, a 1.2mm model can be seen as twelve times

atransistor cell and can be used for further anal-

ysis to gain deeper insight into cell temperature,

current, voltage or the resulting loadline.

Classical Load-Pull

The Load-Pull results of the used transistor were al-

ready obtained by the manufacturer and included

in its model. Within this chapter, the model is used

to perform a Load-Pull analysis only within the

simulation software. First the optimization goals

of the Load-Pull analysis needs to be defined. The

common approach to optimize towards a maxi-

mum output power in parallel to a maximum PAE

was used. The derived impedances are stated in

Tab. 3.3. It can be noted that the optimum load

impedances are extremely low (≈0.4Ω) with lit-

tle dependence over the frequency range 13 to

15GHz. By analysing 12 transistor cells in parallel

(12 x CGHV1J006D), exactly the same impedances

can be obtained as shown in Tab.3.3, which is in

accordance to the scaling rules given in Sec.2.2.

However, as shown in Fig.3.12, a small change

in impedance results in a huge difference with re-

spect to Pout and PAE. The impedances are shown

in the Z-domain, as it is more valuable than the

Smith Chart for displaying a "short". All Load-

Pull analysis were carried out with an increased

flange temperature of the simulation model of

Tflange =80◦C. This is necessary based on the

mounting limitations that have already been ob-

tained in Sec.3.2.1.

Multi Frequency Load-Pull

The analysed impedances represent optimum val-

ues for a certain frequency. To realise a matching

over the specified frequency range Fup, which is

{13.75-14.5GHz}, one would be interested in, for

example, the Pout dependence vs. F. Classical

Source- and Load-Pull contours are only valuable

for one frequency. By using the centre point of

these contours for each point in Fup as optimum

impedances, the result would be a huge restriction

for the design.

Single frequency contours are summarized with

their least intersection (for power or PAE level, re-

spectively) to the newly defined multi-frequency

Source- and Load-Pull contours (MuFLoC). A

Load-Pull matrix [Pout, f1]that represents all Pout

values over a certain complex range of [ZLoad], can

be defined for fixed biasing (VDS,VGS), a certain

input impedance (ZS,optf1) and the input power

conditions (Pin) of f1:

f1:[Pout, f1] ([ZLoad],Pin, VDS,ZS,optf1)(3.15)

These matrices can be generated over all in-band

frequencies f1,f2...fn:

f2:[Pout, f2] ([ZLoad],Pin, VDS,ZS,optf2)(3.16)

fn:[Pout, fn] ([ZLoad],Pin, VDS,ZS,optfn)(3.17)

Now it is possible to calculate the lowest Pout value

matrix [Pout, Fup ]over all in-band frequencies Fup:

[Pout, Fup ]=[Pout, f1]∩[Pout, f2]∩... ∩[Pout, fn]

(3.18)

In other words, the Pout =47dBm contour depicted

in Fig.3.12 represents the impedance area where

an output power of at least 47dBm from 13.75

to 14.5GHz (Fup) can be expected. In contradic-

tion to that, the individual max. output power

contours (Pout,max = 48dBm) are shown frequency

Chapter 3. Power Amplifier

FIGURE 3.12: Simulated optimum Load-Pull impedan-

ces ZLoad for Pout,max =48dBm within 13.75;14;14.25;-

14.5GHz. Furthermore, multi-frequency Load-Pull con-

tours (MuFLoC) are shown for Pout and PAE that

represent the least-intersection within Fup (VDS =40 V;

IDq ={300}mA; Pin =39dBm).

dependent for f1=13.75GHz, ...fn=14.5GHz. The

same principle applies for PAE with a frequency

dependent [PAEout, f1]:

f1:[PAEf1] ([ZLoad],Pin, VDS ,ZS,optf1)(3.19)

and the least intersection over all in-band frequen-

cies Fup:

[PAEFup ]=[PAEf1]∩[PAEf2]∩... ∩[PAEfn]

(3.20)

During the design procedure of matching circuits

these MuFloCs help to observe whether all re-

alised impedances fit within a certain contour or

not, whereas using only the optimum impedances

means you can just observe a distance between the

optimum and realised impedances without any

relation to the consequences.

Linearity Load-Pull

By suggesting that a solution for the frequency

dependency of the Load-Pull contours was found

by the MuFloCs, the influence of the optimum

loads regarding linearity cannot be ignored. Ghan-

nouchi et al. state that with a two-tone signal in

compression, the resulting intermodulation dis-

tortion (IMD) can be used as a sufficient mea-

sure of linearity during the Load-Pull analysis

[Gha+13, S.197 ff.]. However, this analysis de-

pends on the type of the signal used (e.g. two-

tone or a QPSK, 8PSK) as well as on the chosen

operation point. For choosing a two-tone signal

with a rather high 10MHz spacing, Load-Pull con-

tours can be observed with regards to the IMD3,

as in Fig.3.13(a). The dependency of the IMD3 is

shown in relation to the chosen quiescent current

(IDq ={50; 150; 300}mA) for a back-off operation

(Pin =30dBm). The spot with the lowest intermod-

ulation is mainly located at a short. The obtained

optimum impedances related to Pout and PAE are

displayed by the crosses ZL,opt. One would notice

that the low IMD3 located at the short are mainly

related to the low output power at this impedance

level in contradiction to the so-called sweet spots of

the biasing.

The same approach can be used for analysing the

IMD5 related products as can be seen in Fig.3.13(b).

With an increasing quiescent current the spot

moves from the short towards 0.7+j*1Ω.

Taking a change in the input power level into con-

sideration, we see a totally different behaviour in

Fig.3.14(a). It can be noted that this spot moves

towards a purely resistive higher ohmic load (1+

j*0.5Ω) for this increased compression. The value

of the IMD3 degrades with input level due to the

increased harmonics. By considering the IMD5

related products, as can be seen in Fig.3.14(b),

the spot area with the lowest intermodulation

is located at a point with a higher susceptance

(1+j*1.5Ω) for these increased input power levels.

By choosing different baseband impedances we

−27

−24

−21

−30

−27

−24

−21

−27

−24

−21

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

−1

−0.5

0.5

1.5

50 mA

150 mA

300 mA

ZL,opt

(a)

−40

−37

−34

−50

−47

−44

−41

−42

−39

−36

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

0.5

1.5

50 mA

150 mA

300 mA

ZL,opt

(b)

FIGURE 3.13: Simulated (a) IMD3 and (b) IMD5 re-

lated load impedances for various quiescent currents

(VDS =40V; IDq ={50; 150; 300}mA; Pin =30 dBm).

Chapter 3. Power Amplifier

−27

−24

−21

−20

−17

−14

−11

−8

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

−1

−0.5

0.5

1.5

30 dBm

33 dBm

36 dBm

ZL,opt

(a)

−42

−39

−36

−35

−32

−29

−24

−21

−18

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

0.5

1.5

30 dBm

33 dBm

36 dBm

ZL,opt

(b)

FIGURE 3.14: Simulated (a) IMD3 and (b) IMD5 related

load impedances for various power levels (VDS =40V;

IDq =300mA; Pin ={30; 33; 36}dBm).

see different locations of the IMD spots again.

Fig.3.15(a) displays the dependency of IMD3 re-

lated products to a baseband open, short or an

inductive load while the previous observations

were related to a baseband open. On account of

the static increase of the susceptance by the pre-

vious analysis it can be noted that an inductive

load shows the lowest IMD3s at an impedance of

(1.5+j*1.5Ω), while an open leads to a lower suscep-

tance part of (1+j*0.5Ω)The IMD5 dependency on

the baseband impedance is mainly the same, as the

IMD3 dependency and can be seen in Fig.3.15(b).

What all these spots have in common is that their

location is far away from the already obtained op-

timum impedances related to Pout and PAE. Conse-

quently, the influence of IMD related products can-

not be taken into consideration for realising match-

ing circuits. However, a change in the quiescent

current as well as the baseband impedance during

the measurements can result in an improved per-

formance.

Harmonic Load-Pull

Finally, the optimal impedances located at the har-

monics will now be considered. The generated har-

monics of the device itself can be reflected in a cer-

tain manner of phase in order to improve the over-

all efficiency of the device within saturation (e.g.

switch mode amplifier). Rather than simply apply-

ing an open at the second and third harmonics, this

−23

−20

−17

−14

−29

−26

−23

−31

−28

−25

−22

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

−1

−0.5

0.5

1.5

bb open

bb short

bb ind

ZL,opt

(a)

−38

−35

−32

−29

−41

−38

−35

−43

−40

−37

−34

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.5 1 1.5

0.5

1.5

bb open

bb short

bb ind

ZL,opt

(b)

FIGURE 3.15: Simulated (a) IMD3 and (b) IMD5 re-

lated load impedances for various baseband impedances

(VDS =40V; IDq = 300 mA; Pin = 30 dBm).

reflection (Γ=0.95) is changed in phase during the

next analysis to see the influence on the device’s

total efficiency.

Fig.3.16(a) displays the PAE (left axis) as well as

Pout (right axis) of the device while sweeping the

phase angle of the second harmonic (2·f0=28GHz)

as well as the third harmonic (3·f0=42GHz). It can

be observed that neither the second nor the third

harmonic influences the Pout, and as a result the

PAE, significantly. Only a drop of 0.25dB regard-

ing Pout as well as 2.5% PAE can be observed by

the phase angle of 180◦. The influence of the third

harmonic to the PAE, is negligible, due to the low

transit frequency of fT=40GHz.

The small influence with regard to the phase of the

second harmonic can be explained by the size of

the horizontal device of this bare-die. As can be

seen in Fig.3.6 the horizontal dimensions of this

bare-die is ≥3

4λ2·f0for the second harmonics. The

second harmonics are already reflected towards

the intrinsic cells within different phase angles

over the ntimes transistor cells. In consequence,

an additional reflection during this extrinsic Load-

Pull simulation has a minor influence.

Chapter 3. Power Amplifier

0 90 180 270 360

PAE (%)

Phase of Γ( °)

0 90 180 270 360

45.5

46.5

47.5

Pout (dBm)

PAE (Γ2*f0)

PAE (Γ3*f0)

Pout (Γ2*f0)

Pout (Γ3*f0)

(a) CGHV1J070D

0 90 180 270 360

PAE (%)

Phase of Γ( °)

0 90 180 270 360

35.5

36.5

37.5

Pout (dBm)

PAE (Γ2*f0)

PAE (Γ3*f0)

Pout (Γ2*f0)

Pout (Γ3*f0)

(b) CGHV1J006D

FIGURE 3.16: Simulated phase dependency of second

(2·f0=28GHz) and third (3·f0=42 GHz) harmonic re-

flection coefficient Γ=0.95 on PAE, Pout at f0=14 GHz (a)

70W device (b) 6W device (VDS =40V; IDq = 2% Imax).

This theory is proven by analysing the smaller de-

vice CGHV1J006D which represents, through the

scaling rules, one transistor cells. Its fT=46GHz is

only slightly higher but the horizontal dimensions

are significantly less than λ

4for the second harmon-

ics. The harmonic phase-angle swept Load-Pull

analysis can be seen in Fig.3.16(b). A typical de-

crease of PAE down to 38% can be observed for the

phase angle of 180◦. It comes along with a drop

in output power of 1dB. In addition, an influence

of the third harmonic phase angle can be observed

within the 2% PAE range. One would define a safe

phase angle area within 0-150◦and 300-360◦.

Efficiency Limitations

The described achievements concerning the op-

timum impedances in relation to frequency repre-

sent valuable data only for the port reference plane

of the device. Additional losses of the interconnec-

tion as well as the matching will further decrease

the efficiency of the amplifier. Moreover, this anal-

ysis is only representative for the bare-die itself.

Packaging the bare-die will lead to an additional

package capacitance which decreases fTas well as

fMAX of the transistor. On account of the fact that,

the device already barely works at 14GHz, addi-

tional packaging limitations cannot be tolerated,

which is why only a shielding of the whole MIC is

considered within this work.

Chapter 3. Power Amplifier

3.3 Upper Ku-band MIC PA

3.3.1 PA Design Approach

The very low optimum source and load impe-

dances lead to a high impedance transformation

ratio of the network of 50 Ω

0.4 Ω =125 at the output.

Contrary to that is the need for achieving this

transformation ratio over 5% fractional bandwidth

(FBW). The previously analysed low power gain

of ≈6.5dB results in a multi-stage matching ap-

proach that can increase the gain to an acceptable

level (Fig.3.17(a)). The necessary driving level of

the pre-amplifier (Q1) has been calculated to be

Pout,drv ≈15W. Preliminary analysis has shown

that the smaller device with 4.8mm gate width can

hardly reach that level. Additional mismatch con-

straints, which are unavoidable when matching

the output of this smaller device to the input of Q2,

will further decrease its level. A previous design

realisation showed that a continuous power level

of ≥12 W can be reached in a deep compression

[Maa+16a].

Therefore, the same device was chosen for the Q2

as well as Q1 while taking into account the total

PAE, like in [Saa+14]. The resulting PAE of the two

stages can be calculated with:

total PAE =Gain Q2−1

Gain Q1

(Gain Q2

η Q2) + ( 1

η Q1)(3.21)

while the derivation is given in Appx.A.79. As

can be seen in Fig.3.17(b), the gain of Q2 needs

to stay high in order to achieve a sufficient total

PAE of ≥30%, whereas the drain efficiency of Q1

needs to exceed ηQ1≥20% (assuming ηQ2=40%).

The premature power/gain compression of the

HEMT device when operated at the high input

power levels of Q2 causes additional AM-AM

non-linearity [Qua08]. This compression is mainly

caused by the gm curve progression. At the anal-

ysed frequencies, already exceeding fKNEE (k≥1),

the gm curve is asymmetric with a strong increase

from turn-on to gmmax (Fig.3.10(a)). The slow de-

crease towards gm =0S is the reason for a constant

compression over Pin. The simulations show that

(a)

0 10 20 30 40

first stage drain efficiency, ηd1 (%)

total PAE (%)

Gain Q2=4 dB

Gain Q2=5 dB

Gain Q2=6 dB

Gain Q2=7 dB

(b)

FIGURE 3.17: Proposed (a) two stage PA topology with

(b) theoretical total PAE considerations.

this difficult time-dependent AM-AM compres-

sion can be compensated by a lower quiescent

current of Q2 (Sec. 2.3) and by the type of applied

input signal [Ped+14]. On the other hand, the

increased AM-PM non-linearity can be compen-

sated via a pre-distortion for modulated signals.

Thus, for the design of matching networks, the

optimum load impedances for Q2(ZL OMN) are

chosen within saturation conditions. The load

impedances for Q1(ZL ISMN) represent the maxi-

mum gain with respect to the lower output power

level. The input impedances of both transistors

Q1,Q2(ZS IMN, ZS ISMN) should accomplish a flat

gain over frequency. A mismatch of the input

impedance of Q2(ZS ISMN) from the optimum con-

jugate complex match can help to lower AM-PM

non-linearities as shown in [Gio+16].

3.3.2 Design of Matching Networks

The substrate chosen for the matching circuit com-

promises between low losses and a high εrto

realise low transmission line impedances, small

sizes as well as low radiation losses. Within this

design, an intentionally one substrate approach

has been used due to manufacturing constraints.

Chapter 3. Power Amplifier

Multiple substrates with different εrvalues are

widely used [Kaz+11],[Not+12],[Ima+14] while

producing high losses as well as high radiation on

account of interconnections, as already shown in

Fig.2.2. The height of the substrate should ideally

be close to the bare-die height in order to ease the

bonding. For this reason, a thin alumina substrate

(Al2O3) with a height of 127 µm and an εr= 9.9

has been chosen as it can take advantage of its

extremely low tan δ. With a layer stack including

a resistive NiCr-layer, it is possible to produce

highly accurate thin film resistors on the substrate.

To handle high currents the Au metallization has

been grown to a thickness of 10 µm. All the sub

elements have been individually analysed in a

schematic as well as a 2.5D Momentum TM simula-

tion to fulfil their specification. Parametrized EM-

models of the components have also been created

within Keysight ADS TM. These models benefit from

considering all parasitics while maintaining the

ability to change their characteristic parameters,

such as their length or width. All sub elements

were evaluated based on 3 D CST TM simulations

taking possible radiation losses into account1.

Matching

The matching of devices with very low impedan-

ces is challenging. By taking their additional tra-

jectories over frequency into account, a broadband

matching for the input matching network (IMN)

as well as the output matching network (OMN) is

almost impossible. Particularly in the interstage

matching network (ISMN), the two consecutive

stages need to be matched to one another. The

required transformation ratio is considerably low

but a complex to complex transformation needs

to be done with different directions of the imag-

inary trajectories. Notwithstanding the previous

difficulties, a reactively matched design approach

has been chosen to compensate the dominant par-

asitics.

1A more detailed description of the simulation techniques is

given in Appx.A.4

FIGURE 3.18: Schematic of the initial output matching

circuit.

Distributed Matching

A matching circuit was developed based on the

mechanical and electrical constraints. Taking these

constraints into account, an ideal matching net-

work can be designed. The additional parasitic

limitations would decrease the obtained results

from the ideal matching network towards a real

matching network. For this reason, a matching

circuit was developed based on lumped elements,

taking their Qinto consideration. They are con-

nected via transmission line elements (analysed

in Sec.2.1) within a mixed schematic (Fig.3.18).

The drain-source capacitance CDS at the output is

resonated out with a shunt inductance Lfeed. An

additional series capacitance has been used to com-

pensate Lbond, for further transformation as well as

for the ability to block the dc. Ideally, the tran-

sistors internal current source can now be seen as

a purely resistive impedance. The series line ele-

ments (TL1...TL4) behave like a stepped impedance

transformer starting with a low characteristic im-

pedance from the transistor. An additional open

stub (TLstub) has been used in between the last

two transforming elements to flatten the filter re-

sponse. The bandwidth of a stepped impedance

transformer is limited by the number of elements

(N). The transformation ratio is limited by the val-

ues (Z1..N). Furthermore, both issues are limited

to the lowest possible insertion loss (N→0) and

the lowest realisable line impedance (Zmin...N). The

schematic approach is divided into the following

sub elements:

•dc-feed

•Parallel Lines

•Bus Bar

•Interdigital-Capacitor

Chapter 3. Power Amplifier

10 20

−45

−40

−35

−30

−25

−20

−15

−10

−5

Mag S21(dB)

Frequency (GHz)

0.2

0.5

1.0

2.0

5.0

+j0.2

−j0.2

+j0.5

−j0.5

+j1.0

−j1.0

+j2.0

−j2.0

+j5.0

−j5.0

0.0 ∞

Z0=50 Ω

meas

sim

(a)

10 20

−35

−30

−25

−20

−15

−10

−5

Mag S21 (dB)

Frequency (GHz)

0.2

0.5

1.0

2.0

5.0

+j0.2

−j0.2

+j0.5

−j0.5

+j1.0

−j1.0

+j2.0

−j2.0

+j5.0

−j5.0

0.0 ∞

Z0=50 Ω

meas

sim

(b)

FIGURE 3.19: (a) Measured and simulated radial stub

with λ/4-line line and (b) additional gate resistor.

that need to fulfil the requirements of the subsec-

tions.

dc-feed Requirements

For realising a dc-feed, a λ/4-line with an addi-

tional radial stub was designed. As a compromise,

the characteristic impedance of the λ/4-line needs

to be low (high width) to be able to transmit the

high current at the drain, but preferably high, to

realise a high Qof the transformed open over the

bandwidth. This dc-feed was designed for both

gate and drain supplies. It was produced sepa-

rately within a test structure, including GSG probe-

pads at the RF/dc reference planes. A compari-

son between probed measured and field-simulated

analysis is shown in Fig.3.19(a) for the transmis-

sion as well as the reflection. The comparison visu-

alizes the high accuracy of the thin film manufac-

turing process with a sharp rejection at the centre

frequency. To ensure stability at the gate-side of the

transistor the dc-feed was extended with an addi-

tional series resistor RGate =50 Ω based on the NiCr

resistive layer. Thus, the comparison between mea-

surement and simulation in the Smith Chart shows

its origin at 100 Ω with a great match according to

the simulation.

Parallel-Lines Requirements

Trying to realise a transmission line with an ex-

tremely low characteristic impedance tends to be-

come a parallel plate in microstrip. The width

of the microstrip line (w) gets multiple times the

height (h) of the substrate which violates Wheelers

axiom of microstrip definition. As a result, the cur-

rent distribution can no longer be approximated

by a quasi-TEM microstrip mode. The high width

of the bare-die (4.8mm) leads to a minimum strip

width wof the same value. However, this wis

more than λ/2 on the chosen substrate (Fig.3.6)

and may result in a multi-mode propagation. The

power distribution over the width of such a wide

microstrip line shows different magnitude and

phase orientations which disturbs an even-mode

propagation. In addition, the resulting characteris-

tic impedance Zmin =6.5Ωis at least 16 times less

than the required transformation ratio.

Parallelizing one transmission line to ntransmis-

sion lines can help to lower the total characteristic

impedance. Given that an even-mode occurs at

the transmission line, the field distribution of a

microstrip line is ≈ntimes the single one. The

resulting distributed transmission lines have to be

combined to a one ended line at the Z0=50 Ωout-

put over the number of sections N, as can be seen

in Fig.3.21(a). The distance of the twelve parallel

pads at the bare-die side is 360 µm, which results in

a centred distance of all twelve parallel microstrip

lines to be 360 µm. Furthermore, the minimum

distance of two metallized structures is 50 µm ac-

cording to the substrate design rules. As a result,

Chapter 3. Power Amplifier

100 150 200 250 300

w (µm)

100150200250300

s (µm)

Impedance (Ω)

Z0,o

Z0,e

Z0,MS

(a)

1 2 4 6 8 10 12

Impedance (Ω)

Zn,ideal

Z0,o

Z0,e

Z0,EM

(b)

FIGURE 3.20: (a) Calculation of characteristic impedance

from two coupled MS lines (b) Calculation of charac-

teristic impedance from ncoupled MS lines (each with

w=310µm), both for a Al2O3substrate with 5mil thick-

ness at 14GHz.

the possible width of one MS line is {50 −310}µm.

Thus, the characteristic impedance of a MS line

(Z0,MS ) can therefore be calculated, as described

in Sec.2.1 and given in Appx.A.38.

The result is that parallel MS lines could not be

considered to behave like a single MS line. Accord-

ing to Kirchning [Kir+84], the coupling between

two MS lines can be calculated by the definition of

an effective dielectric constant of the even-mode

propagation (εr,eff,e), as well as the odd-mode prop-

agation (εr,eff,o). This analytical calculation is car-

ried out for the width limitations of the MS lines in

question and is shown in Fig.3.20(a) (Appx.A.47).

Here Z0,o denotes the odd-mode, Z0,e the even-

mode as well as Z0the characteristic sum of both.

Towards an increased line-width wthe distance

between both lines shas to decrease to be able to

arrange all MS-lines within the 360µm grid. How-

ever, the MS based impedance calculation achieves

a slightly higher value than the coupled MS lines

calculation due to the coupling (For w=310 µm:

Z0,MS=29.5 Ω;Z0=27.6 Ω).

Due to the twelve transistor cells, parallel lines sec-

tions with n={1; 3; 6; 12}over N=4 were chosen.

A first approximation of the transmission line (TL)

parameter can be done by simply dividing the

characteristic impedance by the number of parallel

lines.

Zn,ideal =Zn,distri

n; Φn,ideal = Φn,distri (3.22)

Nevertheless, the coupling in between all MS lines

cannot be neglected, so the parallel structure was

analysed based on EM-simulations. The compar-

ison is shown in Fig.3.20(a) and visualizes that n

parallel lines lowered the equivalent Impedance

both in the EM-simulation (Z0,EM), as well as in

the simple approach (Zn,ideal), but towards an in-

creased nthe values differ up to a factor of 2. Up

to now no analytical solution to this problem has

been found in the literature. Consequently, the

quasi static analytical calculations of [Kir+84] for

two parallel lines are:

Z0,e =Z0…εr,eff

εr,eff,e

(1 −(Z0/377)(εr,eff )0.5Q4)

(3.23)

Z0,o =Z0…εr,eff

εr,eff,o

(1 −(Z0/377)(εr,eff )0.5Q10)

(3.24)

and they were extended to nparallel lines with

the assumption that the effect of the coupling de-

creases with an increase of nby a simple quadratic

polynom:

nfit =−8.919e−4n2+ 0.804 n+ 0.2174 (3.25)

to result in:

Z0,en =Z0,e nfit

−1(3.26)

Z0,on =Z0,o nfit

−1(3.27)

The complete analytical calculation is given in

Appx.A.47. This polynomial correction is stated

on extensive 2.5-D as well as 3-D field simulations

Chapter 3. Power Amplifier

n=12

Z1, Φ1

ZLoad

Z2, Φ2Z3, Φ3Z4, Φ4

6xZ3, Φ33xZ2, Φ21xZ1, Φ112xZ4, Φ4

12xZ4, Φ4

6xZ3, Φ3

3xZ2, Φ2

ZLoad

n=6 n=3

(a)

n=12

Z1, Φ1

ZLoad

Z2, Φ2Z3, Φ3

Z4, Φ4

6xZ3, Φ33xZ2, Φ21xZ1, Φ1

12xZ4, Φ4

6xZ3, Φ3

3xZ2, Φ2

ZLoad

n=6 n=3

24xZB, ΦB

2xZB, ΦB

(b)

FIGURE 3.21: (a) Schematic visualisation of the parallel MS-line concept with (b) added a Bus Bar in between. Step

by step visualisation of the virtual open in a Bus Bar. Starting with an open stub (c), double open stub (d) resulting

in interconnected symmetrical stubs (e).

and is shown in Fig.3.20(b) as well. A comparison

of the measurements cannot be given here because

nparallel lines cannot be easily measured within

an even-mode propagation. The new analytical

approximation Z0fits very well with the EM sim-

ulated structure (Z0,EM ) and denotes that equiv-

alent characteristic impedance values of down to

Z0=3Ωare realisable. The calculation of the char-

acteristic impedances of the sections n={1; 3; 6}

is simpler due to the higher distance sof the

MS lines and in consequence a weaker coupling

(Fig.3.21(a)).

Bus Bar Requirements

For providing an equal dc distribution to all tran-

sistor cells, while not destroying the even-mode

propagation over the distributed transmission-line

combiner, the Bus Bar principle was introduced by

Marsh [Mar97]. In Fig. 3.21(c), a T-junction shows

a proper RF isolation between two branches while

working in an even-mode. It is self evident, that

the RF propagation stays the same when splitting

the two open stubs into four, keeping their sum

of impedances constant (Fig.3.21(d)). While main-

taining a symmetrical network like in Fig.3.21(e), it

is possible to connect two of the open stubs at their

end, as long as their electrical length (ΦBB) is much

Chapter 3. Power Amplifier

less than λ/4. As a result, a bar is built which al-

ternately provides a virtual open and a combining

sink. This concept enables the provision of a dc cur-

rent to all transistor cells via a wide bar while main-

taining RF isolation in between them by the result-

ing virtual open. Consequently, the bar is added to

the combining circuit of Fig.3.21(a), resulting in an

eased combining in Fig.3.21(b) due to the inserted

odd-mode sink along the Bus Bar. This principle

is limited to a FBW of ≈15% [Mar+99]. For an in-

creased FBW the virtual open combining planes

can be capacitively loaded to ensure a higher iso-

lation.

Interdigital-Capacitor Requirements

Within this design, all capacitors (Cimn, Cismn,

Comn) were realised by Interdigital capacitors on

the substrate. By using n= 6 Interdigital capac-

itors in parallel, the total series capacitance was

increased. The finger width and spacing are set

to 50µm according to manufacturing constraints.

Lumped element models have been developed

and verified by electro magnetic (EM) simulations.

Fig.3.22(a) depicts a comparison between the sim-

ulated and measured results for one single input

capacitor (Cimn

n) as well as the behaviour of the

equivalent model (Fig.3.22(b)). The values for

the equivalent model are Cs=0.06pF, Cp=0.11pF

and Ls=0.14nH for the finger length Lf=0.2mm

and width Wf=50µm as well as a distance Wgap =

50µm in between this structure. Even though, the

parallel capacitance (Cp) is about twice as high

as series one (Cs), the capacitors are utilized as

complex matching elements. The SRF is kept high,

in this case above 20GHz, to achieve an almost

constant effective capacitance within the desired

frequency range (Fig. 3.22(a)). As a result, possible

deviations between simulation and realisation due

to manufacturing tolerances can be minimized.

Nevertheless, their Q ≈40 is rather low, further

decreasing with frequency. The Interdigital capac-

itors with their RF series resistance build a high-

pass filter which reduces possible low frequency

oscillations at the input side of the transistor.

(a)

LsCs

CpCp

(b)

Wgap

(c)

FIGURE 3.22: Measured and simulated capacitance (a)

lumped equivalent model (b) and layout (c) of Interdigi-

tal capacitor.

3.3.3 Simulation Approach

Small-Signal Analysis

The matching networks were developed based

on parametrized EM-models of the previously

described sub-elements. Its objective was to re-

alise the required optimum source- and load -

impedances that were previously identified by

the Source- and Load-Pull- simulations. Dur-

ing the small-signal simulation of the matching

networks the ports were loaded with the conju-

gate optimum Load-Pull impedances, represent-

ing a large-signal match. The resulting schematic

is given in Fig.3.23(a) with its characteristic values

of the elements shown in Tab.3.4. The EM-based

simulated impedances from 13.75-14.5GHz for

the input (ZS IMN,realised,ZS ISMN,realised) are shown

in Fig.3.23(b). For the output side of the transis-

tor the impedances (ZL ISMN,realised, ZL OMN,realised)

are shown in Fig. 3.23(c). Furthermore, multi fre-

quency Source- and Load-Pull contours (MuFLoC)

are plotted considering the output power as well

as the PAE. The contours represent the minimum

values of all frequency - dependent data in be-

tween 13.75- 14.5GHz - and so represent valuable

in-band performance data, as described in section

3.2.2. It can be seen that the input of the first

stage (IMN Q1) as well as the second stage (ISMN

Q2) are well-matched to the optimum impedances

Chapter 3. Power Amplifier

Pout

Pout,n=6

Pout,n=3

Pout,n extrinsic

(a)

(b) (c)

FIGURE 3.23: (a) Schematic of the proposed two-stage amplifier divided into three matching circuits (IMN, ISMN,

OMN). Each transmission line (TL) is parallelised by n-times written underneath in green. Simulated EM-based

impedances realised by the matching circuits within Fup for the input sides of Q1(IMN) and Q2 (ISMN) (b) and

for the output sides of Q1(ISMN) and Q2(OMN) (c). The plotted multi-frequency Load- and Source-pull contours

(MuFLoC) represent the minimum value over the desired frequency range Fup.

(ZS,opt). The direction of the imaginary part is par-

ticularly the same. For the output side, much more

attention was paid to achieve a high Q transfor-

mation for the output of (Q2). Consequently, the

realised impedances are inside the Pout =47 dBm

contour. The high PAE sensitivity should be noted,

changing from ≥35% for the inner circle within

10% down to 25% only by changing the load-

impedance 0.5Ω. Within the ISMN the trajectories

of the load and generator impedances travel in

opposite directions over frequency, which is why

the realised matching is a compromise. All three

matching circuits are able to provide a matching

≥15dB towards their opposite impedance.

An additional Monte-Carlo analysis takes the toler-

ances of Tab.3.2 into account. Here a small-signal

transmission of up to 23dB for Fup can be seen

in (Fig.3.24(a)). The additional bond tolerances

influence both stages, including the IMN, twice

the ISMN as well as the OMN. Therefore, the S-

Parameter changes in Fig.3.24(a) need to be tol-

erated. The IMN, ISMN as well as OMN were

TABLE 3.4: Schematic values of the proposed two-stage

amplifier for f0=14GHz

IMN TL1TL2TL3TL4TL5

Φ 106◦111◦29◦41◦31◦

ZT L 50 Ω 14 Ω 3.6 Ω 2.3 Ω 25 Ω

ZT L xn50 Ω 42 Ω 21.6 Ω 27.6 Ω 50 Ω

Cimn =0.4pF RGate =50 Ω LBond =12.5pH

ISMN TL6TL7TL8TL9

Φ 45◦5◦7◦37◦

ZT L 2.9 Ω 6 Ω 6.6 Ω 2.25 Ω

ZT L xn34.8 Ω 36 Ω 39.6 Ω 27 Ω

Cismn =0.282pF RGate =50 Ω LBond =12.5pH

OMN TL10 TL11 TL12 TL13 TL14

Φ 35◦25◦113◦104◦22◦

ZT L 2.25 Ω 4.6 Ω 13.3 Ω 50 Ω 25 Ω

ZT L xn26.4 Ω 27.6 Ω 26.6 Ω 50 Ω 50 Ω

Comn =0.498pF LBond =12.5pH

analysed as combining circuits (1 to n) as well. The

theoretical insertion loss of a real to real 1 to n

combiner can be defined as follows:

IL = 10 ·log 1

n(3.28)

Chapter 3. Power Amplifier

12.5 13 13.5 14 14.5 15 15.5 16 16.5

−20

−10

Frequency (GHz)

S−Parameters (dB)

S11

S21

S11 monte

S21 monte

(a)

13.5 14 14.5 15

Frequency (GHz)

η(%), Pout (W)

Pout

Pout,n intrinsic

Pout,n extrinsic

Pout,n OMN (n=6)

Pout,n OMN (n=3)

Pout,n

ηout,n extrinsic

ηout,n

(b)

FIGURE 3.24: (a) Simulated small-signal (b) large-signal

behaviour of the amplifier (VDS1,2 =40V; IDq1,2 = 300 mA).

for n= 12 which represents the IMN as well as the

OMN combiner the losses are:

IL = 10 ·log 1

12 = 10.79 dB (3.29)

Within the EM-simulation the IL of all nsections

was -11.5dB with ±0.5dB amplitude imbalance.

The isolation of the Bus Bar can be depicted to be

in the range of 7dB. This way the phase difference

between all branches is ±3◦with an increase to-

wards higher frequencies, as can be seen further

on in Fig.3.25.

Large-Signal Analysis

During a large-signal analysis, power as well as fre-

quency is swept using a Harmonic Balance Analysis.

Special attention was given to the temperature of

the junction so as not to exceed the theoretical

cooling constraints during the simulation. The

sensitive gate current was also monitored. The

simulated output power of the amplifier (Pout) is

shown in Fig.3.24(b) using the normal large-signal

model of the device. Here, an output power level

≥50W can be obtained over Fup. Each ntransistor

cells was modelled separately and de-embedded to

its intrinsic current source. It was therefore possi-

ble to simulate the output power of all nintrinsic

current sources described as (Pout,n intrinsic). It can

be obtained that the intrinsic power level is ≈10W

higher than the output power level of the ampli-

fier (Pout). To determine the dependency of these

losses, simulations were carried out at various

positions within the OMN (compare Fig.3.23(a))

where (Pout,n extrinsic) is the extrinsic output ref-

erence plane of the device, (Pout,n OMN (n=6)) is

the reference plane where n=6 lines are in paral-

lel and (Pout,n OMN (n=3)) is the reference plane

where n=3 lines are in parallel. According to

these simulations (Fig.3.24(b)), the losses of the

OMN increases towards the output of the am-

plifier. The total losses of the OMN (αc, αd, αr)

are in the range of 5W according to the differ-

ence of (Pout,n extrinsic) to (Pout,n). Based on this

analysis the drain efficiency of this second stage

(Q2) can be compared between the extrinsic ref-

erence plane (ηout,n extrinsic) and the output of

the amplifier (ηout,n) with a difference of only 3%.

The achieved extrinsic efficiency (ηout,n extrinsic)

is nearly the maximum available drain-efficiency

simulated within the Load-Pull analysis (Tab.3.3)

which indicates a great matching.

The magnitude and phase imbalance of all transis-

tor cells can be analysed and are shown in Fig.3.25.

A phase-imbalance of the combiner can be ob-

served that may be improved by changing the

inner bond-wires. This can also be seen within

the sum of all intrinsic powers within Fig.3.24(b),

where the distributed simulation approach de-

grades in power (Pout,n) towards higher frequen-

cies, while the power (Pout) of the one transistor

approach increases.

In addition, intrinsic load-line simulations of each

transistor cell (Q2.1...Q2.12) were carried out, vi-

sualising a saturated amplifier (Fig.3.26(a)). The

load-lines indicate a typical Class-AB response

with an oval shape towards a line - spanning a

lower amount of area than a Class-A curve which

Chapter 3. Power Amplifier

13.5 14 14.5 15

−0.5

0.5

1.5

Frequency (GHz)

∆mag (dB)

Q2.2; Q2.11

Q2.3; Q2.10

Q2.4; Q2.9

Q2.5; Q2.8

Q2.6; Q2.7

13.5 14 14.5 15

−3

−2

−1

Frequency (GHz)

∆phase ( °)

FIGURE 3.25: Simulated (left) magnitude imbalance

(right) phase imbalance of the transistor cells referenced

to (Q2.1...Q2.12).

improves efficiency. The power distribution be-

tween the transistor cells as well as leakage cur-

rents were analysed. From Fig.3.26(b) a good

distribution between the twelve cells can be no-

ticed. The outer ones (Q2.1;Q2.12) provide the

most RF-power to the matching circuit, due to their

lower baseplate temperature and the reduced com-

bining parasitics. Nevertheless, a slightly earlier

degradation of the power towards higher frequen-

cies can be observed for the inner transistor cells

(Q2.5...Q2.8). The combiner efficiency (ηc) can be

calculated to be ≥83% for the relation between the

output power (Pout) and the sum of all distributed

extrinsic transistor cells [Gup92]:

Pout =ηc

∑

i=1

Pout, Q2.n extrinsic (3.30)

Large-Signal Stability

Given that the designed amplifier is a multi-stage

circuit, the stability calculations could not be done

using classical K-factor analysis [Rol62]. Stability

has therefore been proven in a large-signal anal-

ysis by the STAN TM-Tool [Del+12]. By applying

this approach, additional odd - mode signals were

injected to all gates, drains and dc- connections

of the 24 transistor cells. By calculating the large-

signal transfer function of the amplifier, a pole

zero analysis was performed. In Fig.3.27(a) a sta-

ble operation can be seen as an example for an

inserted odd mode excitation at one certain port

over various power levels within the ISMN. Un-

stable poles (in red arrows) can be determined,

located at the same point as right-half-plane (RHP)

zeros for the maximum injected power. After ad-

ditional analysis they can be ignored as physical

quasi-cancellation occurring from the low sensitiv-

ity in the interstage matching circuit [Del+12]. The

same technique is applied for injecting power in

the OMN (Fig.3.27(b)). This means the injected

power must be increased regarding the higher

power level of Q2. Despite this, no oscillation

was obtained.

Analysis with modulated Signals

The large signal simulation of the two stage am-

plifier can be used to prove its linearity within a

ADS/System Vue TM co-simulation. A QPSK-signal

with 4MSym/s at 14GHz is generated. The sig-

nal is applied to the two-stage amplifier consid-

ering the different baseband impedances of the

dc-feed while holding the output power constant

at Pout, avg = 30 W. As can be seen in Fig. 3.28(a), a

short slightly improves the shoulders of the output

spectrum that are related to the IMD3 products2.

Apart from that, the quiescent current of the stages

{Q1/Q2} is varied to prevent IMDs that are related

to AM/AM or AM/PM compression products.

According to Fig.3.28(b) the quiescent current of

Q2 can be decreased to 50mA while holding the

current of Q1 at 300mA with the best ACPR per-

formance (cyan).

3.3.4 Realisation

The bare-dies and substrates were aligned and

mounted on a thick CuMoCu-flange (Fig.3.29(a)).

All wedge-wedge bond-wire interconnections were

automatically placed. A top view of the mounted

MIC can be seen in (Fig.3.29(b)). The die-attach

was analysed via X-Ray microscopy (Fig.3.29(c),

3.29(d)). The few bright dots are tiny air-inclusions.

2The Bandwidth of the baseband termination is larger than

the modulation bandwidth

Chapter 3. Power Amplifier

(a)

(b)

FIGURE 3.26: Simulated intrinsic

load-lines (a) and power distribu-

tion over power bar (b).

−4−3−2−1 0 1

−20

−10

Real (GHz)

Imag (GHz)

stable Poles

unstable Poles

stable Zeros

RHP Zeros

(a)

−15 −10 −5 0 5

−20

−10

Real (GHz)

Imag (GHz)

stable Poles

unstable Poles

stable Zeros

RHP Zeros

(b)

FIGURE 3.27: Example of an anal-

ysed amplifier large-signal transfer

function by the STAN TM-Tool for an

odd mode injection in the (a) ISMN,

(b) OMN.

−5 0 5

−60

−50

−40

−30

−20

−10

Frequency (MHz)

normalized PSD (dBm/Hz)

BB open

BB short

(a)

−5 0 5

−60

−50

−40

−30

−20

−10

Frequency (MHz)

normalized PSD (dBm/Hz)

50/300

50/50

150/150

300/50

300/300

(b)

FIGURE 3.28: Simulated output

spectrum with different (a) base-

band impedance (b) biasing con-

ditions (QPSK 4MSyms; 14GHz;

Pout,avg =30W).

This pallet was later on positioned in a surround-

ing aluminium water cooled fixture. On top of this

a203 µm thick bolted RO4003c substrate supplies

all dc-potentials as well as the RFin, RFout signals

to SMA-connectors (Fig.3.31). Within this fixture

the pallet can be measured on a alumina reference

plane (RefGSG) via GSG-probes as well as at the

SMA reference plane (RefSMA).

3.3.5 Measurement Results

Small-Signal Measurements

Probed small-signal measurements were carried

out with 500 µm pitch probes (|Z|-ProbeTM) on

the alumina reference-plane (RefGSG) using a net-

work analyser (N5230A). An additional 2nd tier

thru-reflect-line calibration (TRL) de-embeds the

ground-signal-ground-pads (GSG). In Fig.3.30

(top) a very good agreement between simulation

and measurement can be seen. Only a slight fre-

quency shift occurs as a result of the bond-wire

tolerances. Six samples (#1 ... #6) were manu-

factured and compared within small-signal con-

ditions in Fig.3.30 (bottom). All show a slightly

different behaviour with respect to the frequency,

as well as the amplitude. Nevertheless, the aim

to produce working samples within the specified

frequency range of Fup {13.75- 14.5 GHz}has been

achieved.

Large-Signal Measurements

Large-signal measurements in the Ku-band suffer

from high losses and in consequence high mea-

surement uncertainties. To lower the losses and en-

hance the accuracy, a measurement setup based on

high directivity WR75 waveguide - couplers (ATM)

was used. The CW input is generated with a mi-

crowave synthesized source (E8254A) and boosted

with a first pre-amplifier (ZVE-3W-183+) as well

as a second one (previously developed [Maa+16a])

(Fig.3.31) to be able to put the DUT in saturation.

The input and output power levels of the DUT

were measured with a power meter (E4412). A

Chapter 3. Power Amplifier

(a)

(b)

(c)

(d)

FIGURE 3.29: Realisation of the amplifier. Side-view il-

lustration of the MIC (a). Top view of the MIC (b). X-Ray

pictures of the bare-die Q1 (c), Q2 (d).

non flat pre-amplification is compensated by a

Matlab TM controlled measurement system to hold

the DUT in a reproducible thermal compression.

Both gate currents were monitored separately to

indicate the compression level. Automatic short

intermissions were used in the measurement setup

to lower thermal self heating. The setup was cali-

brated to the SMA reference plane RefSMA. After-

wards, the results were de-embedded to RefGSG

based on the known offset from the small signal

measurements (Section3.3.5).

The PA is characterised versus input power for

all frequencies between 13.5-14.6GHz within a

dynamic range of 24dB. From Fig.3.32 it can be ob-

served that the compression behaviour of the mea-

surement is equal to the simulation for 14.2GHz.

A constant decrease in gain for the Class-AB be-

haviour needs to be stated. With a Class-C biasing

the gain could have been lowered down to 15dB

(a)

(b)

FIGURE 3.30: Comparison between measured (sample

#1) and simulated small-signal behaviour of the ampli-

fier (VDS1,2 =40V; IDq1,2 = 300 mA) (a). Comparison be-

tween six measured amplifiers within small-signal con-

dition (VDS1,2 =40V; IDq1,2 = 300 mA) (b).

VDS2

VDS1 VGS2

VGS1

RO4003C

housing

dc supply

water cooling

pre

amp

pre

amp

RefSMA

RFin RFout

load

RefGSG RefGSG

MIC

Q1 Q2

E8254A

ZVE-3W-183

E4412

E4440A

[9]

spec

FIGURE 3.31: Large-Signal measurement setup.

in the back-off while afterwards remaining con-

stant up to Psat. The output power reaches 47dBm

about 1dB later than in simulation. The gain is

compressed to 14dB in the saturation, like in the

simulation. The PAE of the two stages is 5%less

than simulated but reaches up to 25%. This depen-

dency can be explained by the device’s self heating,

which is higher than initially simulated.

By either increasing the Rth of the model, or the

base temperature, the higher self heating in the

measurement can be explained. Moreover, this is

proven by thermal images shown in Sec.3.3.5. The

six manufactured amplifiers were measured in

their large-signal behaviour. They all demonstrate

an equal peak output power with respect to the fre-

quency shift seen in Fig.3.30 (bottom). In Fig.3.33

a reasonable agreement between simulation and

Chapter 3. Power Amplifier

FIGURE 3.32: Comparison between measured and sim-

ulated large-signal behaviour of the two-stage amplifier.

Power-sweep at 14.2GHz (VDS1,2 = 40 V; IDq1,2 = 300 mA).

13.5 13.75 14 14.25 14.5 14.75

frequency in (GHz)

Gain (dB), PAE (%), Pin (dBm), Pout (dBm)

Pout

Pout sim

Gain

Gainsim

PAE

PAEsim

Pin sim

FIGURE 3.33: Comparison between measured and

simulated large-signal behaviour over frequency

(VDS1,2 =40V; IDq1,2 = 300 mA).

measurement can be noted over frequency. The

ripple in the frequency range of interest is ±0.6dB.

Thermal Analysis

A thermal imaging of the fixture was taken during

a CW-measurement in the dark to monitor the sur-

face temperature of the bare-die. The surface re-

flection coefficients (εIR) for IR light vary over the

different materials. With a constant temperature of

a heated up fixture, the bare-die coefficient on top

of the passivation was analysed to be εIR(Die) =0.34

and the flange εIR(flange) =0.5. The thermal differ-

ence between the surface of the Si passivation and

the channel itself is ∆T,pCH(V) ≈40-60 K.

(a) (b)

FIGURE 3.34: Comparison between measured (a)

and simulated (b) thermal behaviour (VDS1,2 =40V;

IDq1,2 =300mA; Pout,avg =40W).

From Fig.3.34 the channel temperature can be cal-

culated for Pout =40W to TCH,avg ≈228◦C with

TCH,peak ≈280◦C. The total thermal resistance of

the junction to the sink can be calculated to:

R∆JS =TCH −Tflange

Pdc −PRF =228◦C−24◦C

176 W−40 W= 1.5K

(3.31)

The thermal measurement is in a good agreement

with the finite element method (FEM) thermal sim-

ulation based on CST TM from Fig.3.34(b). Never-

theless, the thermal conductivity of the mount-

ing is too low for higher output power levels.

For Pdiss ≥80W a self heating occurs within the

CW measurement. To achieve lower thermal re-

sistances, modern mounting technologies with

plated diamond [Han+15] as well as silver sin-

tering [Baj+15] can be used in future work.

Modulated Measurements

The parameters previously analysed in CW excita-

tion, like Psat or P1dB, are insufficient for describing

the non-linear behaviour of an amplifier for opera-

tions in multi-carrier modes. This is why, AM-AM

as well as AM-PM conversion, were chosen as the

first set of valuable performance data. Compared

to TWTAs, the premature gain compression of

the GaN-HEMT is a highly non-linear behaviour

(compare Fig.3.32). Within this work, effort has

been made to compensate this compression simply

through the biasing. For applying a gate volt-

age to the power amplifier Q2 in deep Class-AB

IDq2 =50mA instead of IDq2 =300mA while hold-

ing the pre-amplifier Q1 in the biasing conditions

Chapter 3. Power Amplifier

0 0.25 0.5 0.75 1

normalized input magnitude

Gain (dB)

300 mA

50 mA

(a)

0 0.25 0.5 0.75 1

−40

−20

normalized input magnitude

Phase shift (degree)

300 mA

50 mA

(b)

FIGURE 3.35: Measured gain compression (a) and AM-

PM conversion (b) with a 32APSK modulation (α=0.25;

16MSym/s) at an un-linearised amplifier for 14.25GHz.

(VDS1,2 =40V; IDq1 = 300 mA; IDq2 = {300; 50} mA).

−1 0 1

−1

(a)

−1 0 1

−1

(b)

−1 0 1

−1

(c)

FIGURE 3.36: Measured modulation schemes of com-

mon SatCom signals for Pout, peak -PAPR, 14.25GHz.

(a) QPSK (α=0.35; 16MSym/s; DVB-S1) (b) 32APSK

(α=0.25; 16 MSym/s; DVB-S2) (c) 64APSK (α=0.05;

16MSym/s; DVB-S2X).

of max gm (IDq1 =300 mA) results in a lowered

small-signal gain (Fig.3.35(a)). This AM-AM and

AM-PM analysis were carried out with modulated

signals to lower errors of a thermal self-heating.

In Fig.3.35(b) it can be noticed that this biasing

also linearises the AM-PM conversion to a lower

phase variation, the maximum can be depicted

with 1.6◦/dB. Additionally to AM-AM and AM-

PM conversion the spectrum regrowth, measured

by the adjacent channel power ratio (ACPR), is an

important indicator of a linear amplifier operation.

Furthermore, the error vector magnitude (EVM)

is a comprehensive measure of the quality of the

transmitter. A QPSK modulation with a peak to

average power ratio (PAPR) of 3.9dB and a roll-off

factor α=0.35 was chosen to represent the classical

DVB-S signal (Fig.3.36(a)). The increasing demand

of data leads to higher order modulation schemes

(up to 32APSK) that were defined in the DVB-S2

standard (Fig.3.36(b) PAPR=5.6). Additionally,

the roll-off factor was lowered to α=0.25 to en-

hance the spectral efficiency. The newly defined

DVB-S2X standard allows modulation schemes

FIGURE 3.37: Output spectrum of the PA

for Pout,avg =30W and a QPSK signal with

16MSym/s; α=0.35 (w) and (w/o) a RFPAL at

14.375GHz (VDS1,2 =40V; IDq1 = 300 mA; IDq2 = 50 mA;

RBW=200kHz; RMS; VBW=10MHz; 300 ms sweep;

100MHz span).

up to 256APSK with a sharp roll-off factor down to

α=0.05. The decreased αparticularly leads to high

PAPR of up to 6.42dB for a 64APSK with α= 0.05

(Fig.3.36(c)). The spectral mask depends on the sig-

nal bandwidth and is defined in the ETSI standard

[Eut]. Linearisation was performed with a digital

pre-distortion (DPD) that was able to reduce the

out-of-band energy and enhances the efficiency by

compensating non-linearities like AM-AM, AM-

PM as well as memory effects. As an alternative an

IF pre-distortion directly in the block up-converter

(BUC) path was used by the method described in

[Maa+15a] called RF PA linearisation (RFPAL) that

is explained later on in Sec.4.3. Both techniques

show equal performance levels and can be used

either in the BUC (RFPAL) or in the modulator

(DPD).

In Fig.3.37 the resulting output spectrum of the

FIGURE 3.38: Measurement results for a QPSK signal

with 16MSym/s; α=0.35 and a RFPAL at (VDS1,2 =40V;

IDq1 =300mA; IDq2 =50mA).

Chapter 3. Power Amplifier

TABLE 3.5: Linearity measurements for various modulation schemes

MOD f0Pout,avg Pout,pk PAPR PAE ηACPR (dBc) EVM

(GHz) (W) (W) (dB) (%) (%) w/o w w (%)

QPSK 13.75 30 73.5 3.9 23 31 31 42 3.2

α=0.35 14.00 30 73.8 3.9 21 29 35 48 3.5

14.25 30 74 3.9 23 31 32 44 3.6

DVB-S 14.50 30 70.5 3.7 22 30 30 39 3.8

32APSK 13.75 20 62 4.9 23.8 31 21 39 2.8

α=0.25 14.00 20 64 5 22.3 28 25 41 3.5

14.25 20 65 5.1 22.4 30.2 27 41 3.2

DVB-S2 14.50 20 64.7 5.1 21.7 29.8 26 40 3.3

64APSK 13.75 16 68.3 6.3 22.7 30.2 22 31 6.5

α=0.05 14.00 16 64 6.0 20.3 28.9 26 37 4.5

14.25 16 68.3 6.2 20.3 28.9 26 35 6.3

DVB-S2X 14.50 16 68 6.3 19.7 28 23 34 6.5

PA for a QPSK and an average output power

Pout,avg =30W at 14.375GHz can be seen. It can be

noted that the amplifier can hardly reach the spec-

ifications in band as well as the required shoulder

distance without (w/o) pre-distortion. The side-

lobes cross the mask restrictions. However, the

spectrum mask is easily fulfilled with (w) the RF-

PAL.

Modulated measurements over frequency are visu-

alized in Fig.3.38 which takes advantage of the

RFPAL for fulfilling the mask. Depending on

the measured output crest factor the peak output

power (Pout,peak) can be calculated. It can be noted

that Pout,peak ≥70W is much higher than Pout,avg

during the CW measurements. The lower aver-

age power does not produce that much dissipated

power and results in lower thermal stress for the

devices. Consequently, self heating, that limits the

output power, is lowered. The high output power

results in an acceptable PAE of ≈20% over the

Ku-band. The calculated drain efficiency is with

ηQ2 ≈30% as high as intended in the simulation,

while the EVM is lower than 6%. Tab. 3.5 shows

the linearity measurements for various modula-

tion schemes, all with constant 16 MSym/s. It

can be noted that with a higher order modulation

scheme and a decreased αthe Pout, avg needs to

be decreased as well to fulfil the mask. Neverthe-

less, high PAE can be achieved even in the deep

back-off of the higher order modulation schemes

(32APSK, 64APSK). This depicts the possibilities

for high-data rate transmission in VSATs.

3.3.6 Summary

In this section, an extensive design procedure for

an efficient two-stage GaN-HEMT PA in the Ku-

band has been presented. A Load/Source-Pull

methodology has been used with a systematic de-

sign approach to develop the matching circuits. Ef-

fort was spent for EM-modelling of the matching

circuits to reduce the effects of manufacturing con-

straints. The procedure has later been validated by

implementing the two stage PA based on two 70W

bare-die GaN-HEMT devices.

Simulated and measured results of this PA show a

very good agreement. Large-signal measurements

(CW) show more than 50 W output power in the

desired frequency range of interest with more than

23% PAE. These results were achieved while main-

taining a high gain of ≥15dB. Linearised mod-

ulated measurements using a 16MSym/s QPSK

(DVB-S) signal demonstrate an average PAE of

21% by more than 30W output power (70W peak)

while holding the linearity requirements. More-

over, higher order modulation schemes 32APSK

(DVB-S2), 64APSK (DVB-S2X) were tested and

state 20 and 16W output power with a PAE of

≥21%. Different manufactured amplifiers show

only a small variation in their performance data.

Chapter 3. Power Amplifier

3.4 Lower Ku-band MIC PA

To further prove the methodology used in the pre-

vious chapters the design has been changed to a

working adaptation that should provide an equal

output power in the frequency range of 12.75-

13.25GHz (Flow) and is going to be published in

[Maa+op]. This range can also be used for broad-

cast uplink but not all transponders support its

range. Its intended in several countries for provid-

ing advanced broadcasting services like UHDTV.

Within, higher order APSK modulations are used

to increase the data-rate of up to 100MBit/s per

transponder.

3.4.1 PA Design Approach

The design needs to fulfil the same mechanical di-

mensions (18.7x12.5mm) as the previously men-

tioned upper Ku-band amplifiers to ease an in-

tegration within the test-setup. A lowered cen-

tre frequency of 1GHz extends the mechanical

length of a λ/450ΩMS-line within 0.17mm (λ/4

at 14GHz=2.12mm; λ/4 at 13 GHz = 2.28 mm).

By fulfilling the limitations of mechanical dimen-

sions the electrical lengths of the matching circuits

needs to stay constant. In addition, the lowered

operation frequency should exceed the previously

achieved efficiency values based on:

•higher simulated PAE (Tab. 3.3)

•higher optimum impedances and therefore

more easy matching circuits

•lowered electrical losses (αc, αd, αr)

Nevertheless, the low gain of the devices around

13GHz needs to maintain the two-stage design

with both equal devices as described in Sec. 3.3.1.

3.4.2 Design of Matching Networks

As a first approach the meandering of the 3to 1

combiner section has been changed, which as a

result shrinks its mechanical dimensions. Sec-

ondly, the coupling capacitors at all IMN, ISMN

as well as OMN were increased, which increases

a pre-transformation. Based on layout constraints,

the number of fingers cannot be scaled. As a re-

sult, only the finger lengths were enlarged. An

increased capacitance results in a lowered SRF,

which may affect the tolerance dependency of the

whole circuit. As a validation of not exceeding

the SRF of the Interdigital capacitors, its quality

factor can be utilised. To lower the dependency

of bond-wire tolerances the number of bond-wires

were increased to three per pad. This does not

lower the inductance by a factor of 2/3 - EM sim-

ulations showed a total resulting inductance of

LBond =11pH due to the higher mutual coupling of

the wires. The total schematic of the two-stage am-

plifier is given in Fig.3.39(a) showing only minor

changes to the previous design. The open stubs at

the IMN and OMN were changed in position to-

wards the 50ΩMS-line position. Furthermore, the

length of the pre-transformation line (TL3) behind

the capacitor Cimn at the input side is exceeded.

3.4.3 Simulation Approach

Small-Signal Analysis

The matching networks are simulated like in the

previous section using parametrized EM-models

of all sub-circuits. The simulated S-Parameters of

the matching networks are shown in Fig.3.39(b-d).

The ports of the simulation are loaded with the

optimum impedances that were analysed within

the preliminary Load-Pull analysis. For instance,

the simulation of the IMN consists of a 50Ωport

(Z0) that represents the RFin with a reflection co-

efficient (S11) shown in Fig. 3.39(b). The opposite

facing term is the gate-side of the transistor with

its optimum source impedances loaded to the port

(ZS IMN) resulting in a reflection coefficient (S22).

The transmission parameter (S21) represents a

transmission ratio of the real to complex transfor-

mation network IMN. A low reflection coefficient

paired with low IL can now be applied to the sim-

ulation tool as a design goal. These S-Parameters

are shown for all three networks (IMN, ISMN,

OMN) where a reflection coefficient of ≤-10dB can

be obtained for all networks. Furthermore, the

Chapter 3. Power Amplifier

(a)

12 12.5 13 13.5 14

−40

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−4

−3

−2

−1

Transmission (dB)

S22

S11

S21

(b) IMN

12 12.5 13 13.5 14

−40

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−4

−3

−2

−1

Transmission (dB)

S22

S11

S21

12 12.5 13 13.5 14

−40

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−4

−3

−2

−1

Transmission (dB)

S22

S11

S21

(d) OMN

FIGURE 3.39: (a) Schematic of the proposed two-stage amplifier divided into three matching circuits (IMN, ISMN,

OMN). Each transmission line (TL) is parallelised by n-times written underneath in green. Simulated EM-based

s-parameters while the ports are loaded with the conjugate optimum impedances for (b) IMN (c) ISMN (d) OMN.

transmission losses are ≤1dB which consists of

a mismatch as well as electric losses (αc, αd, αr).

It can be obtained that the extremely low ohmic

input impedances are hard to match, resulting in

a lower matching compared to the output side

that achieves a RL of up to 20dB (Fig. 3.39(d)).

The designed circuits were later analysed towards

their phase and amplitude imbalance considering

the transistors as transistor cells. The values of all

schematic elements are shown in Tab.3.6. The

Re{Z} (Ohm)

Im{Z} (Ohm)

0.2 0.4 0.6 0.8 1

1.5

2.5

PAE

ZL ISMN

ZL OMN

Pout

FIGURE 3.40: Simulated EM-based impedances realised

by the matching circuits from 12.5- 13.5 GHz (Flow) for

the output sides of Q1(ISMN) and Q2(OMN). The plot-

ted MuFLoCs represent the minimum value over the de-

sired frequency range Flow.

TABLE 3.6: Schematic values of the proposed two-stage

amplifier for f0=13GHz

IMN TL1TL2TL3TL4TL5

Φ 96◦108◦66◦74◦31◦

ZT L 47 Ω 12.5 Ω 5.6 Ω 3.3 Ω 25 Ω

ZT L xn47 Ω 37 Ω 53.1 Ω 28 Ω 50 Ω

Cimn =0.39pF QCimn =39 LBond =11pH

ISMN TL6TL7TL8TL9

Φ 84◦59◦52◦77◦

ZT L 5.3 Ω 6.5 Ω 6.6 Ω 3.4 Ω

ZT L xn35.6 Ω 33.7 Ω 37.6 Ω 28.6 Ω

Cismn =0.33pF QCismn =38.7 LBond =11pH

OMN TL10 TL11 TL12 TL13 TL14

Φ 82◦21◦105◦96◦22◦

ZT L 3.3 Ω 9.1 Ω 13 Ω 47.5 Ω 25 Ω

ZT L xn27.6 Ω 53.1 Ω 28 Ω 47.5 Ω 50 Ω

Comn =0.83pF QComn =38 LBond =11pH

realised impedances of the output matching net-

works are optimized towards the MuFLoCs within

the frequency range Flow. Fig.3.40 shows the re-

alised impedances for the OMN (ZL OMN) that are

located within the Pout =47dBm contour. More-

over, the OMN impedances fit into the PAE = 39%

contour. In contrast the load of the ISMN (ZL ISMN)

is realised with a far wider spread cutting the

Chapter 3. Power Amplifier

0 0.2 0.4 0.6 0.8 1 1.2

Pout (W)

Time ( s)

Pin (W)

Pout

overshoot

FIGURE 3.41: Simulated pulsed RF-behaviour of the am-

plifier for 10% duty cycle with 1µs period at 13 GHz.

PAE= 29% contour. The results demonstrate a

compromise due to the different directions of the

imaginary trajectories of both facing impedances

(ZL ISMN, ZS ISMN).

Large-Signal Analysis

The Large-Signal analysis is performed with CW

as well as pulsed RF-signals. The pulse signals

are used to analyse the thermal compression of the

devices and lower the self-heating. Fig.3.41 shows

the simulated RF response at 13GHz with a slight

overshoot at the beginning of the pulse. The high

output power of up to Pout =75W demonstrates

the good output matching. The structure is anal-

ysed within large-signal conditions and shows an

almost equal output power within Flow. During

large-signal simulations it turns out that the inher-

ent AM/AM soft-compression of the GaN-HEMT

can be easily compensated by lowering the quies-

cent current of Q1towards a Class-B operation.

This can be explained by the highly non-linear ac-

transconductance of the device with its maximum

at IDq =300mA at this high frequency operation.

This lowering of the quiescent current of Q1down

to 100mA comes along with a further increased

mismatch in the ISMN that flattens the overall

AM/PM as well as explained in detail in [Qua+14].

3.4.4 Realisation

The bare-dies and substrates were aligned and

mounted on a thick CuMoCu-flange (Fig.3.42(a)).

The wedge-wedge bond-wire interconnections

(a)

(b)

(c)

(d)

FIGURE 3.42: Realisation of the amplifier. Side-view il-

lustration of the MIC (a). Top view of the MIC (b). X-Ray

pictures of the bare-die Q1 (c), Q2 (d).

were designed to be three in parallel to lower the

tolerances of the resulting inductance. A top view

of the mounted MIC can be seen in (Fig.3.42(b)).

The die-attach was again analysed via X-Ray mi-

croscopy (Fig.3.42(c),3.42(d)) to circumvent ther-

mal problems. A grinding pattern of the mounted

bare-die was done and shows a thickness of the

mounting of 18µm.

3.4.5 Measurement Results

Small-Signal Measurements

Probed small-signal measurements were perfor-

med with 500 µm pitch probes (|Z|-ProbeTM) on

the alumina substrate using a network analyser

(N5230A). In Fig.3.43(a) a comparison between

simulation and measurements of the amplifier can

be seen. The probe alignment was checked by

changing the position of the probes several times.

Chapter 3. Power Amplifier

This only affects the transmission phase of the

measured small-signal measurements within ±6◦.

The measurement shows a slightly different trans-

mission compared to the simulation resulting in a

narrower band-pass behaviour. The gain can be

determined to be 21dB at the centre frequency of

13GHz and within the in-band frequency range

Flow. By applying the Monte-Carlo tolerance anal-

ysis of Tab.3.2 the bond-wire tolerances clearly

indicate the small deviations between simulation

and measurement. To further clarify the depen-

dency of the amplifier over various biasing con-

ditions Fig.3.43(b) shows the S-Parameters for

IDq1,2 ={10/10; 50/50; 150/150; 300/300}mA bias-

ing of both amplifier stages Q1/Q2.

It can be seen that the biasing conditions of IDq1,2 =

{150/150}mA nearly achieves the 20dB small sig-

nal gain while IDq1,2 ={50/50}mA only results

in 10dB gain. Fig.3.43(c) visualizes the depen-

dency to the supply voltage varying from VDS1,2 =

{25; 30; 35; 40; 45}V. A huge decrease in gain as

well as in matching can be observed by lowering

the supply voltage to VDS1,2 ={25}V.

Large-Signal Measurements

The CW measurement setup of the last section

(Fig.3.31) has certain drawbacks:

•Firstly, the interconnection between the MIC

and the surrounding RO4003c substrate was

realised via a wide ribbon bond. The height

and distance of the ribbon interconnection in-

fluence the input as well as output matching

of the MIC and therefore cause additional

mismatch losses. A de-embedding of this

structure is only possible by measuring a suit-

able reference structure and de-embedding

its losses from the measured DUT.

•Secondly, the measurement of the DUT within

the CW state is difficult due to self-heating.

This affects not only the DUT but also the

pre-amplifier stages that are driven into com-

pression due to the high losses of the sur-

rounding RO4003c substrate.

12 13 14 15 16

−20

−10

Frequency (GHz)

S−Parameters (dB)

S11

S21

S11 meas

S21 meas

S11 monte

S21 monte

(a)

12 13 14 15 16

−20

−10

S−Parameters (dB)

Frequency (GHz)

S21 300/300

S21 150/150

S21 50/50

S21 10/10

S11 300/300

S22 300/300

(b)

12 13 14 15 16

−20

−10

S−Parameters (dB)

Frequency (GHz)

S21 45V

S21 40V

S21 35V

S21 30V

S21 25V

S11 45V

S22 45V

(c)

FIGURE 3.43: (a) Comparison between measured

and simulated small-signal behaviour over frequency

(VDS1,2 =40V; IDq1,2 = 300 mA) with additional Monte-

Carlo analysis (b) Measured small-signal behaviour

in dependency to IDq1,2 (VDS1,2 =40V) (c) Measured

small-signal behaviour in dependency to VDS1,2

(IDq1,2 =300mA).

To prevent an unwanted pre-matching of the sur-

rounding substrate, GSG-probes can be used, as

already done in the small-signal measurements.

A special series of GSG-probes were used that

are able to withstand up to 25W average output

power (GSG-500 |Z|-ProbeTMPower at 10 GHz). To

lower interconnection losses the probes were di-

rectly connected to the WR75 directional couplers

with low loss semi-rigid cables. The measurement

setup can be seen in Fig.3.44 while the MIC is still

Chapter 3. Power Amplifier

VDS2

VDS1 VGS2

VGS1

RO4003C

housing

dc supply

water cooling

pre

amp

RefGSG

RFin RFout

load

MIC

Q1 Q2

E8254A

ZVE-3W-183

NRP-Z85

E4440A

NRP-Z85

spec

FIGURE 3.44: Probed Large-Signal measurement setup.

located within the test-bench for feeding dc and

water cooling.

To lower the self-heating of all devices the DUT is

measured within pulsed RF conditions. The signal

generator (KeysightTME8254A) can be driven to

duty cycles of as low as 10% which means that the

full amount of input power is only given during

10% of a period of 1µs. The pulsed RF power is

measured at the input as well as the output of the

DUT via the WR75 directional couplers by peak

power meters (R&STMNRP-Z85). At the output

side, an additional low pass filter is located in be-

tween the coupled port of the directional coupler

and the power meter. This is due to the fact that

a wave-guide reacts as a high-pass filter begin-

ning from its cut-off and not, as often suggested,

as a bandpass filter. The coupling port is going

to overestimate the amount of power by the 2nd

harmonics within 11dB (-29dB coupling) to the

fundamental (-40dB coupling). Due to the low-

ered interconnection as well as input losses of this

measurement setup, compared to the previous one,

an additional pre-amplification after the pre amp

is no longer necessary.

Firstly, the probed power measurement setup is

calibrated by probing a TL while inserting a pulsed

power sweep over frequency. The output power is

compared with the input power and fulfils the con-

ditions of equality considering the losses of the TL.

The measured average output power Pout,avg repre-

sents the integrated RF power during the period.

Moreover, peak output power Pout,pk represents

the peak value of power that is only present dur-

ing the, for example, 10% duty cycle of the period.

For this reason, it has to be mentioned that the

peak value is not equivalent to eventual positive

0 5 10 15 20 25 30 0

Pin (dBm)

Gain (dB), PAE(%), Pout (dBm)

Pout,pk

Pout,pk sim

Pout,avg

Pout,avg sim

PAE

PAE sim

Gain

Gain sim

(a)

12.25 12.5 12.75 13 13.25 13.5 13.75

Frequency (GHz)

Gain (dB), PAE(%),Pout (dBm)

Pout,pk

Pout,pk sim

Pout,avg

Pout,avg sim

PAE

PAE sim

Gain

Gain sim

(b)

FIGURE 3.45: Comparison between measured and sim-

ulated pulsed RF-behaviour (a) over the input power

level at 13GHz and (b) over frequency (VDS1,2 =40 V;

IDq1,2 =300mA).

or negative overshoots. They are filtered during

a timing offset. The peak output power Pout,pk is

consequently equivalent to the pulse top power.

The measured large-signal behaviour of the MIC is

shown in Fig.3.45(a) for a power-sweep at 13GHz.

Secondly, the duty cycle is defined with 10% for

1µs period. The measurement shows a slightly

later compression than the simulation and exceeds

the power level of the simulation at 13GHz. The

PAE shows a discrepancy in the back-off of the

measurement to that of the simulation. In addition,

the output power is slightly less than simulated in

the back-off which results in a lowered gain and a

lower PAE.

The saturated output power demonstrates a great

fit to the simulation shown in Fig.3.45(b). The

measured frequency response has a more narrow

bandwidth compared to the simulation, still per-

forming within Flow. An extremely high peak out-

put power of up to 82W with ≥30% PAE demon-

strates the great achievements. The pulsed power

Chapter 3. Power Amplifier

17 20 23 26 29 32 35

Pin (dBm)

Gain (dB)

50,50 mA

100, 300 mA

300, 100 mA

300, 300 mA

Pin, 1dB (300,300)

Pin, 1dB (100,300)

(a)

17 20 23 26 29 32 35

Pin (dBm)

PAE (%)

50,50 mA

100, 300 mA

300, 100 mA

300, 300 mA

(b)

12.2 12.4 12.6 12.8 13 13.2 13.4 13.6 13.8

Frequency (GHz)

PAE (%), Pout,pk (W)

50,50 mA

100, 300 mA

300, 100 mA

300, 300 mA

(c)

FIGURE 3.46: Measured pulsed RF-behaviour at

13GHz(a) gain (b) PAE (c) saturated output power and

PAE for various biasing conditions of (Q1,Q2) (10% duty

cycle VDS1,2 =40V).

measurements makes it possible to get a deeper

insight of the typical GaN-HEMT soft compres-

sion, which can be observed in Fig. 3.46(a). The

pulsed RF-signal lowers the thermal compression

of the devices – the compression behaviour shown

is therefore mainly related to the current collapse.

The pre-amplifier (Q1) is realised via a device

which is far too large feeding the amplifier (Q2).

However, the quiescent current of this stage (Q1)

can be lowered while still achieving enough drive

level for the PA (Q2). As a result, an almost

flat gain compression can be realised with the

quiescent current conditions of (100, 300 mA).

This technique can be easily applied resulting

in a 1dB compression point of Pin 1dB =32 dBm

with Pout 1dB = 70 W at 13 GHz. The lowered qui-

escent current improves the PAE of the amplifier

as can be observed in Fig.3.46(b) with up to 10%

towards 30%. The effects of this quiescent cur-

rent correction over frequency are demonstrated

in Fig.3.46(c) showing that the saturated output

power is less influenced while the PAE exceeds the

30% over frequency.

3.4.6 Summary

In this section the design procedures of the previ-

ous amplifier were once again applied, while the

frequency range was lowered within 1GHz. The

resulting two stage PA was manufactured and its

performance shows a great agreement to the sim-

ulation. It was possible to improve the measure-

ment setup to a probed pulsed power setup which

exceeds the measurement accuracy and lowers the

thermal compression of the DUT. The PA shows a

high gain of 17dB with a Pout 1dB = 70 W and up to

80W output power. An increased PAE of ≥30%

was obtained through this.

Chapter 3. Power Amplifier

3.5 Extended Ku-band MIC PA

To further clarify the bandwidth limitations of the

transistor, a design should exceed the frequency

range of both previously designed amplifiers to

12.75-14.5GHz (Fext), which is 14% FBW. This de-

sign can be used within all Ku-band uplink chan-

nels fulfilling the lower Flow as well as the upper

Fup frequency range and is published in [Maa+18].

3.5.1 PA Design Approach

During the design process of the previously men-

tioned amplifiers two factors limits the bandwidth

and as a result the power-match of the amplifiers:

1. The analysed limitations towards a broad-

band impedance match are mainly related to

the extremely low matching impedances. To

lower these restrictions the load resistance

can be increased by simply increasing the

supply voltage (compare Eq.3.1). The intrin-

sic breakdown voltage (VBD ≥100V) is the

boundary that could not be exceeded. An

increase of the supply voltage comes along

with a lowered efficiency, which needs to be

taken into account during the design.

2. The first pre-transformation of the matching

networks is always caused by an inductance

that represents the bond-wires. This induc-

tance transforms the optimum load impe-

dance, mainly a capacitive load, crossing the

quality-factor circles within the Smith Chart.

As already shown in Fig.3.9(b) a low induc-

tance interconnection to the matching circuit

clearly eases the FBW of the matching. The

inductance of this bond-wires can be lowered

due to paralelizations down to a number of

three in parallel. Afterwards, the mutual cou-

pling of the bond-wires no longer decreases

its inductances. To accommodate these lim-

itations, ribbon-bond-wire interconnections

might be a solution.

Consequently, the theoretical bandwidth limita-

tions related to the Bode Fano equations (Sec.3.2.3)

0 5 10 15 20 25 30

−25

−20

−15

−10

−5

FBW (%) for the Output

rel. matching (dB)

VDS=40 V 10 GHz

VDS=50 V 10 GHz

VDS=40 V 13.2 GHz

VDS=50 V 13.2 GHz

FIGURE 3.47: Analysed theoretical matching limit (Bode

Fano) of the complex Zout{Rdc;CDS;Lpad}(bottom) impe-

dances for various supply voltages at f0=13.2GHz.

are analysed again for an increased Rdc that is re-

lated to the VDS = 50 V supply and a lowered

Lbond =9pH by the usage of ribbon-bond-wires.

Fig.3.47 displays the increased theoretical FBW

to 14% for a rel. matching of 8dB at the new

f0=13.2GHz.

3.5.2 Design of Matching Networks

The load-pull analysis given in Sec.3.2.4 has been

extended to an increased supply voltage of VDS =

50 V, as well. Furthermore, the quiescent current

was lowered to IDq = 100 mA to improve the ef-

ficiency performance as well as flattening the pre-

mature compression of GaN-HEMTs. Based on the

techniques to build the least-intersection over var-

ious load-pull contours given in Sec.3.2.4 it was

also applied for the changed biasing conditions at

this extended frequency range (Fext).

3.5.3 Simulation Approach

Small-Signal Analysis

The techniques for designing the matching net-

works are already described in the previous sec-

tions. The same schematic as for the Kulow MIC

has been used here again (Fig.3.39(a)). The bond-

wire interconnection of the Q2-OMN has been

analysed to be as low inductive as possible. There-

fore two parallel ribbon bond-wires per pad were

chosen, both with 100 µm width. The structure

Chapter 3. Power Amplifier

45 45

Re{Z} (Ohm)

Im{Z} (Ohm)

0 0.2 0.4 0.6 0.8 1

1.6

1.8

2.2

2.4

2.6

PAE

Pout

Pout 40V

ZL ISMN

ZL OMN

FIGURE 3.48: Simulated EM-based impedances realised

by the matching circuits from 12.5- 14.5GHz (Fext) for

the output sides of Q1(ISMN) and Q2(OMN). The plot-

ted MuFLoC represent the minimum value over the de-

sired frequency range Fext at VDS1,2 =50 V.

was analysed within full 3D-EM simulations re-

sulting in a extremely low equivalent inductance

of only LBond =9pH for 24 parallel ribbon. Based

on this value, the OMN was developed to fulfil the

requirements of the MuFloC within Fext.

The dc-feed circuits were changed to the new oper-

ation frequency by changing the λ/4 to its equiva-

lent at f0. As can be seen in Tab.3.7 the matching

Interdigital capacitors Comn are like in the Kulow

design while the length and impedances of the

TL are corrected to the extended bandwidth Fext

and the lowered inductance of LBond. The realised

impedances of the developed OMN are shown in

Fig.3.48 in comparison to the VDS= 50 V MuFLoCs.

In addition, one MuFLoC power contour is dis-

played, representing the optimum impedance area

for the VDS= 40 V operation. It can be noted that

the area is much smaller and less inductive in com-

parison to the VDS= 50 V operation contours for

Pout =47dBm. It was not possible to develop the

OMN with such a high transformation ratio to

achieve all realised impedances (ZL,OMN) within

the Pout =47dBm contour. Nevertheless, they fit

within the Pout =46dBm contour holding ≈25%

PAE. The output side of the ISMN (ZL,ISMN) is even

worth fitting within the Pout =46dBm contour rep-

resenting a compromise to the input match of the

ISMN ZS,ISMN. All transmission and reflection

coefficients of the matching circuits can be seen

in Fig.3.49. Within this simulation, all ports were

once again loaded with the optimum impedances

for a power match based on the new Load-Pull

analysis considering the VDS= 50 V operation. The

transmission parameter (S21) of the IMN shows

almost doubled losses in comparison to the previ-

ously developed Kulow MIC. Moreover, the real to

complex match can only be clarified to a RL≈8dB.

In addition, the matching decreases towards the

higher frequency edge of Fext which explains the

increased losses. The ISMN shows slightly in-

creased losses in comparison to the Kulow MIC

with a tolerable match of up to RL≈10 dB. The

OMN can take advantage of its lowered bond in-

ductance and achieves a good power match of up

to ≈12dB with a small resonance in the transmis-

sion losses at 14.2GHz.

The extended FBW of Fext leads to an increased

asymmetry of the bus bar. To prevent a phase im-

balance within the n-times sections of the ISMN

the Interdigital coupling capacitors were designed

with an unsymmetrical number of fingers across

the positions, as can be seen in the picture of

the realised MIC (Fig.3.51(a)). This means that

both outer and inner capacitors of the n=6 sec-

tion were realised with only 3 fingers resulting in

Cismn1 =0.038pF. Two different capacitors with 5

fingers (Cismn2 =0.074pF) flatten the phase imbal-

ance of all cells (Q2.1-Q2.12) to ±6◦. The resulting

total capacitance is Cismn =0.3pF (Tab.3.7).

TABLE 3.7: Schematic values of the proposed two-stage

amplifier for f0=13.25GHz

IMN TL1TL2TL3TL4TL5

Φ 96◦108◦68◦75◦31◦

ZT L 47 Ω 12.5 Ω 6.9 Ω 4.2 Ω 25 Ω

ZT L xn47 Ω 37 Ω 39.8 Ω 27 Ω 50 Ω

Cimn =0.33pF QCimn =49 LBond =11pH

ISMN TL6TL7TL8TL9

Φ 81◦55◦24◦81◦

ZT L 4.2 Ω 7.9 Ω 6.5 Ω 3.4 Ω

ZT L xn35.5 Ω 45 Ω 37.5 Ω 28.3 Ω

Cismn1 =0.038pF QCismn1 =21 LBond =11pH

Cismn2 =0.074pF QCismn2 =48

Cismn =(2xCismn2)∥(4xCismn1)=0.3pF QCismn =30

OMN TL10 TL11 TL12 TL13 TL14

Φ 81◦46◦105◦83◦22◦

ZT L 3.3 Ω 6.2 Ω 13 Ω 40.9 Ω 25 Ω

ZT L xn27.6 Ω 35.6 Ω 28 Ω 40.9 Ω 50 Ω

Comn =0.82pF QComn =39 LBond =9pH

Chapter 3. Power Amplifier

12 12.5 13 13.5 14 14.5 15

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−6

−4

−2

Transmission (dB)

S22

S11

S21

(a) IMN

12 12.5 13 13.5 14 14.5 15

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−6

−4

−2

Transmission (dB)

S22

S11

S21

(b) ISMN

12 12.5 13 13.5 14 14.5 15

−30

−20

−10

Reflection (dB)

Frequency (GHz)

−6

−4

−2

Transmission (dB)

S22

S11

S21

FIGURE 3.49: Simulated EM-based S-Parameters while the ports are loaded with the conjugate optimum impedan-

ces for (b) IMN (c) ISMN (d) OMN.

Large-Signal Analysis

The amplifier was analysed towards pulsed RF-

operation as mentioned during the previous de-

signs. Nevertheless, CW analysis was used to

ensure a proper function of the amplifier by an

increased thermal heating. Given the increased

supply voltage, special care must be taken not to

exceed the breakdown limitations of the device

(VBD = 100 V). This breakdown voltage needs to

be interpreted as the breakdown voltage of the in-

trinsic current source. Therefore, once again, the

large-signal analysis approach of the twelve par-

allel transistor cells is employed to provide insight

within the cells (Q2.1-Q2.12). Nevertheless, this

extrinsic transistor cells needs to be de-embedded

to the intrinsic current source by compensating

the output capacitance CDS as well as pad induc-

tances Lpad. The voltage swing of all transistor cells

can be monitored (intrinsic) during a power and

frequency sweep of the pulsed RF-simulation and

is shown in Fig.3.50(a). It was obtained that the

intrinsic voltage swing is up to 10V higher than

the extrinsic one. It can be seen that some fre-

quency points at some intrinsic transistor cells are

about to reach the VBD for a high drive level of

Pin =34dBm. The model itself features a port that

indicates the channel temperature of the devices so

all temperatures of the transistor cells can be shown

in Fig.3.50(b) for saturation over frequency. The

manufacturer limits the mounting temperature to

320◦C for not exceeding the maximum channel

temperature. The simulation shows only values

0 50 100 150 200

100

Time (ps)

Voltage (V)

Q2.1

Q2.2

Q2.3

Q2.4

Q2.5

Q2.6

(a)

12 12.5 13 13.5 14 14.5 15

100

150

200

250

300

350

Frequency (GHz)

Channel temperature ( °C)

Q2.1

Q2.2

Q2.3

Q2.4

Q2.5

Q2.6

(b)

FIGURE 3.50: CW simulated (a) intrinsic voltage-

swing (b) channel temperature for saturation operation

(VDS1,2 =50V; IDq1,2 = 100 mA; Pin = 34 dBm).

up to 300◦C for the high CW saturation. An al-

most equal heat spread over the transistor cells can

be observed, indicating a good phase as well as

amplitude over the wide bare-die. Large-signal

stability was once-again ensured by the use of the

STAN TM-Tool.

Chapter 3. Power Amplifier

18.7 mm

11.5 mm

IMN ISMN OMN

Q1 Q2

(a)

(b) (c)

FIGURE 3.51: (a) Top view of the extended Ku-band MIC

(b) wedge-wedge bond-wire interconnection for Q1(c)

bond and ribbon interconnection for Q2.

3.5.4 Realisation

The bare-dies and substrates were aligned and

mounted on a thick CuMoCu-flange, as for the pre-

viously mentioned amplifiers (Fig.3.51(a)). Special

care was taken for the bond-wire interconnections

between the matching networks and the bare-die.

The realised mounting distances were measured to

calculate the best loop-height (that influences the

bond-inductance) of the wedge-wedge bond-wires

for the three interconnections (IMN-Q1,Q1-ISMN,

ISMN-Q2). Fig.3.51(b) displays a different shape

of the connection IMN-Q1(left) to the Q1-ISMN

(right). Taking into consideration, the closed posi-

tioning between Q1and Q2with this bond-arrays,

one may argue that a huge coupling between these

different stages will occur. However, the extremely

low impedance level at the input and output of the

devices paired with the flat bond-wires makes the

radiation negligible.

The output interconnection Q2-OMN is the most

critical for the increased bandwidth of Fext which

is why it was realised with 100µm wide ribbon

12 13 14 15 16 17

−20

−10

Frequency (GHz)

S−Parameters (dB)

S22

S21

S22 meas

S21 meas

S22 monte

S21 monte

FIGURE 3.52: Comparison between measured and

simulated small-signal behaviour over frequency

(VDS1,2 =50V; IDq1,2 = 100 mA) with additional Monte-

Carlo analysis.

wires, as can be seen in Fig. 4.21. These ribbon in-

terconnections were realised by the development

of a special deep access ribbon wedge that is able

to feed a 100µm wide ribbon into a sink while not

cracking the surrounding substrates. To be able to

melt this ribbon to the pads, the ultrasonic power

of a bonder (K&S 4526) needed to be further am-

plified. The resulting ribbons from Fig.3.51(c) vi-

sualises an extremely wide and low resistance in-

terconnection to the bare-die. Within this manual

bonding the risk of a bonding besides the pads is

high, due to the enlarged size of the wedge. Never-

theless, no damage to the pads or the channel was

observed.

Small-Signal Measurements

Fig.3.52 shows a comparison between the simula-

tion and the measurements of the amplifier. The in-

creased supply voltage and the reduced quiescent

current lead to almost the same small-signal gain

in the simulation like for the previous MICs. The

measurements indicate a frequency shift towards

lower frequencies within 200MHz. This leads to a

non-flat amplification behaviour with up to 22dB

gain for the lowest operation frequency while only

achieving a gain of 12dB for 14.1 GHz. By consid-

ering the tolerances of the bond-wire inductance

during a Monte-Carlo analysis, the measurements

can hardly be explained only based on this bond-

wire tolerances. Analysing the output reflection

coefficient (S22) the measurement indicates a far

higher match than simulated for its poles but not

Chapter 3. Power Amplifier

0 5 10 15 20 25 30 0

Pin (dBm)

Gain (dB), PAE(%), Pout (dBm)

Pout,pk

Pout,pk sim

Pout,avg

Pout,avg sim

PAE

PAE sim

Gain

Gain sim

(a)

12.5 13 13.5 14 14.5 15 15.5

Frequency (GHz)

Gain (dB), PAE(%),Pout (dBm)

Pout,pk

Pout,pk sim

Pout,avg

Pout,avg sim

PAE

PAE sim

Gain

Gain sim

(b)

FIGURE 3.53: Comparison between measured and sim-

ulated large-signal behaviour (a) over the input power

level at 13GHz and (b) over frequency (VDS1,2 =50 V;

IDq1,2 =100mA).

in the central area of f0. A detailed optical mea-

surement of the Interdigital fingers located in the

OMN (Comn) indicated that the finger distance

(Wgap) was ≈5µm less than simulated. This can

be explained by a layout failure resulting in an

increased finger width (Wf). An increased capaci-

tance can explain the frequency shift as well as the

asymmetry. Nevertheless, the bandwidth of the

measured amplifier is equal to its simulation.

Large-Signal Measurements

Large-signal measurements were carried out in

the probed-pulsed power setup shown in Fig.3.31.

The measured behaviour of the MIC is shown in

Fig.3.53(a) for a power-sweep at 13GHz. A good

agreement can be observed with a slightly low-

ered gain of the measurement in the deep input

back-off operation (deeper Class-AB), which leads

to a reduced PAE. The duty cycle is defined with

10% for a 1µs period. The saturated output power

is shown in accordance with the simulation in

12.25 12.5 12.75 13 13.25 13.5 13.75 14 14.25

Frequency (GHz)

PAE (%), Pout,pk (W)

50 V

45 V

40 V

Pout,pk

PAE

FIGURE 3.54: Measured saturated pulsed output power

and PAE for various supply voltages (10% duty cycle

IDq1,2 =100mA, Pin =34dBm).

Fig.3.53(b). The already observed frequency shift

of the small-signal measurements can be seen in

these large-signal measurements again. Apart

from that, the gain and, as a result, the output

power drops ≈1dB starting from 13.7GHz. De-

spite the fact that a peak output power ≥55W

can be observed in between 14% FBW. The depen-

dency to the supply voltage is displayed in detail

in Fig.3.54. The saturated output power signifi-

cantly drops for a lowered supply voltage, due to

the lower power-match. The PAE stays somehow

constant around 20% in between 12.4-14.1GHz

even for the high voltage biasing conditions, due

to the improved power-match.

3.5.5 Summary

In this section, the design procedures of the pre-

vious section were once again applied. The fre-

quency range was extended to fit both the lower

(Flow) as well as the upper (Fup) frequency range.

To ease the matching, the optimum load impedan-

ces were enlarged by increasing the supply voltage.

Furthermore, the bond-wire interconnections were

improved by ribbon bond-wires. The resulting two

stage PA was manufactured and its performance

shows a good match according to the simulation

with 200MHz frequency shift. The PA shows a

saturated gain of 15dB with a Pout ≥55W, while

a PAE of ≥20% was obtained. The FBW of this de-

sign enlarged the previous ones to 14%, which is

nearly the theoretically assumed 15% limitation of

a working busbar, as stated by [Mar+99].

Chapter 3. Power Amplifier

3.6 Efficiency Enhancement

To further improve the efficiency of power ampli-

fiers within the Ku-band, the efficiency restrictions

needed to be determined:

1. The saturation efficiency is limited by the

transistor losses, as described in Sec.2.2. The

saturation efficiency of an amplifier can be

enhanced by compensating its parasitics to

shape the overlap between the current and

voltage waveform at the intrinsic transis-

tor. This waveform engineering is realised by

switch-mode amplifiers which take advantage

of special reflection coefficients at the har-

monics of the amplifier. These techniques are

nowadays popular within the mobile com-

munication market [Cri06]. As previously

described in Sec.3.2.4, a harmonic Load-Pull

analysis has shown that the scaling of the

huge transistor bar is too wide to see an

influence of harmonic matching at the in-

trinsic waveforms. The only solution for

increasing the saturated efficiency of the am-

plifiers would be to realise a pre-matching

located more closely to the intrinsic transis-

tor. In addition, future design technologies

like 150nm GaN-HEMTs can take advantage

from a lowered on-resistance and therefore

lower losses at higher frequencies. None of

these techniques can be applied to the devel-

oped MIC’s.

2. The back-off efficiency of an amplifier is

limited by its matching. It can be enhanced

by increasing the optimum load-impedances

during the output back-off (OBO) conditions

while maintaining a low load-impedance

during saturation, known as load-modula-

tion. There are two common approaches for

changing the load impedance. It can be re-

alised by either changing the supply voltage,

which is called envelope tracking [Kah52], or

by modulating the sink and therefore the cur-

rent which is defined as a Doherty amplifier

[Doh36].

Modern DVB-S2x modulation standards have a

PAPR of up to 6dB, which means a PA is often

driven in back-off operation. Furthermore, the am-

plifier working in a satellite link needs to be driven

in an even lower output power, to gain for extra

power during a rain-margin. Common amplifier

architectures like Class-C and Class-AB suffer

from a much lower efficiency here than in satu-

ration. The techniques of enhancing the back-off

efficiency should be evaluated within this section

on the developed amplifiers.

3.6.1 Envelope Tracking

A way to change the load impedance of the tran-

sistor while working in the back-off is to change

its supply voltage as can be seen in Fig.3.48. This

way, the optimum load impedance of the transistor

decreases and saturation is achieved earlier. With

an increased signal magnitude, the supply-voltage

needs to increase as well to enhance the saturation

again [Kah52]. Hence, the so-called envelope fol-

lows the momentary amplitude of the RF signal,

which is called envelope tracking (ET).

Dynamic Envelope Tracking

To realise a working ET system, one has to con-

trol the supply voltage based on the actual RF-

waveform in real-time. Therefore, an ET-system

has been developed and published in [Maa+16b]

for the ultra high frequency range (470 - 803MHz).

The block diagram is shown in Fig.3.55(a) with a

R&S SMU200a signal generation feeding the RF-

signal as well as the envelope. The envelope is

connected to the supply modulator via a low volt-

age differential signal connection (LVDS), ensuring

signal integrity. The supply modulator (Emerson

P5) used can take advantage of its extremely high

dc/dc conversion efficiency by up to 95% with

up to 80MHz modulation bandwidth, which is

multiple times the signal bandwidth required in

[Wan14]. Overall, the supply modulator is able to

switch 15V (VMOD) with multi-levels in 12 bit reso-

lution. An additional supply voltage (VFIX) is used

to increase the supply voltage to 30V (VFIX+VMOD).

Chapter 3. Power Amplifier

Supply

Modulator

Generator

RFout

PApre Amp

Delay

ARB

ARB envelope LVDS

DPD

VDRV VFIX VMOD

VFIX+VMOD

(a)

10 15 20 25 30

−5

−2.5

2.5

7.5

time in (us)

Amplitude in (V)

10 15 20 25 30

envelope in (V)

modulated RF

envelope

(b)

FIGURE 3.55: (a) Block diagram of the proposed ET sys-

tem (b) Measured modulated RF and corresponding en-

velope for a 470MHz DVB-T signal with 8.6MHz band-

width measured at the drain.

A programmable RF-delay within the signal gen-

erator ensures a synchronisation of the RF and the

modulated supply at the drain of the PA. A mea-

surement of this alignment was carried out with

an Oscilloscope and is shown in Fig.3.55(b). Al-

though the envelope is not a constant adoption

of the amplitude but rather a discretised function,

due to the high number of steps, one would not

call this static or a Class-G amplifier.

These analyses were made for laterally diffused

metal oxide semiconductor (LDMOS) amplifiers

working between 470 to 803MHz for application in

terrestrial broadcasting. The use of ET for this am-

plifier results in an overall efficiency improvement

of 14% for modulated signals over the entire fre-

quency range. The signals used are 8MHz DVB-T

signals (COFDM64 QAM) with a PAPR= 9 dB. Al-

though the signals differ from its pendants in the

satellite communication market the system used

can be easily adopted to an application within the

Ku-band by replacing the pre-amplifier and the PA

with a complete Ku-band BUC. Nevertheless, this

technique represents an adoption with access to

the baseband signal and therefore the baseband

modulator, which cannot be granted within most

SatCom applications.

Static Envelope Tracking

Static measurements were carried out to analyse

the possible influence of a dynamic ET on the PAE

of a Ku-band PA. This means that the supply volt-

age of the PA is constantly changing with discrete

voltage levels during a power-sweep to achieve the

maximum PAE for different output power states of

the PA. This static change in supply voltage can be

defined as a Class-G amplifier widely used for non

time-sensitive applications.

The lower Ku-band PA, described in Section3.4,

was tested in its pulsed RF probe measurement

setup. It should be mentioned that a reduction in

the supply voltage results in a huge reduction of

the amplifiers gain, as shown in Fig. 3.43(c) dur-

ing small-signal measurements. An ET is inten-

tionally used to increase the load in the back-off,

which works for ideal transistors as well as for

low frequency applications. As the gain shows a

significant dependency on small variations in the

supply voltage, the load-modulation is reduced. It

is therefore not the drain efficiency which has to

be improved by this static ET but rather the PAE,

taking the lowered gain into account.

By using a simple algorithm which compares the

achieved PAE for all supply voltages (VDS1,2 ={20-

45}V) during a power sweep, an improvement

can be obtained from Fig.3.56(a). This way, the

power sweep is shown over the peak output power

(Pout,pk) of a pulsed signal. While considering an

output power back-off (OBO) of 4 dB, 11% PAE is

reached for a supply voltage of VDS1,2 = 45 V. By re-

ducing the supply voltage to 35V an improvement

to 16% PAE can be obtained while the saturated

output power is reduced. The static variation of

supply voltage down to VDS1,2 = 20V improves

Chapter 3. Power Amplifier

40 42 44 46 48 50

Pout,pk (dBm)

PAE(%)

Class G

45V

40V

35V

4dB OBO

(a)

40 42 44 46 48 50

Pout,pk (dBm)

Gain (dB)

Class G

45V

40V

35V

4dB OBO

(b)

FIGURE 3.56: Measured (a) PAE (b) gain of the Class-G

PA at 13 GHz (10% duty cycle, IDq1,2 = 300 mA).

the OBO PAE up to 19%. With an increased out-

put power level the Class-G statical increases the

supply voltage to achieve the same high saturated

output power as the constant supply voltage of

VDS1,2 = 45V. This algorithm leads to a non-linear

gain over the output power level which is shown

in Fig.3.56. One should notice that the minor PAE

improvement of 8% does not justify this impracti-

cal large-signal gain. By changing the algorithm

to maintain a constant gain over the output power,

only minor efficiency improvements of up to 4%

were obtainable.

The impact of reducing the quiescent current to-

wards deep Class-B biasing has a much higher

influence on improving the PAE than the reduced

voltage, as can be seen in Fig. 3.57(a). Yet, the

lowered large signal gain of this biasing with IDq1,2

=50mA shows a much more linear behaviour than

the Class-G amplifier (Fig.3.57(b)). The PAE of the

VDS1,2 = 40V measurement is improved in the sat-

uration from 25% to 30%. In the 4dB OBO the

improvement is 6% while maintaining an almost

40 42 44 46 48 50

Pout,pk (dBm)

PAE(%)

Class G

45V

40V

35V

4dB OBO

(a)

40 42 44 46 48 50

Pout,pk (dBm)

Gain (dB)

Class G

45V

40V

35V

4dB OBO

(b)

FIGURE 3.57: Measured (a) PAE (b) gain of the Class-G

PA at 13GHz (10% duty cycle, IDq1,2 =50 mA).

flat gain of 17dB during the power sweep. In

theory, the optimum impedance is increased by

lowering the supply voltage. In fact, for all FET

a lowering of the supply voltage furthermore re-

acts in an increase of the drain-source capacitance

CDS, which furthermore increases the complex op-

timum impedance. By applying this technique to a

GaN-HEMT the drain-source capacitance CDS only

shows a small dependency on the supply voltage

(CDS =f(VDS)Fig.3.11(b)), whereas the feed-

back capacitance CDG shows a huge dependency

(CDG =f(VDS)). Additionally, an increase in the

input capacitance CGS can be obtained for a high

frequency operation (Fig.3.11(b)). Note that this

is not directly related to the standalone extrinsic

capacitance: it is a dependency of the total die

parasitics obtained for an increasing high feedback

capacitance.

The dominance of the feedback capacitance clearly

Chapter 3. Power Amplifier

reduces the effect of ET for GaN-HEMT’s operat-

ing at frequencies above the frequency of uncondi-

tional stability. Furthermore, the gain of the transis-

tor suffers a lot from reducing the supply voltage

which results in a lowered effect of ET applied to

GaN-HEMT amplifiers at high operation frequen-

cies.

3.6.2 Doherty Amplifier

An active load-modulation can be achieved by

changing the load of the main amplifier with an

additional peaking amplifier in the back-off. Dur-

ing saturation, a combined working of both ampli-

fiers is maintained. For the usage of this Doherty

technique a few restrictions need to be considered:

1. The combining of two amplifiers, even with

the use of ideal power-splitters and combin-

ers, reduces the power gain of the amplifier.

2. With the use of non-ideal working transistors

the load-modulation has to consider the non-

linear parasitics. One solution is to increase

the peaking-amplifier in size compared to the

main-amplifier.

3. The working bandwidth of a Doherty ampli-

fier is practically restricted. There is ongoing

work to enhance this FBW to ≥50% with the

use of extremely low-ohmic transformation

circuits in UHF [Qur+14]. Towards higher

frequencies non equal devices help to in-

crease the FBW to ≥42% with additional

non 50Ωtransformation circuits [Bat+11].

4. The improved OBO with an increased back-

off efficiency depends on the design. For the

realisation of high OBO like 10dB the usage

of multiple peaking amplifiers is useful to

achieve multiple peaks in the OBO efficiency

[Ngh+14].

To use a Doherty amplifier in the Ku-band one

has to consider the extremely non-linear parasitics

paired with a low gain of the devices. The first

stated argument of a decreased gain can be low-

ered by using the two-stage amplifier MIC of Kuup.

The already decreased gain of this MIC is partially

RFin split

50 Ω

95°

30 Ω

75°

24 Ω

117°

-5V

-2.7V

RFout

OMN

IMN ISMN

Kuup Main

OMN

IMN ISMN

Kuup Peak 1

OMN

IMN ISMN

Kuup Peak 2

Q1 Q2

(a)

36 38 40 42 44 46 48 50

Pout (dBm)

Gain (dB), PAE, η (%)

PAE

Gain

6dB OBO

(b)

36 38 40 42 44 46 48 50

Pout (dBm)

Current(A)

Main

Peak

Sum

6dB OBO

(c)

FIGURE 3.58: (a) Schematic view of the 2-Way unequal

Doherty using three Kuup MIC (b) simulation of the RF

compression (c) simulation of the current distribution

between the main and peaking amplifier (14GHz; CW,

IMain =500mA, VGS,Peak =-5V).

related to its huge non-linear Miller capacitance.

Multiple peaking amplifiers are therefore neces-

sary to achieve a load-modulation of the main

amplifier. However, bandwidth is not a restriction

within the SatCom uplink because the FBW is only

in the range of 6%. In addition, the OBO only

needs to be improved within 4-6dB considering

the future DVB-S2x modulation schemes.

3.6.2.1 Simulation Approach

Within a simulation the Kuup amplifier was anal-

ysed in an unequal 2-Way Doherty setup as shown

in Fig.3.58(a). The load of the Kuup main ampli-

fier can be modulated by using two parallel Kuup

peaking amplifiers. This unequal device technique

is able to compensate for the strongly non-linear

transconductance (Fig.3.10(a)) as well as the non-

linear Miller capacitance. The calculations of the

load transforming networks were carried out as

described in [Bat+11]. Fig.3.58(b) visualizes the

Chapter 3. Power Amplifier

simulation results of the proper working Doherty

amplifier. The PAE and ηcan be held ≥30% for

the 6dB OBO simulation at 14GHz. Furthermore,

Fig.3.58(c) depicts the equal current split of the

main and peaking amplifier with only a slight

amount of leakage current.

The obtained simulated results work for the whole

Fup frequency range. Nevertheless, they are ob-

tained by using MS-line models. For a realisation,

the distance between two Kuup MIC is restricted

by its mechanical size (18x12.5mm). Within the

first approach, it was intended to design low-loss

SIW transformation structures to achieve a high

mechanical distance with lower electrical losses

compared to MS-lines.

So splitting and combining structures based on Ri-

blet Short-Slot SIW structures were designed and

published. The work [Kon+16] describes such an

wideband SIW coupler (Fig.3.59(a)). While a lot of

effort was spend on improving the MS to SIW tran-

sitions used in this coupler (IL ≤0.7dB), the losses

of SIW related structures are by far too high (≥4dB

Fig.3.59(b)) for use with a combining or splitting

network. A future design methodology can rely

on thicker SIW structures or air-filled SIW to lower

the losses.

According to the simulation results, the improved

back-off efficiency of a few percent, does not jus-

tify the usage of six bare-dies while the total gain

remains at 10dB for saturation.

To face this problem a scaling of the main and peak-

ing device needs to be further investigated and the

transforming as well as splitting structures needs

to be realised directly on a MMIC, as already done

in [Qua+17].

12.5mm

(a)

10 11 12 13 14 15 16 17 18

−8

−6

−4

−2

Frequency in (GHz)

S21, S31 in (dB)

S21 meas

S21 sim

S31 meas

S31 sim

(b)

FIGURE 3.59: (a) Layoutview of the developed SIW

coupler (b) de-embedded comparison between measure-

ment and simulation of the coupling [Kon+16].

3.6.3 Summary

Within this section efficiency enhancement meth-

ods are analysed regarding their usability towards

Ku-band SatCom PAs. The saturation efficiency of

the developed PAs cannot be improved, due to the

low dependency of the transistor itself regarding a

harmonic match.

To enhance the back-off efficiency, static envelope

tracking measurements were carried out for the de-

veloped Kulow MIC and show a PAE improvement

of up to 10% for the 4dB OBO. The resulting vary-

ing gain reduces the usability of this technique.

The Kuup MIC was analysed towards an improve-

ment of the back-off efficiency by using a Doherty

technique. The simulations proved, that during

the 6dB OBO the PAE can maintain ≥30%. Nev-

ertheless, the large-signal gain decreased to only

10dB using six bare-dies, therefore the design has

not being further pursued.

Chapter 3. Power Amplifier

3.7 Discussion

The results of the developed amplifiers are shown

in comparison to previously reported packaged

PAs in Tab. 3.8. The first two entries represent

MMICs that have a comparable gain to the first

described MIC (Kuup) while suffering from a

lower output power and PAE. The published MIC

[Kaz+11] shows excellent PAE but under pulsed

power conditions. Bandwidth and gain are con-

siderably lower than in this work. However, the

reported MICs [Not+12],[Ima+14] determine the

max. output power reported suffering from a low

power gain. A pre-matched MMIC resulting in a

MIC reported in [Yua+16] demonstrates high band-

width with high efficiency. These obtained results

are implausible considering their design and mea-

surement techniques and the FBW in particular ex-

ceeds the theoretical limitations. The first reported

work [Maa+16a] shows a high power density over

6% FBW by using the smaller 25W device.

Within the MIC Kuup [Maa+17a] the low power

gain is extended to 15dB by keeping the PAE at

≥21%. Furthermore, an higher output power was

achieved due to the increased gate-periphery.

The lower part in this table (Tab.3.8) denotes the

achievements within the lower Ku-band. The first

entry represents a MMIC (Die) of Wolfspeed [Crea]

using the same transistor technology as this work,

but with a significant higher total gate width (Wt).

With this higher gate periphery, it achieves 20W

less output power than the developed MIC Kulow

with significant less PAE and a lower FBW. The sec-

ond entry [Nag+16] can take advantage of its lower

gate length (150nm) and moreover the increased

PAE of 34%. Nevertheless, this MMIC has an al-

most doubled amount of Wtcompared to Kulow

with an extremely low gain of only 6dB.

The last entry represents the developed MIC Kuext

which almost doubles the reported FBW to 14%, so

the PAE is lower but still at 20%.

The excellent results obtained indicate that a hy-

brid two stage design approach has significant ad-

vantages towards system design while achieving a

state-of-the-art efficiency.

TABLE 3.8: Comparison of state of the art PA in the Ku-band

design fcFBW Pout Gain PAE size lgWt3

(GHz) (%) (W) (dB) (%) (mm2)(µm)(mm)

[Kan+14] MMIC 14.1 5 20(CW) 10 16 226 0.25 9.6

[Creb] MMIC 14.1 5 25(CW) 20 18 232 0.25 16

[Kaz+11] MIC 15.0 3.3 56(pulse) 8 44 90 0.25 20

[Not+12] MIC 14.0 - 100 (pulse) - - - 0.25 38.4

[Ima+14] MIC 14.1 5 80(CW) 4.5 22 217 0.25 57.6

[Yua+16] MIC 15 22.5 30(pulse) 20 38 24 0.25 7.2

[Maa+16a] MIC 14.0 6 12(CW) 6 23 90 0.25 4.8

Kuup MIC 14.0 6 30 (QPSK)115 21 234 0.25 14.4

[Maa+17a] 14.0 6 70(QPSK)215 21 234 0.25 14.4

14.0 6 50(CW) 15 23 234 0.25 14.4

[Crea] MMIC (Die) 12.97 4 60 (pulse) 17.5 27 32.3 0.25 18

[Nag+16] MIC 11.45 4 100(CW) 6 35 217 0.15 28.8

Kulow MIC 12.9 7 80(pulse) 17 34 215 0.25 14.4

Kuext MIC 13.25 14 ≥55 (pulse) 15 20 215 0.25 14.4

1average power for QPSK. 2peak power for QPSK. 3Only PA stage.

4 Block Up-Converter

A block up-converter (BUC) is a part of the trans-

mitting chain within a satellite uplink base-station.

The signal processing of this base-station relies on

a double up-conversion technique. First the mo-

dem generates a baseband signal and converts it to

the intermediate frequency (IF 950-750MHz). Af-

terwards, the BUC converts this IF to the radio fre-

quency (RF).

Within this chapter the design and measurements

of a BUC with packaged integrated circuits that

are part of a hybrid design is described. The up-

conversion from the IF (950-1750MHz) towards

the radio frequency (13.75-14.5GHz) was con-

ducted by mixing the IF with a phased locked local

oscillator (PLO) of 12.8GHz, which is described in

detail in Sec.4.1 (Fig.4.1).

Unwanted mixing products had to be filtered by

the TX-filter introduced in Sec.4.2. A pre-amplifier

is necessary for boosting the signal to a higher

power level to feed the final PA (Sec.4.3). In ad-

dition, the developed BUC was equipped with a

pre-distortion technique that compares the output

of the PA with the IF input (Sec.4.3).

The MS output of the BUC was converted into

a WR75 waveguide which is implemented in the

housing (Sec.4.5).

The complete conversion chain was analysed in a

system simulation as well as evaluating measure-

ments which where carried out and described in

Sec.4.6.

A discussion section states the developed two

BUCs in comparison to commercially available

BUCs in Sec.4.8.

The results of this realised BUC are partially pub-

lished in [Maa+17c] and [Rau+17b].

Circuit Board

Within modern electronic mass-production all sub-

elements of the circuit should be housed separately

to ease the manufacturing. Most of these IC pack-

ages use a 500µm pitch between their pins. This

value becomes important when the high frequen-

cies which should be routed on the BUC circuit

board are taken into consideration. As a design

goal the lead-width of a package pad should rep-

resent a 50Ωcharacteristic line impedance for an

MS or coplanar line. Consequently, the height of

the substrate with its εrcan be calculated based

on the lead-width. Within this design a RO4003c

substrate with an εr=3.5 and a thickness of 221µm

was chosen, resulting in a line-width of 0.46mm

for ZL=50Ω(Φ90 = 4.5mm; εr,eff =2.7). To lower

the losses within the substrate, a special LoPro

foil was chosen which lowers the roughness of

FIGURE 4.1: Schematic of the BUC including the predicted power levels and the power consumption.

Chapter 4. Block Up-Converter

RO4003c

LoPro

RO4003c

LoPro

RO4450 Prepreg

221 µm

101 µm

35 µm

cond1

cond2

pc1

pc2

pcvia1

pcvia2

pcvia3

pcvia4

backdrill

blind via ﬁlled via

solder

mask

Signal

Signal GND

GND

FIGURE 4.2: Layerstack of the HF circuit board.

the metallisation (as discussed in Section2.1). Due

to the high number of different potentials, a four

layer stack provides two layers with 221µm of

thickness and one 101µm prepreg (RO4450) in

between to ease routing (Fig.4.2). Furthermore,

thermal vias (filled vias) are realised underneath

the ICs as well as blind vias and via-walls for the

high frequency isolation. In addition, vias can get

back-drilled and plugged to provide spacing to

a housing underneath and therefore, dc-isolation.

Unlike a layer-stack with RO4350b, on top of a con-

ventional FR4 core, this layer-stack is symmetric

and does not bend during the lamination process.

4.1 Frequency Generation

Local Oscillator

SatCom relies on several timing protocols. For

example, time division multiplexing (TDMA) is

used within the modem to synchronize TX and

RX data for different users. This means the mo-

dem provides a 10MHz output signal (REF) to the

BUC. The LO of the BUC is realised as a phased

locked oscillator (PLO) referenced to the (REF) in-

put. This REF is provided by an external modem

but its phase noise depends on the crystal technol-

ogy used within the modem. The REF signal is

fed into the BUC in combination with the IF sig-

nal. At the input chain of the BUC both signals are

extracted from each other via a triplexer filter that

was realised via SMD components.

The output frequency of the LO should be 12.8

GHz, which is why the conversion ratio from

10MHz is x1280. This leads to a high amount

(a)

102103104105106107108

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

Frequenz (Hz)

SSB Phase Noise (dBc/Hz)

PLO only

PLO 80kHz

PLO 18kHz

Maske (krit.)

Maske (typ.)

10 MHz

100 MHz

(b)

FIGURE 4.3: (a) Schematic of the multiplied PLO with its

(b) measured SSB phase noise.

of theoretically converted phase noise (PNconv):

PNconv = 20 ·log(1280) = 62.2dB. (4.1)

Multiplied PLO

Within the first approach, the REF is directly mul-

tiplied by a factor of x10 via a simple multiplier.

An integrated clock synthesizer should provide

a low phase noise and consists of a sub-micron

CMOS process (Fig.4.3(a)). As a second step, this

100MHz signal is converted with a phase locked

oscillator (PLO) by a factor of x128 resulting in the

12.8GHz LO. The given PNmulti = -132 dBc/Hz (@

10kHz) of the multiplier at 100MHz is going to

result in a theoretically converted phase noise of

PNconv = -90 dBc/Hz (@ 10 kHz) for the 12.8 GHz

signal. This is going to fulfil the requirements of

the critical phase noise mask within the Eutelsat

standard [Eut].

The circuit based on this schematic was designed

while realising different external loop filters

(18kHz, 80 kHz) of the second PLO. Thus, the

Chapter 4. Block Up-Converter

NXP TFF103N

PCB

2...80

MHz

REF

x10

10MHz 100

MHz

PFD CP

Loop

VCO

x128

12.8 GHz

80 kHz

PLO

PLL

HMC1031

PFD CP

VCXO

Loop

80 Hz

100

MHz

(a)

100 1k 10k 100k 1M 10M

−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

Frequency (Hz)

SSB Phase Noise (dBc/Hz)

PLO

PLL

mask (krit.)

mask (typ.)

10 MHz

(b)

FIGURE 4.4: (a) Schematic of the two-stage PLO with its

(b) measured SSB phase noise.

circuit was measured and is shown with its sin-

gle sideband (SSB) phase noise in Fig.4.3(b). It

can be observed that the phase noise of the REF

is PNREF = -130 dBc/Hz (@ 10 kHz). The multi-

plied phase noise (in green) results in PNmulti =

-118dBc/Hz (@ 10kHz) which is related to the the-

oretical assumptions. Furthermore, some spikes

occur that rely on a non proper biasing of the cir-

cuit. The internal loop-bandwidth of the multiplier

can be observed at 1MHz due to an overshoot.

This overshoot is further converted during the sec-

ond stage PLO circuit, to an increased phase noise

in the range between 10kHz and 1MHz – clearly

breaking the mask. The measurements indicate

that the phase frequency detector (PFD) of the

PLO suffers from a high residual phase noise at

12.8GHz. Increasing its loop bandwidth results in

a decrease of the low frequency SSB. An increase

of the loop bandwidth towards higher frequencies

is not possible due to the overshoot of the first

multiplier at 1MHz.

Two-stage PLO

Within a second topology (Fig.4.4(a)) the first

multiplier is replaced with a conventional PLL.

It consists of a PFD including a fixed division

ratio of x10 and an external voltage controlled

crystal oscillator (VCXO). It is possible to circum-

vent a high phase noise coming from the REF

input. Furthermore, the loop bandwidth of this

PLL can be set to extremely low values (80 Hz)

based on low charge currents of the PFD. Now

the loop bandwidth of the second PLO can be

set to high values (80kHz) to lower its effect of

the PFD residual phase noise. The resulting to-

tal phase noise is shown in Fig.4.4(b) and fulfils

the typical and critical Eutelsat mask [Eut]. It

should be mentioned that these measurements

were taken with an even worth REF that only

achieves PNREF = -120 dBc/Hz (@ 10 kHz). Nev-

ertheless, the first PLL is able to lower this input to

PNPLL = -145 dBc/Hz (@ 10 kHz) for the 100 MHz

signal by using its own VCXO. The resulting phase

noise at 12.8GHz based on the PLO now clearly

fulfils the mask while the internal loop bandwidth

of 18kHz shows a little overshoot.

PLO Amplifier

The differential output power level of the PLO is

in the range of -6dBm at Vcc =3.3V. To achieve

an appropriate driving level for a mixer, the LO

is boosted via a narrowband p-HEMT amplifier

(BFU730) that is already packaged and gets matched

on the RO4003c substrate. The amplifier has a

10dB gain with a P1dB=16dBm. In addition to

the narrowband character of the driving amplifier,

this LO is filtered with a coupled short stub fil-

ter to further lower possible side-band products

within the LO signal as can be seen in Fig. 4.5(a). It

compromises between losses and side-band atten-

uation. Therefore, only one section was used with

short ended stubs to increase the unloaded Qof

the pole.

Chapter 4. Block Up-Converter

Up-Conversion

The up-conversion is carried out via a double bal-

anced IC mixer (TGC2510) based on a GaAs p-

HEMT process. It includes a buffer amplifier as

well as an image rejection based on a fully differ-

ential IF input. The output TOI is 33dBm with

a conversion gain of 17dB. The p-HEMT process

allows a biasing of up to VD=5V, even though

all parts of the circuit need separate biasing (e.g.

LO buffer, RF output, control voltage as well as

a voltage reference). In addition, an LO-nulling

technique was applied via the biasing of the differ-

ential IQ IF inputs. As described in [Bal+02], high

precision mV supplies were designed based on op-

erational amplifiers that were capable of providing

±0.01V individually for the I and Q input of the

mixer. Thus, the LO reduction at the RF output

port was minimized to ≥40dBc within FKu for

various output power levels.

4.2 Hybrid Filter

The filter in the uplink path must be able to elim-

inate the crosstalk between the TX-band (13.75-

14.5GHz) and the close RX-band (10.95 -12.75

GHz). Despite effort being spent on reducing the

LO, in between the TX and the RX bands the fLO

=12.8GHz needs to be suppressed as well (Fig.4.6).

A proper working filter design results in a high

spectral purity of the whole BUC. Filter design in

a BUC for a Ku-band uplink path are traditionally

made by coupled wave-guide cavities. However,

they are rather big and difficult to implement in the

PCB design. Coupled line filters have been widely

used to achieve narrow FBW because of their rel-

atively weak coupling. A good repetition of these

filters is achievable with an easy synthesis proce-

dure [Poz05]. A low loss behaviour is possible by

choosing low tanδas well as a high electrical con-

ductivity (σ) in combination with a low roughness

(Ra) for the substrate. Nevertheless, hybrid filter

design at these frequencies compromises the better

rejection, leading to a high number of resonators

and a low insertion loss.

(a)

(b)

FIGURE 4.5: (a) Layout of the up-conversion with its (b)

measured conversion gain.

Furthermore, the group delay needs to stay con-

stant within the pass-band and should not exceed

a value of ≈1nspp. Often edge-coupled filters pro-

duce the longest delay in a complete uplink path

and the value increases even more with the filter or-

der. Those tough requirements can be extended by

the need for a harmonic suppression at two times

the centre frequency (2·f0).

Al2O3TX Filter

The results of the substrate analysis in section 2.1

show that there are several limitations on the un-

loaded Qof a λ0

4resonator. The highest Qwas

obtained by a rather thin Al2O3alumina substrate

with h=127µm and an εr=9.9. Therefore, the TX

filter design starts on this substrate and was par-

tially published in [Maa+16c].

Chapter 4. Block Up-Converter

0,95 GHz 1,7 GHz

10.95 GHz 12.75 GHz 13.75 GHz 14.5 GHz

fLO = 12.8 GHz

Rx-band Tx-band

Upconverter PA

f LO

Tx- lter

FIGURE 4.6: Transmission spectrum of the proposed

transceiver in the Ku-band and block diagram of the up-

conversion path.

A band-pass filter (BPF), with the 5% FBW spec-

ifications located at 14.125GHz, can be realised

by either combining a low-pass (LP) and a high-

pass (HP) or using resonant structures like quarter-

wave coupled lines. Resonant structures are prefer-

able in the case of size and PCB manufacturing is-

sues and are then connected either capacitively or

inductively. All filters are designed based on the

commonly known equations depicted by Matthaei

[Mat+85]. Thus, an appropriate schematic design

is realised in CST Design Studio TM including com-

mon parasitic behaviour of edges, coupled lines

and open end effects. The design is afterwards

optimized and transformed to a layout, which is

analysed via a full 3-D time domain EM-solver.

Within the following subsections four topologies

of filter were selected and later on designed. Dif-

ferent numbers of the coupled line sections were

used while their FBW remains constant.

Coupled Line Filter

A coupled line filter (CLF) (Fig.4.8(b)) is an easy

filter type of combined resonators. The length of

one coupled line (CL) is λ0

4and within this work

combined to three resonators to realise a moder-

ate 3rd order filter with low insertion loss. The

outer CLs are strongly coupled and the inner ones

weakly coupled. It is intended to have a high FBW

just around f0to get a flat as possible group delay.

Hairpin Filter

Within the hairpin filter (Fig.4.8(a)) the CL pairs

are connected with uncoupled lines to realise the

12.5 13 13.5 14 14.5 15 15.5 16 16.5

−30

−25

−20

−15

−10

−5

S−Parameters (dB)

Frequency (GHz)

meas S21

meas S11

sim S21

sim S11

Spec

26 28 30 32

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5

f2 (GHz)

FIGURE 4.7: Comparison between measurement and

simulation of the proposed hairpin filter.

folding. As a consequence, this results in a self-

coupling of the resonator that decreases the filter

bandwidth and increases the losses. The open-

circuit resonators reduce the free-space radiation

by the phase cancellation at its end. At high fre-

quencies the bend discontinuities become domi-

nant. What is more, it is the effect of folding the

resonator which does not decrease the size (weak-

coupling) [Mal04]. The spurious mode occurs at

twice the pass-band frequency and can only be

lowered by equalizing the even- and odd-mode

phase constant (βe, βo) of the coupled resonators

or changing the length of the input/output lines

to λ0

8[Mal04]. To achieve a harmonic suppression

the coupled lines are over-coupled to an electri-

cal length of 130◦. The pass-band response is not

effected by this, since the derivative of the cou-

pling response is zero at f0. This over-coupling

extends the phase length of the odd-mode like in

[Rid88], [Kuo+03] and results in a suppression of

≥20dB for the second harmonics. It is also well

known that increasing the Image impedance of

coupled lines equalizes βe, βoas well. The high εr

of the used substrate in combination with the low

thickness will result in thinner lines that exceed

the manufacturing tolerances and are therefore not

used. Both input and output lines are tapped to

improve the matching.

Chapter 4. Block Up-Converter

(a)

(b)

5 mm

1.2 mm

0.13 mm

0.08 mm 0.13 mm

0.06 mm

1.2 mm

7 .3 m m

0 .0 7 m m

2 .4 m m

1 mm

2 mm

0.28 mm

0.2 mm

0.3 mm

6.4 mm

0.54 mm

0.05 mm 0.07 mm

2.14 mm

FIGURE 4.8: Pictures of the realised filter on alumina

substrate (a) hairpin (b) CLF (c) ringresonator (d) inter-

digital.

Ringresonator Filter

The ringresonator, or open-loop resonator, can be

seen as four resonators (1-4) that are directly cou-

pled like in Fig.4.9(a) (Realisation in (Fig.4.8(c))).

It’s behaviour is like the hairpin filter whereas the

self coupling is increased due to the closer ring.

The additional capacitive coupling of the open-

ended lines result in a flatter response. Due to

the high self coupling, of the ring, the CL cannot

be over-coupled without changing the pass-band

frequency. A harmonic suppression can there-

fore only be realised by equalizing the even- and

odd-mode impedances (Ze, Zo). However, this ap-

proach cannot be realised due to the manufactur-

ing constraints. A combination of open-loop res-

onators that are inductively, capacitively or mixed

coupled can also lead to a harmonic suppression

[Poz05].

Interdigital Filter

Interdigital filters (Fig.4.8(d)) are known to have

multiple-order poles of attenuation at the funda-

mental and second harmonic. The lines operate as

impedance transformer and are therefore coupled

transformers and not coupled resonators. This

filter does not have any even harmonic spurious

transmissions. Furthermore, the bandwidth can

be as narrow as 1%. The difficulties regarding an

interdigital filter rely on the manufacturing and

the ground inductance of interconnection, which

is necessary at the end of the stub. The ground

inductance of a via is therefore studied with a

full 3-DEM-simulation. Afterwards, a model is

inserted in the schematic at the beginning of the

optimization process.

Experimental Results

All filters are measured via 500µm pitch probes

with a HP8510c. A GSOLT-calibration defines the

reference plane to the probe-pads. With an addi-

tional second tier TRL calibration on the Al2O3

substrate the reference plane is shifted to the 50Ω

input of the filter. Fig. 4.7 shows, as an example,

the comparison between the measured and simu-

lated hairpin filter. It can be seen that simulation

and measurement fit each other well. The FBW of

the measurement is slightly higher than simulated.

The centre frequency is equal. The IL (S21 indB)

and RL (S11 indB) are both as simulated. The

harmonic suppression at 2·f0is a bit less than

simulated but still ≥20dB.

As shown in Fig.4.9(b) all designed filters work in

the frequency range of interest. The critical param-

eters are also compared in Tab.4.1. The CLF has a

low IL and a low suppression of the fRX as well as

the fLO. The three other filters all derive benefits

from their higher Qwhich helps to fulfil the speci-

fications (dotted line) from Fig.4.6. All filters have

an IL ≤2.2dB. Only the RL of the hairpin as well

as the ringresonator filter is good with ≥17dB. The

interdigital filter has the weakest matching of only

≈10dB due to its shortened stubs. A harmonic

suppression can only be seen, as designed, for the

hairpin filter of ≥20dB and the interdigital filter of

≥42dB. For the others, additional low-pass filters

could be added.

The CLF has the lowest as well as the flattest group

delay with 0.2±0.03ns (refer to Fig.4.9(d)). The in-

terdigital filter has a surprisingly flat group delay

of 0.48±0.03ns in the frequency range of interest,

Chapter 4. Block Up-Converter

(a)

11 12 13 14 15 16 17

−35

−30

−25

−20

−15

−10

−5

S21 (dB)

Frequency (GHz)

CLF

hairpin

ringresonator

interdigital

spec

25 27 29 31

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5

2⋅f0 (GHz)

(b)

11 12 13 14 15 16 17

−35

−30

−25

−20

−15

−10

−5

S11 (dB)

Frequency (GHz)

CLF

hairpin

ringresonator

interdigital

25 27 29 31

−20

−18

−16

−14

−12

−10

−8

−6

−4

−2

2⋅f0 (GHz)

(c)

12.5 13 13.5 14 14.5 15 15.5

0.2

0.4

0.6

0.8

Frequency (GHz)

group delay (ns)

CLF

hairpin

ringresonator

interdigital

25 27 29 31

−0.5

0.5

1.5

2.5

2⋅f0 (GHz)

(d)

FIGURE 4.9: (a) 3D view of the ringresonator filter in

CST with the appropriate coupling structure of the four

resonators, source and load. (b) Measured transmission

and (c) reflection, as well as (d) group delay results for

the designed filters.

while the hairpin filter has 0.38±0.04ns around

14GHz. In spite of the highest group delay with

the biggest variance, the ringresonator filter has to

be declared with 0.64±0.06ns.

RO4003c TX Filter

The realised TX filter on AL2O3works well for the

defined requirements. However, interconnection

losses between the components of the transceiver

and the filter will be dominant in the case of choos-

ing a second substrate only for the filters.

Ringresonator Filter

Based on this preliminary analysis a combination

of a ringresonator and an interdigital filter is de-

signed and realised directly on the lower unloaded

QRO4003c LoPro substrate (Fig.2.4(a)) and is

shown in Fig.4.10(a). The shortened stub behaves

as a feeding resonator with a higher Qthan the

normal open-stub of a hairpin. Special care was

taken to determine exactly the ground inductance

of the via holes by a full 3D EM simulation. In ad-

dition, two MS rings build a 4 pole section. So the

increased self coupling of the rings interact with

the feeding resonator. The harmonic suppression

is realised by the construction of the poles.

SIW Filter

By far the best quality factors can be achieved by

using coupled wave-guide cavities. Substrate in-

tegrated wave-guides (SIW) can be used to ease

the integration of these cavities and to lower the

dimension. Therefore, a SIW-filter containing five

cavities is realised in [Rau+16b] and shown in

Fig.4.10(b). Especially the high Q of the SIW cav-

ities are a great example for lowering the LO fre-

quency within the TX output spectrum as shown

in Fig.4.10(c). This figure displays a comparison

of both realised filters which were designed to per-

form with an almost equal FBW. It needs to be

pointed out that the compared IL describes the ref-

erence plane related to the MS line not to the SIW

plain, which would be far less. Effort was spent

Chapter 4. Block Up-Converter

TABLE 4.1: Comparison of realised Ku-band filters

fLfUFBW Q IL RL fRX fLO 2·f0group Size

3dB 3dB 3dB 3 dB att. att. att. delay

(GHz) (GHz) (%) (dB) (dB) (dB) (dB) (dB) (ns) (mm2)

[Riu+05] 13.25 11.3 2.1 8.8 12 35* 29

[Li+08] 16.57 17.7 5.6 14.5 77.7

[Shi+10] 13.97 20 1.7 4.9 17 4.5 54

[Man+09] 12.5 18 4.6 5.4 40* 190

Al2O3

CLF 12.5 16.16 28.6 3.8 1.5 13 7 2.7 3 0.2 18

hairpin 13.1 15.2 14.8 6.7 1.5 20 25 11 20 0.38 16

ringresonator 13.7 15.1 9.7 10.2 2.2 17 40 27 3 0.64 17.5

interdigital 13.2 14.78 11.2 8.85 1.9 10 20 14 42 0.48 9

RO4003c

ringresonator 13.7 14.5 5.6 9 4.5 10 32 23 0.36 36

SIW [Rau+16b] 13.4 14.75 7.5 13.3 4.5 17 ≥40 30 1±0.03 776

*This filter has a different centre frequency so the distance to fRX is referenced and used

on optimizing the high impedance MS line tran-

sition to the low impedance SIW and up to 20dB

RL was achieved in [Kon+16]. Nevertheless, the

transition losses from MS to SIW are that high that

they significantly affect the total IL.

Furthermore, the IL of both filters are highly re-

lated to the tanδof 0.0027 of the substrate and the

conductive losses based on the roughness. In the

ringresonator only the top roughness of the sub-

strate is important, whereas in the SIW the rough-

ness of the metallized vias as well as the MS to

SIW transition is significant. In addition, the low

thickness hof the substrate increases the conduc-

tive losses of the SIW as well as the ringresonator.

Summary

Four different coupled line filter topologies are de-

signed and measured on a Al2O3substrate. All de-

signs show a good agreement between simulations

and measurements and are suitable for their appli-

cation as a TX-filter in the up-conversion path of

aKu-band BUC. Compared to the published work

(Tab. 4.1) the commonly used topology is a hairpin

filter. The results of this work are like [Riu+05],

[Li+08] and [Man+09] but with a lower IL and a

harmonic suppression. [Shi+10] uses split-ring res-

onators in combination with a low-pass to realise

a bandpass characteristic. Its low IL of 1.7 dB with

the higher FBW can therefore not be reached by the

ringresonator filter of this work. The interdigital

filter has a low FBW as well as low IL in combi-

nation with the highest harmonic suppression and

the smallest size. Its the preferred choice of filter in

between amplifier stages, where its low RL is not a

hindrance. A developed SIW filter shows excellent

filter parameters but due to its large size a realisa-

tion was impractical. A combination of the inter-

digital filter and the ringresonator was finally re-

alised on a RO4003c substrate fulfilling all require-

ments of LO, RX suppression as well as the band-

width, which is why it is used further on.

4.3 Amplifier

Dual Directional Coupler

A dual directional coupler was developed to deter-

mine the forward and reflected power level within

different stages of the BUC. Realised on a RO4003c,

it compromises between losses and bandwidths as

already described during the previous filter analy-

sis. The coupler should be located among different

positions of the BUC, being so small as not to oc-

cupy more space than a necessary TL would take.

As a result, only a weak coupling can be realised

to lower the influence of the coupling path to the

Chapter 4. Block Up-Converter

(a) (b)

Transmission (dB)

Frequency (GHz)

(c)

FIGURE 4.10: (a) Layoutview of the ring resonator, the

(b) SIW Filter as well as (c) the measurement results ob-

tained.

main line. A common dual directional coupler con-

sists of a main line with two coupled lines along it.

The length of the coupling lines determine the fre-

quency range while the distance to the main-line

influences the coupling.

For a centre frequency of 14GHz the length should

be λ0

4which is 4.5mm. It can be shown that equal-

izing the electrical length of the even and odd

mode for this coupler needs to be done to improve

the directivity of the coupler [Mar82]. In [Zha+15]

this technique is applied by using interdigital fin-

gers at the edges of the coupled line, which locally

introduce capacitance. Interdigital fingers are not

only used at the edges of the coupling lines but also

in between. The coupler is shown in Fig. 4.11(a)

with additional coaxial connectors to ease a sep-

arate measurement. One coupled path ends at a

coupler while the other one feeds a Wilkinson split-

ter. This splitting is necessary for the output side of

the BUC to simultaneously use the forward power

(FWD) for a down-conversion as well as a contin-

uous power measurement with a power detector.

4 mm

1.2 mm

0.65 mm

Input Output

0.83 mm

p g

(a)

12 12.5 13 13.5 14 14.5 15 15.5 16

−80

−70

−60

−50

−40

−30

−20

−10

REV, FWD, RL (dB)

Frequency (GHz)

−5

Frequency (GHz)

S Parameter

IL, directivity (dB)

REV

FWD

direct

(b)

FIGURE 4.11: (a) Layoutview of the realised dual direc-

tional coupler (b) measurement results.

The reverse power (REV) is later on connected to

another power detector.

From Fig.4.11 the measured S-Parameters can be

obtained, while the connectors are de-embedded.

An IL of 0.45dB is measured for the 4mm structure

with additional 1mm 50ΩMS lines (right Y-axis).

The RL for the input as well as output is equal and

≥20dB for Fup (left Y-axis). At the coupling port

an FWD=-40dB and a REV=-66dB coupling can

be determined. The REV can be seen as isolation

– leading to a calculated directivity of ≥20dB for

Fup (right Y-axis). One may conclude that the di-

rectivity limits the detectable VSWR to 1:1.22 but a

higher selectivity would lead to an even higher IL

by the cost of output power.

Pre-Amplifier

A multi-stage 20V GaN-HEMT pre-amplifier IC

(TGA2958SM) is used to increase the Pout from the

up-conversion to 32dBm to be able to saturate the

PA. The pre amp achieves a PAE of 25% that results

in a Pdiss =5W which needs to be cooled at the bot-

tom of a 4x4mm QFN package. The pre-amplifier

Chapter 4. Block Up-Converter

(a)

13.5 13.75 14 14.25 14.5

Frequency (GHz)

Gain (dB), ETA (%), Pout (dBm)

Gain

Eta

Pout

(b)

FIGURE 4.12: (a) Layoutview of the realised pre-

amplifier with hybrid dual directional couplers and (b)

measurement results with de-embedded connectors.

was measured with on-board dual directional cou-

plers as can be seen in Fig.4.12(a). CW measure-

ments of Fig.4.12(b) visualize the achieved output

power of Pout ≥31dBm for the target frequency

range Fup.

Power-Amplifier

To implement the designed MIC PA Kuup from

Sec.3.3 into the BUC, a cavity was left with the

mechanical dimensions of the PA. The PA is posi-

tioned in the cavity as a drop-in circuit. A side-

view of the stack can be seen in Fig.4.13. This

way, the interconnection between the top met-

allisation on the RO4003c (cond1) and the met-

allisation on the AL2O3is realised via 100µm

wide gold ribbons. The gap in between both sub-

strates leads to an inductive connection for the

ribbon as well as the GND interconnection. So,

this inductive ribbon needs to be compensated

via a capacitive post or open-stub at the RO4003c

side of the substrate. This compensation network

is measured separately by a drop-in circuit that

only consists of a 50ΩML and states 20 dB RL

within Fup. By de-embedding the losses of the

MS line the IL is determined to be 0.3dB which

depends on the positioning accuracy of the drop-

in circuit. In addition, GND ribbons between

both substrates were added. Besides this RFin,

RFout feeds the biasing is realised via silver rib-

bons that can be easily attached by soldering. The

CuMoCu flange is connected to the Al-housing

RO4003c

cond1

cond2

pc1

pc2 RO4003c

RO4003c

ribbon ribbon

Housing

BUC BUC

FIGURE 4.13: Integration of the designed MIC PA into

the hybrid stack.

via screws to provide the best thermal connectiv-

ity where simulation indicates an RT H ≤0.3K/W.

The MIC PA can be scaled in output power be-

tween Pout, peak = 25 W [Maa+16a] using the smaller

bare-die (CGHV1J025D) or Pout, peak =70W from

Sec.3.3 [Maa+17a] because both MICs are designed

for the same mechanical dimensions and the same

positions of the pads.

Linearisation

This section extends the results already published

in [Maa+15a] by a complete implementation of

a RF-linearisation within a BUC. Linearisation is

nowadays a standard technique to compensate

for the non-linearity of either an amplifier or a

complete conversion chain for base-station appli-

cations (terrestrial broadcast, 3G telecommunica-

tion). A common method for compensating the

compression behaviour of a PA is the usage of a

digital pre-distortion (DPD) that can be included in

the baseband digital modulation path and builds

a gain expansion to achieve a linear output power

behaviour [Fra+06]. For a DPD the processing

power increases with the signal bandwidth. Unfor-

tunately, the signal bandwidth of SatCom signals

is rather high with up to 36MHz1compared to,

for example WCDMA or LTE signals with only a

few MHz bandwidth. Apart from that, there is

a lack of interconnection between the output of a

BUC and the output of a modem as they are, based

on the double up-conversion technique, located in

different frequency ranges.

To overcome this problem, a so-called RF pre-dis-

tortion (RFPD), which filters the non-linearity as

well as compensates for the memory dependants

directly within the RF domain, can be a solution as

136MHz represents one transponder of a Ku-band satellite.

Chapter 4. Block Up-Converter

REF

pre Amp CPL

delay

RFINP

RFINN

RFFBP

RFFBN

RFPAL

L-Band Ku-Band

CPLCPL

RFOUTP

RFOUTN

correction

feedback

input

FIGURE 4.14: Schematic of the IF linearisation.

shown in [Kat+10], [Kat14]. RF linearisation tech-

niques are already applied for TWTAs but only

through the use of simple diode networks that ex-

pand the compression behaviour [Jie+15], [Vil+12].

Within this work, a RF pre-distortion is applied

in the IF range (950-2150MHz), instead of the RF

path, as it was shown in [Ban+01] for OFDM sig-

nals.

The IF pre-distortion is realised with a RF PA lin-

earisation (RFPAL-system) of Maxim IntegratedTM

(formerly ScinteraTM). Inside this IC an analogue

linearisation takes place by dynamically enabling-

or disabling filter coefficients [Rog13]. An input

signal is compared to a feedback signal (from the

PA output) in real-time and correction coefficients

are applied towards optimized distortion.

Fig.4.14 shows the schematic of the IF pre-distor-

tion in which the input and correction coupler

is placed in between the IF input and the IF up-

conversion. A delay is necessary to compensate

the processing time of the RFPAL IC that is fed

back into the circuit via the coupler. At the output

side of the PA the signal is coupled and converted

back into the IF via a mixer. This way, the LO of

the up-conversion as well as the down-conversion

needs to be in phase.

The advantages of implementing this technique

in the IF over the Ku-band are the lower losses

and the commercially available RF-pre-distortion

techniques from the telecommunication market.

Moreover, the distortion of the up-conversion as

well as the pre-amplifier, so the whole chain, is

compensated. Additional distortion caused by

the down-conversion mixer is negligible due to

the low power level the mixer is operating. The

system is able to reduce the out-of-band energy

by compensating non-linearities like AM/AM

and AM/PM distortion as well as memory ef-

fects [Rog11]. The detection whether a signal is

in-band or out-of-band relies on a live sampling of

the signal and analysing its 10dB slope. Further-

more, it automatically detects the IF as well as the

bandwidth of the signal. The modulation type is

not relevant for the RFPAL system. What is more,

also multi-carrier signals can be applied. However,

higher order modulation schemes will increase the

error vector and side-band products, which makes

an improvement more challenging.

Preliminary Tests

To get adequate measurement results, the linear-

ity of the system with the combined hybrid GaAs

PA from Sec.3.1 was proven with (w) and without

(w/o) the RFPAL-system based on measurements

of the error vector magnitude (EVM), the resulting

constellation diagram, and the spectral regrowth

of the output signal. The output signal was there-

fore measured in the Ku-band to eliminate mea-

surement failures that rely on a down-conversion.

A signal with a 8PSK modulation and symbol rates

from 10MSym/s to 30 MSym/s (13-36 MHz) with

a PAPR of 3.7dB was chosen.

The output power spectrum of the BUC is shown

in Fig.4.15. It can be seen that a massive improve-

ment of the shoulder distance can be realised by

the pre-distortion for a constant output power of

37.5dBm. This improvement was equal over all

measured frequencies within Kuup.

Chapter 4. Block Up-Converter

−20 −10 0 10 20

−40

−30

−20

−10

Baseband Frequency (MHz)

Normalized PSD (dBm/Hz)

w/o RFPAL

w RFPAL

FIGURE 4.15: Normalised output power spectrum of the

BUC at 14.35GHz centre frequency with Pout=37.5 dBm.

A 10MSym/s 8PSK signal with 3.7dB PAPR is used and

measured with RBW=300kHz; RMS; VBW=3MHz; 2 s

sweep; 100MHz span.

On the left shoulder the RFPAL-system improves

the ACPR within 9.8dBc, whereas the improve-

ment on the right shoulder is only 7.7 dBc. The

spectral regrowth is asymmetric over the channel

frequency band, which indicates a group delay

problem of the up-conversion as well as the feed-

back channel. Moreover, a base-band problem

can cause this asymmetric response. Nevertheless,

an improvement of the spectral regrowth can be

noted almost independently from the symbol rate

(Tab. 4.2). Due to the good results, the failure of

the feedback path, caused by the down-conversion

distortion, seems to be negligible. The output con-

stellation diagram shows a good EVM improve-

ment of at least 3 % over different symbol rates. A

screen shot of the constellation diagram is shown

in Fig.4.16.

TABLE 4.2: Measured average output power, EVM and

minimum ACPR level (BW + 0.5MHz), without (w/o)

and with (w) RFPAL at 14.35GHz for 8PSK modulation

Pout EVM right ACPR

(dBm) (%) (dBc)

w/o w w/o w

10MSym/s 36.7 6.1 3.1 -25.4 -37.6

10MSym/s 37.5 6.9 4.1 -23.3 -31.0

20MSym/s 37.5 12.0 9.1 -25.6 -33.1

30MSym/s 37.5 21.4 18.2 -26.9 -30.3

FIGURE 4.16: Measured output constellation diagram

for a 10MSym/s 8PSK signal with 3.7dB PAPR at

Pout=36.7 dBm with a running RFPAL.

Implementation

To implement this technique within the BUC a few

constraints needed to be faced. Firstly, all the differ-

ential IF inputs of the RFPAL IC are originally used

narrowband (e.g.1400-1800MHz), while internally

the IC is able to work between 225-3800MHz. To

be able to use the whole IF range (950-2150MHz)

without changing the layout, new coupling as well

as balancing circuits needed to be investigated.

Secondly, a high directivity of the couplers must

be granted as well as a flat IL over the whole sys-

tem. For this extended bandwidth wire wound

coupled air coils as SMD components are used

(TCD-9-1WX+). The increasing losses towards the

higher IF are compensated using a low slope high-

pass circuit, as can be seen in front of the coupler

in Fig.4.17(a). Baluns were realised with LTCC

multilayer circuits offering a good phase equal-

ity over the IF. The differential IF inputs are not

strictly 100Ωrather than a complex varying load

that needed to be matched to the opposite facing

term of the balun as well as the couplers. As an

example, the matching between the differential in-

and outputs of the IC to the balun is visualized for

the IC output side in Fig.4.17(a). An additional dc-

feed is necessary to bias the CMOS output drivers

and supplied via the cold-point of the balun. By ap-

plying this technique the RFPAL is easily matched

to the required bandwidth.

To equalize towards an optimal SNR at the inputs

of the RFPAL IC, additional variable gain ampli-

fiers (VGA) were used to either boost or decrease

Chapter 4. Block Up-Converter

IFout

RFOUTP

RFPAL CPL

RFOUTN

BLN

0.3pF

0.2pF

4.3nH

Ferrite

Bead

100pF

dc-feed

BD1631J50100AHF TCD-9-1WX+SC1894

IFin

(a)

IFin

IFout

IFfeedback

RFPAL

delay2

delay1

VGAin

VGAout

VGAfeedback

CPL

matching circuits

feedback

input

correction

(b)

FIGURE 4.17: (a) Schematic of the linearisation matching

circuits (b) Layoutview of the realised IF linearisation im-

plemented in the BUC.

the input power as well as the feedback power. In

addition, one VGA is used at the output side of the

RFPAL IC to match the level to the input of the up-

conversion. The layout-view of the IF linearisation

can be seen in Fig.4.17(b).

4.4 dc/dc Conversion

Within the BUC there are in total 29 different po-

tentials that need to be supplied to the different

circuits. A range of different voltages and currents

need to be biased while only the drain-supply of

the PA is fed, directly coming from the connector

dc-in via a switching FET (Fig.4.18(a)). Coming

from the connector, a first integrated step-down

converter (LTC3649) switches the voltage to 20 V,

which is the drain-supply for the pre-amplifier. An

additional converter (LT8601) aligns the 20 V to 5V,

3.3V as well as 1.8 V, which are necessary for driv-

ing the up-conversion, the LO generation as well

as the linearisation circuit. During the start-up se-

quence only the 3.3V are biased to detect whether

40V

10 MHz

LCK DET

NEG DET

Lineariser

20V

3,3V

1,8V

pre Amp

-5V

GND

DC-in

(a)

(b)

FIGURE 4.18: (a) Schematic view of the realised dc/dc

conversion with (b) a layoutview.

a 10MHz REF is connected or not. The power con-

sumption of this stand-by mode is therefore only

1.5W.

By applying the REF, the first PLL of the PLO

is able to lock and therefore the LCKDET signal

gets high. This LCKDET signal starts a sequence

by first switching the 1.8V, followed by the 5 V

(Fig.4.19(a)). Within a charge-pump the positive

5V supply is afterwards converted to a -5 V supply

that is used with operational amplifiers to realise

the negative gate supply for all normally on devices

(up-converter, pre-amplifier, PA). To prevent the

self-destruction of these devices their drain-supply

is switched off during the start-up sequence by

a p-MOS switch (Si3127) triggered by NEGDET

(Fig.4.19(b)).

Baseband Impedance

The previous analysis regarding linearity of the

GaN-HEMT process, in Sec. 3.2.4, showed that the

influence of a well-chosen baseband impedance

on the intermodulation distortion cannot be ne-

glected, while the influence at the drain-side dom-

inates the gate-side due to the effects of a stability

Chapter 4. Block Up-Converter

0 1 2 3

−5

20 V

5 V

3.3 V

1.8 V

Time (ms)

Voltage (V)

(a)

0 1 2 3

Supply

−2.8 V

20 V

Time (ms)

Voltage (V)

(b)

FIGURE 4.19: Measured starting sequence for the dc/dc

conversion with (a) the connector injection and (b) the

PA bias.

resistor. In general, the dc-feed of an amplifier

should provide an open circuit for the frequency

range of usage. Within this work, this is realised

by λ0

4lines located on the MIC substrate in combi-

nation with a radial stub. This enables a sufficient

RF/dc isolation within the bandwidth of operation.

The interconnection from this ended structure to

the surrounding substrate is realised via gold rib-

bons that introduce an additional inductance to the

path. Beginning on this surrounding structure, the

RF blocking is extended by additional capacitors

that typically increase with size within decades

(e.g. 1 pF, 10 pF, 100pF, 0.1µF ...). The failure of

this classical approach is located within the reso-

nances of this structure. The increasing distance

between the capacitor (and therefore the induc-

tance) introduce resonances in the overall blocking

structure. Furthermore, modern multilayer SMD

capacitors are pursuing for higher quality factors

that sharpen these resonances. They are titled low

equivalent series resistance (ESR) which defines

the inner resistance and therefore the amount of

dissipated power. By eliminating these resonances

within the baseband frequency range as well as its

harmonics, the IMD can be improved [Sri+08].

The new design approach of the biasing circuits is

defined as follows:

•λ0

4lines with radial stub provide RF/dc iso-

lation in band

•a small SMD capacitance with a low ESR

1051061071081091010

10−2

10−1

100

101

102

104

|X| (Ω)

Frequency (Hz) Frequency (GHz)

classical

new approach

10 13 15 20

10−2

10−1

100

101

102

104

FIGURE 4.20: Measured reactance of four parallel dc-

feeds.

compensates for an inductive ribbon as well

as feeding circuit next to the MIC

•one large SMD capacitance should provide

enough decoupling for the IF range while

its SRF is located away from operating fre-

quency ranges

•the BB impedance response is not influenced

by the previous capacitors and can take ad-

vantage of a non resonating large electrolyte

capacitor as close as possible to the drain

However, it turns out that designing biasing cir-

cuits for a specific baseband impedance becomes

difficult by the lack of measurement data for the

blocking components. Therefore, measurements

were carried out to enhance the S-Parameters pro-

vided by the manufacturer towards lower frequen-

cies. In addition, these measurements were ap-

proximated by a discrete model to ease the sim-

ulations. Fig.4.20 denotes the simulation of the

complete dc-feeding circuit for a symmetrical bias

of four drains in parallel. It can be seen that the

first resonance of these bias networks is located at

≈300kHz which is related to the resonance of a

470pF electrolyte capacitor.

Later, the frequency range up to 36MHz can be

declared as the fundamental baseband frequency

range. In here, no resonances should occur which

tend to ring within intermodulation products. The

denoted classical approach with the constantly in-

creasing capacitance values shows at least two

additional resonances located at 0.7 and 1.4 MHz.

The next resonance is located at 500 MHz which is

Chapter 4. Block Up-Converter

due to the high Q of a 100pF capacitor used in the

classical approach, while the new approach displays

the same resonance but can take advantage of a

low Q capacitor. Within the Ku-band the impe-

dance is dominated by a λ0

4MS line with a radial

stub that is equal for both approaches. The over-

all performance of the new approach is more flat

without any disturbance. While applying this tech-

nique to the linearity measurements, which are

described later on, an IMD3 improvement of up to

10dBc was achieved. In particular, asymmetrical

IMD products are highly related to resonances in

the baseband impedances.

4.5 Realisation

Waveguide

With an increased operation frequency the com-

mon output connectors for BUCs are waveguides.

For the Ku-band the WR75 rectangular waveguide

dominates the VSAT market and enables low-loss

interconnection from the BUC to the antenna feed.

Two possible approaches of feeding a waveguide

from a coaxial or MS line can be determined:

•A right angle (or orthogonal) transition inter-

connects the waveguide with a simple feed

within the E-field maximum. A so-called

back-short is positioned λ0

4away from the

feed reflecting electromagnetic energy back

to it. This results in a TE01 mode excitation

orthogonal to the MS or coaxial feed. The

transition represents an open circuit with the

possibility of a low insertion loss intercon-

nection.

•As an alternative, the in-line transition is re-

alised by feeding the coaxial or MS line by

a short circuit to the walls of the waveguide.

The transition results in a slightly higher in-

sertion loss caused by a field disturbance

within the back-short.

The planar realisation of the BUC has to fulfil the

mechanical constraints of feeding the antenna in

an orthogonal way. In contrast, commercially avail-

able BUCs take advantage of the high power han-

dling capability of an in-line transition, while in

consequence, the waveguide connection is not lo-

cated at the heat-sink side of the BUC. Within this

developed VSAT the antenna should be consid-

ered as a possible heat-sink for the BUC. There-

fore, the bottom of the BUC faces the back of the

antenna, which both should provide the waveg-

uide interconnection. Hence, the orthogonal tran-

sition is adopted via a hybrid MS feeding struc-

ture as described by Rautschke et al. in [Rau+17b].

Fig.4.21(a) displays the top view of the rectangular

WR75 waveguide. Within Fig.4.21(b) the feeding

structure of a MS circuit is obtainable and realis-

able as a drop-in circuit. The waveguide feed is a

simple radial stub that reacts as a capacitive patch

located at the E-plane of the waveguide. The cover

of this transition can be depicted from Fig.4.21(c)

reacting as the back-short. An additional screw cen-

tred in the back-short is used to tune its distance to

the feed.

Two of these transitions were interconnected at the

MS reference plane and measured back-to-back

feeding from the WR75 connection. The measure-

ment is de-embedded via a second tier TRL cali-

bration to the WR75 reference plane. By splitting

the obtained T-Parameter, the S-Parameter results

of Fig.4.21(d) represent only one MS to WG tran-

sition. It can be obtained, that the IL = 0.65 dB is

somehow constant over the frequency range of 10-

15GHz with a RL≥20dB. The IL is mainly related

to the conductive losses of the long MS feeding

line (Fig.4.21(b)), which was necessary for posi-

tioning the mounting screws of the WR75 outside

the housing of the BUC. Finally, the BUC can be

either equipped with a SMA-connector2or this MS

to waveguide transition, taking advantage of the

same mechanical dimensions. The feed can also

be realised for supplying to a lower height WG as

described in [Oh+10] or by taking advantage of a

SIW feeding structure as in [Can+15].

2Rosenberger 32K242-40ML5

Chapter 4. Block Up-Converter

(a) (b) (c)

9 10 11 12 13 14 15 16 17

−1.5

−1

−0.5

S21 (dB)

Frequency (GHz)

S21

9 10 11 12 13 14 15 16 17

−30

−20

−10

S11 (dB)

Frequency (GHz)

S22

(d)

FIGURE 4.21: Top view of the MS to WR75 transition (a)

housing (b) with substrate (c) including the back short

(d) deembedded S-Parameter measurements of a transi-

tion.

Housing

By mounting the BUC on the backside of a planar

antenna, one has to consider the weight the BUC

adds to the antenna, changing its centre of gravity.

Consequently, the pointing agility is lowered. The

housing of the BUC compromises between cooling

capacity and size/weight with a limitation of 1kg.

With a simple convection cooling, the thickness of

the cooling-plate is calculated to 13mm, giving the

ability to spread the dissipated power to the side

where additional heat sinks are located. Neverthe-

less, only a limited amount of dissipated power

can be cooled with this thin housing, displayed

in Fig.4.22(b). For a dissipated power exceeding

Pdiss,max ≈80W self heating will occur.

Fig.4.22(a) shows the layout view of the BUC in-

cluding the dc/dc conversion (A), a RF linearisa-

tion (B) and the up-conversion (C). In between the

different sections a shielding wall is realised by a

milled cover attached to via-walls in the substrate.

The height of this shielding chambers is different

for each chamber. Within the areas (A) and (B)

the height of mounted components determines the

minimum height of the chamber. Thus, the area (C)

95 mm

116 mm

RFout

RFin

(a)

RFout

WR75

RFin

SMA

DCin

120 mm

190 mm

20 mm

(b)

FIGURE 4.22: (a) Layout view of hybrid integrated BUC

(b) with housing.

is the main high-frequency section including parts

of the LO, the up-conversion as well as the PA.

The height of this section is limited to the cut-off

frequency of the highest Ku-band operation fre-

quency. Eigen-mode calculations of this housing

were carried out to prevent resonances caused by

this shielding. The RF-interconnections between

the sections (A, B, C) were realised in a lower layer

(cond2). The MS line of layer "cond1" ends in a

blinded via connecting to "cond2". Underneath the

shielding a coplanar line with a reference GND on

RFin

RFout

cond1

cond2

pc1

pc2

via

blinded

via

shielding

wall

FIGURE 4.23: Layoutview of RF-interconnection under-

neath the shielding walls.

Chapter 4. Block Up-Converter

IFin VGA Mix Filter CPL amp CPL PA CPL WR75 RFout

−20

Pout (dBm), conv. Gain (dB)

Pout

conv. Gain

FIGURE 4.24: System simulation of the BUC for a vary-

ing input power level at the IF.

top as well as on bottom is used (Fig.4.23). Be-

hind the shielding another blinded via returns the

signal to the top layer (cond1). The diameter of

the via ring metallisation was tuned as a capaci-

tive post to resonate the via inductance. This RF

interconnection was designed based on a time do-

main reflection (TDR) analysis and shows a mea-

sured RL≥20dB up to 4GHz which is sufficient

for the IF and REF interconnections. In a first ap-

proach, an RF-interconnection was designed using

the same principles but up to the Ku-band frequen-

cies which would enable a separate shielding of

the up-conversion, LO as well as the PA section.

Nevertheless, the uncertainty of the milling depth

of the blind-via, which is ≈50 µm, is degrading the

RL of the interconnection for f0≥6GHz, therefore

this idea could not be realised.

The total size of the BUC including the housing is

190x120x20mm with a weight of 950g. Within the

picture, the BUC is equipped with the 25 W PA. At

the input and output of the layout-view the SMA

connectors are missing because they were not part

of the Reflow mounting process.

4.6 Simulation / Evaluation

The whole transmission chain of the BUC was anal-

ysed within ADS as a budget simulation. All com-

ponents were adopted with characteristic equiva-

lent values to ease the simulation. For example,

the complex large-signal simulation of the PA can

be replaced by a simple model that consists of the

S-Parameters, the saturation power, and the gain

13.6 13.8 14 14.2 14.4 14.6

Frequency (GHz)

η(%), Pout (dBm), Gain (dB)

Gain

Pout

(a)

−32 −30 −28 −26 −24 −22 −20 −18 −16

Gain (dB)

−32 −30 −28 −26 −24 −22 −20 −18 −16

Pout (dBm)

−32 −30 −28 −26 −24 −22 −20 −18 −16

Pin (dBm)

(%)

(b)

FIGURE 4.25: CW measurements of the BUC (a) in satu-

ration with dependency to the frequency and (b) to the

input power Pin.

compression. Furthermore, the frequency genera-

tion can be replaced by an ideal source with a lim-

ited phase-noise and a mixer with an ideal conver-

sion gain paired with second and third order inter-

cept point definitions. A budget of the signal chain

can thus be evaluated like for the output power

and the conversion gain as shown in Fig.4.24. All

lossy networks, like the filters or couplers, result

in a decrease of power level or a reduction in gain.

Overall, a conversion gain of up to 55dB can be

obtained from this simulation. It can be seen that

an increased IF input power to -14dBm is going to

saturate the PA which results in a decreased con-

version gain. Nevertheless, an output power level

of up to 42dBm for the 25W PA was achieved dur-

ing simulation.

For increased accuracy within system simulation,

the complete transmission chain could be analysed

within ADS System-View TM but therefore all sub-

elements needed to be characterized non-linear on

their own, which exceeded the time-frame of this

development.

Chapter 4. Block Up-Converter

20 25 30 35 40 45

Pout (dBm)

Gain (dB)

w/o RFPAL

w/ RFPAL

(a)

20 25 30 35 40 45

−30

−20

−10

Pout (dBm)

Phase (°/dB)

w/o RFPAL

w/ RFPAL

(b)

13.99 13.995 14 14.005 14.01

−60

−50

−40

−30

−20

−10

f (GHz)

normalized PSD (dBm/Hz)

w/o RFPAL

w/ RFPAL

(c)

FIGURE 4.26: Measured output of the BUC (w) and (w/o) linearisation for (a) gain compression (b) AM/PM (c)

spectrum for Pout, avg=39dBm, 32APSK 4 MSym/s.

BUC with 25 W PA

As previously described, the BUC can either be

equipped with a 25W or a 70 W PA. So the evalua-

tion and measurement is split into two parts. The

BUC performance is analysed based on continu-

ous wave (CW) measurements in Fig.4.25(a). A

very flat conversion gain of 55±0.3dB between

13.8 to 14.5GHz can be seen with an output power

higher than 39dBm. The total efficiency exhibits

15%. The power consumption in saturation is only

52W due to the implementation of high efficiency

dc/dc step down converters.

Fig.4.25(b) shows a constant power compression

starting from Pin =-24dBm to Pin =-17dBm, result-

ing in a gain decrease from 60 to 55dBm, which is

typical for GaN technology (soft compression). It

has to be mentioned that the PA can be operated

in the deep compression of Pout, peak =39 dBm even

though it is the 5dB compression of the BUC, with

a rather low increase of IMD products compared to

GaAs or TWTAs.

Nevertheless, based on Eutelsat regulations, a

BUC’s operation has to be limited to its 1dB com-

pression by the fear of increased IMDs. The normal

procedure of levelling a VSAT is that the satellite

operation control increases the input power of the

BUC within 1dB steps upon the point where the

measured output power (in the link) no longer in-

creases in 1dB steps. Even though a BUC is able to

deliver linear higher output power levels, the con-

trol centre will not allow it through this obsolete

procedure.

Compression

Biasing the PA in the Class-AB operation leads to

an increased soft compression. By biasing the PA

with a lower quiescent current its compression de-

creases as already shown in Sec.3.3.5.

The compression behaviour is shown in detail in

Fig.4.26(a) for a 32APSK modulation (PAPR=6.4

dB) with a deep Class-AB to Class-C biasing. The

gain compression is already flattened compared

to the CW measurement (Fig.4.25(b)). The higher

PAPR of the modulation limits the thermal com-

pression of the PA that can additionally lead to a be-

haviour that is misunderstood as soft-compression.

By enabling the linearisation system, the trend-

line of the gain compression is further reduced

(Fig.4.26(a) (w) RFPAL). The deeper Class-C bias-

ing results in a slight overshoot of the AM/PM

behaviour for the plot (w/o) RFPAL in Fig.4.26(b),

while (w) RFPAL the phase can be flattened.

By comparing this AM/PM plot with the one orig-

inally obtained for the stand-alone PA it needs to

be mentioned that the spread of the phase points

is wider in here. This can be explained by the

higher amount of phase noise within the BUC

compared to a laboratory signal generator. The

output spectrum plot in Fig.4.27 clearly shows the

improvement of the out-of band energy (w) RFPAL

enabled.

As can be seen in Fig.4.27(a) the implemented RF-

PAL is able to reduce the ACPR of a 1.5MSym/s

QPSK within 5dBc to 35dBc for Pout, avg = 39 dBm.

While the BUC w/o RFPAL is already able to fulfil

Chapter 4. Block Up-Converter

−4 −2 0 2 4

−60

−50

−40

−30

−20

−10

Frequency (MHz)

normalized PSD (dBm/Hz)

MASK

w/o RFPAL

w RFPAL

(a)

−20 −10 0 10 20

−60

−50

−40

−30

−20

−10

Frequency (MHz)

normalized PSD (dBm/Hz)

MASK

w/o RFPAL

w RFPAL

(b)

−20 −10 0 10 20

−60

−50

−40

−30

−20

−10

Frequency (MHz)

normalized PSD (dBm/Hz)

MASK

w/o RFPAL

w RFPAL

(c)

FIGURE 4.27: Normalized measured power spectral density of the BUC (w) and (w/o) linearisation for (a) QPSK

1,5 MSym/s (b) QPSK 10 MSym/s (c) 16APSK 10MSym/s for Pout, avg = 39 dBm.

the mask at saturated output power, the BUC (w)

RFPAL is able to hold the more stringent military

restrictions. The improvement for a 10MSym/s

QPSK is far better resulting in 10dBc towards

42dBc ACPR (Fig.4.27(b)). This is related to the

internal bandwidth of the RFPAL system, which

starts with 1MHz.

Particularly higher order modulation schemes like

16APSK can benefit from this technique. As can

be seen in Fig.4.27(c) a 16APSK output spectrum

is improved with more than 10dBc, now holding

the mask. It has to be pointed out that this 16APSK

has a 1dB higher PAPR compared to QPSK. There-

fore, using the BUC with the same average out-

put power for a QPSK or a 16APSK results in a

1dB higher linear peak power. Towards the trend

of lowering the α≤0.35 used within DVB-S2 or

DVB-S2X, the more stringent requirements of lin-

earity can be fulfilled with this linearisation tech-

nique without decreasing the output-power level

of the BUC.

BUC with 70 W PA

The BUC is further analysed with the 70 W Kuup

PA described in Sec.3.3. The improvements re-

garding linearity for various output signals are

already stated in Sec. 3.3.5. The limitation of us-

ing this medium power amplifier within the small

housing of this BUC is the amount of dissipated

power. Tab. 4.3 states the input as well as output

power of the BUC equipped with the 25W as well

as the 70W PA. The usage of a QPSK signal with

TABLE 4.3: Comparison of both PAs in the BUC

f0Pdc Pout,pk PAPR PAE

(GHz) (W) (W) (dB) (%)

25W PA 13.75 51 19 3.9 13

α=0.35 14.00 52 19.4 3.9 14.3

4MSym/s 14.25 50.9 20 3.9 14.5

QPSK 14.50 52 19.6 3.7 14.7

70W PA 13.75 128 40.7 3 16.3

α=0.35 14.00 122 40.8 3.1 16.2

4MSym/s 14.25 119 42.5 3.4 17

QPSK 14.50 117 40.9 3.1 17

70W PA 13.75 93 37 4.4 13.9

α=0.05 14.00 93.8 39 4.8 14.4

4MSym/s 14.25 86.9 38 5.1 15.5

32APSK 14.50 92 38 4.5 14.9

the 70W PA is described in the second row, with

an extremely high power consumption of ≥117W.

Here the PA is driven to a high compression re-

ducing the PAPR from initially 3.9dB to only 3dB.

This leads to a high self-heating which itself limits

the output power to Pout,avg =20W. The resulting

PAEsys depends on the Pout,avg in relation to the

system power consumption (Appx.A.85).

The 70W PA should only be seen as an extension

for the use with signals towards higher modula-

tion schemes for this small size BUC. By applying

a 32APSK (α=0.05) the measurements indicate a

Pout,avg =14W with up to Pout,pk =39 W while hold-

ing the Eutelsat mask. The power consumption is,

due to the increased PAPR, lowered to ≥86W re-

sulting in an excellent PAEsys of up to 17%.

In comparison to the modulated measurements of

the PA only (Sec.3.3.5) the considerably high losses

Chapter 4. Block Up-Converter

of the output coupler as well as the MS to WG tran-

sition lowers the output power. Furthermore, the

imperfect heat-sink of the BUC adds self-heating

to the PA, while in the stand-alone measurement

an almost perfect water cooling was attached.

Environmental Tests

The previous measurements state a proper be-

haviour of the BUC within laboratory conditions.

Nevertheless, the described functions needed to

be proven under bad thermal conditions as well.

So environmental measurements were carried out

within a thermal chamber. The temperature of the

chamber was changed within a time-frame of four

hours between 0◦C and 45◦C room-temperature

over the course of a week. The resulting output

power of the BUC, its power consumption as well

as the resulting output power spectrum was moni-

tored.

Fig.4.28 visualizes the temperature behaviour of

the chamber and the housing of the BUC during

eight hours. No additional cooling was applied to

the housing of the BUC. It can be obtained that ex-

tremely high temperature values of up to 68◦C for

the housing were measured at 45◦C room tempera-

ture of the chamber. Over the course of the week a

change in output power of ±0.4dB was observed.

In addition, the IMD5 products rise with an in-

creased temperature, but are still compensated by

the linearisation to fulfil the mask.

This environmental analysis does not represent

typical EN60068 analysis but indicates a proper

working for additional outdoor usage.

4.7 BUC Summary

Within this chapter, a design procedure of a hybrid

Ku-band BUC has been presented. Beginning with

0246810

Time (H)

T (°C), Pout,avg (dBm)

Tdesired

Tchamber

Thousing

Pout,avg

FIGURE 4.28: Measured temperature behaviour within

climate chamber of the BUC equipped with the 25W PA

for a QPSK signal with Pout,avg =39dBm.

a design description, all components of a BUC,

namely the LO generation, up-conversion, filter-

ing as well as the amplifier and power amplifiers

are described. All parts were evaluated individ-

ually as well as in the system. The BUC can be

equipped with a Pout =25W amplifier resulting in

an output power up to 39dBm with PAEsys =15%

for a CW excitation. Through using QPSK signals,

the peak output power increases to Pout,pk =20W

due to the lowered self-heating.

With the aim of using higher order modulations

and therefore an increased PAPR the larger Kuup

amplifier (Pout =70W) can be located in the BUC.

Measurements with a 32APSK modulation indi-

cate Pout,pk =40W with up to PAEsys = 17%.

The BUC is equipped with an IF-pre-distortion

that is able to improve the ACLR for QPSK mod-

ulated measurements within 10dBc. Real time

centre frequency and signal bandwidth detection

is realised without access to the baseband signal.

This work has shown that a linearisation of the PA

in a BUC can be done within the IF-range. An IF

pre-distortion delivers good results for decreasing

the spectral regrowth as well as minimizing the

EVM of modulated SatCom signals. The technique

is easy to implement directly within the BUC and

can extend the throughput of the uplink as well as

its efficiency.

Chapter 4. Block Up-Converter

4.8 BUC Discussion

The realised BUC cannot be directly compared to

the state-of-the-art results due to the lack of pub-

lished BUCs. The results are thus compared to

commercially available BUCs. It can be noted, that

commercially BUCs are nowadays made of GaAs

up to a power level of ≈25W. GaN is starting

to build the bridge with medium power BUCs to-

wards high power TWTA based BUCs, which are

mainly used for broadcasting and the military. A

comparison is stated in Tab.4.4.

Starting with Pout,1dB =39dBm there are three near

identical BUCs based on GaAs technology given in

[Agi16a], [Nor15a], [NJR17a]. The output power is

defined with up to 8W resulting in a low PAEsys of

only up to 10%. In comparison, the developed low

power BUC25Wshows a lower Pout,1dB =38 dBm

due to the typical GaN soft-compression. Never-

theless, the output power is with up to 20 W, far

higher – also the included linearisation enhances

the output power level to linear values higher

than Pout,1dB, but only for modulated signals. The

BUC can furthermore take advantage of the higher

drain efficiency resulting in a PAEsys of 14.5%.

The PAEsys for the medium power BUCs are cal-

culated considering the 3dB back-off power con-

sumption in relation to the 3dB back-off output

power (Appx.A.85). In consequence, the PAEsys is

related to a realistic operation with a compressed

QPSK signal. It should be mentioned that the

first two entries do not state the technology used

[Agi16b], [Nor15b]. However, based on their high

power consumption, a combined GaAs technology

can be assumed. In addition, they can take advan-

tage of a high Pout,1dB through the use of GaAs. The

third mentioned BUC uses a GaN MMIC and is

able to increase its PAEsys of up to 11.4% [NJR17b].

Nevertheless, it does not state its Pout,1dB due to

the assumed soft compression of GaN. Furthermore,

no linearisation technique is included in this BUC

which is why, it is assumed that the BUC needs

to be operated in a high back-off to fulfil Pout,1dB

compression requirements.

In comparison to this commercially available BUC,

the developed BUC70Wcan achieve an equal

Pout,pk while producing significantly less dissi-

pated power. It can take advantage of the al-

ready improved PAEsys with regard to the PA itself

(Tab. 3.8) and does not lose power in an output

combining like [Agi16b], [Nor15b].

TABLE 4.4: Comparison to commercial BUC in the extended Ku-band (13.75-14.5GHz)

tech Pout,1dB Pout,pk Pdc Gain PAEsys PN Dimensions

@1kHz L x W x H

low power: (dBm) (W) (W) (dB) (%) (dBc/Hz) (cm)

Agilis ALB [Agi16a] GaAs 39 8 85 64-72 9.4 -73 28x14x10

Norsat 1081XRTS [Nor15a] GaAs 39 8 80 56-66 10 -70 28x13x13

NJT8318 [NJR17a] GaAs 39 8 80 59-65 10 -70 18x13x8

BUC25WGaN 38 20152 55-60 14.5 -80 19x12x2

medium power:

ALB128 slim [Agi16b] ? 46 40 350370 5.7 -75 34x35x4

MEDIBKU040 [Nor15b] ? 44 40 270365 9 -73 20x13x12

NJT8371 [NJR17b] GaN 40 220368-74 11.4 -70 23x15x10

BUC70WGaN 43 401130365-71 17 -80 19x12x2

BUC70WGaN 42 40292465-71 16 -80 19x12x2

1QPSK

232APSK

33dB back-off 4for 32APSK 4.5dB

back-off

5 Satellite Link

Within this section, the developed hardware, namely

the PA and the BUC, are going to be evaluated in a

Satellite Link.

A detailed description of the Link Scenario is given

in Sec.5.

The characteristic budgets of the Link are calcu-

lated in Sec.5.1 while the necessary analysis and

nomenclature is given in Appx. A.6.

The evaluating Link Test is described in Sec.5.2,

taking a Video-on-Demand (VoD) scenario into

consideration. Finally, the results are summarised

in Sec.5.3.

Data Link

Television satellite services are widely realised

with a single uplink, casting to any number of re-

ceivers back on earth (broadcast Fig.5.1(a)). Nowa-

days, fixed satellite services (FSS) are widely used

for classical telecommunications, television as well

as back-haul solutions for data communications.

In contrast to a classical broadcasting SatCom, a

data connection via satellite needs to be directed

within two directions. One is called the forward

link (FWL), which directs to the satellite and is

relayed back to earth. The receiving terminal on

earth needs to reply to the transmission terminal

with an acknowledgement (Ack) within the return

link (RTL) via satellite (Fig.5.1(b)). Several topolo-

gies can be realised, for example, a single cast

uplink between a HUB and a VSAT results in a

point-to-point connection. By increasing the num-

ber of VSATs a Star-Network is created enabling

the typical application of several back offices com-

municating with one main office. An interconnec-

tion from one VSAT to another has to be relayed

through the HUB, which reduces frequency alloca-

tion and lowers the necessary EIRP of a VSAT.

HUB

FWL

(a)

HUB

FWL

RTL

VSAT

(b)

FIGURE 5.1: (a) classical SatCom with broadcast FWL (b)

data link via HUB and VSAT with additional RTL (Star-

or Mesh-Network).

Within a Mesh-Network all VSATs can generate in-

terconnections to each other as well as the HUB.

This is by far the most expensive network with a

maximum amount of frequency allocation as well

as a high EIRP of each VSAT. The amount of al-

located frequencies can be reduced by time divi-

sion protocols synchronizing several forward and

return links. The needs for satellite interconnec-

tions increase, as a backup solution for time sensi-

tive and critical markets. What these markets have

in common is high investment as well as the oper-

ating costs to maintain the satellite link, which can

be paid off quickly, during a breakdown of the con-

ventional data communication system (e.g. mobile

communication, telephone service).

Among these classical services, modern satellites

provide an increased number of transponders to

their precursor. A new launched satellite is there-

fore able to provide more data links than its pen-

dant of the past. In particularly, the total number

of Ku-band transponders has increased within the

past few years, as can be seen in Fig. 5.2. Further-

more, new techniques like high throughput satel-

lites (HTS) use spot beams and therefore frequency

re-usage within a satellite to increase the possible

data rate via satellites [Uni11]. This progress low-

ers the costs-per-bit of a satellite link for its user.

Apart from that, new markets can grow by the

Chapter 5. Satellite Link

1985 1990 1995 2000 2005 2010 2015 2020

250

500

750

1000

Year

No. of transponders

C−band

X−band

Ku−band

Ka−band*

*including spot beams

FIGURE 5.2: Launched transponders per year (data

taken from [Sat]).

increasing demand in selectable video content, in

contradiction to the classical broadcasting televi-

sion industry. VoD services can be realised via

HTS through the use of a bidirectional VSAT for

the end user. The request is sent from the VSAT

in a rather small FWL with mainly signalling data.

A HUB can reply within the RTL with the video

content. An additional content provider needs to

supply either selected or all content via a terres-

trial network to the HUB. The increased number

of spot-beams located on this HTS can, in com-

bination with a transponder sharing increase the

possible number of users per coverage.

To achieve a data connection in remote regions a

terminal interconnection to a hub station via satel-

lite can be the only solution among mobile commu-

nication realised by VSATs.

Link Scenario

Within the used satellite link there are two earth

terminals that both react as transceivers. The satel-

lite itself simply converts an incoming signal in

frequency and amplitude and returns it to earth

within its transponder. The larger terminal on

earth can be defined as HUB and the other as VSAT.

It needs to be mentioned that normally all directed

interconnections (FWL up, FWL down, RTL up,

RTL down) are defined with different frequency

allocations. Thus, FWL as well as RTL are con-

tinuous in a two-way interconnection. Both earth

terminals are equipped with a satellite modem that

modulates/ demodulates Ethernet signals to an IF.

While choosing a data link, the link budget has

30 35 40 45

T Antenna Gain (dBi)

PA output power (W)

41 dBW

46 dBW

49 dBW

52 dBW

FIGURE 5.3: Various typical EIRP levels are calculated

based on antenna gain versus PA output power.

to be calculated for the FWL as well as the RTL

separately. The size of the dish (and therefore the

antenna gain) influences the transmitting as well

as the receiving signal strength. In conclusion, the

HUB terminal has to compensate for the lower

antenna gain of the VSAT by an increased size of

its own dish to improve the carrier to noise (C/N)

distance.

Nevertheless, VSATs are limited to a certain equiv-

alent isotropically radiated power (EIRP) either in

terms of the antenna gain or the output power of

the block up-converter (BUC) as can be obtained

from Fig.5.3.

Typical EIRP levels of {41,46, 49, 52}dBW for com-

mercially available VSATs are displayed regarding

their BUC power level vs. their antenna gain. For

example, by assuming an antenna gain of 40 dBi

and a BUC output power of 10W an EIRP of

49dBW can be obtained while mispointing and

interconnection losses are assumed as described in

[Mar03].

By increasing the antenna gain, which comes along

with increasing the size of a dish or planar antenna,

the VSAT gets bulky and impractical. Increasing

the power of the BUC normally leads to a very

heavy housing with a higher power consumption

and a rapid growth of its costs. The utilized tech-

niques given in Sec.3for the PA and in Sec.4for

the BUC lead to a lightweight solution with a high

output power that is affordable. A functional test

of this BUC, a LNB as well as a planar antenna is

described within the following subsections.

Chapter 5. Satellite Link

−150

−100

−50

100

Power Level in (dBm)

Modem out

BUC

Cable

TX Antenna

misspoint losses

athmosphere losses

rain losses

freespace losses

SAT

(a) uplink

−150

−100

−50

100

Power Level in (dBm)

RX Antenna

RX Power

Input repeater

TX HPA

TX Antenna

(b) transponder

−150

−100

−50

100

Power Level in (dBm)

SAT

freespace losses

physical losses

RX antenna

LNB

Modem in

signal

noise

FIGURE 5.4: Link budget analysis calculating the equivalent power level (red) as well as the equivalent noise level

(blue) for a 4MHz QPSK signal displaying (a) the uplink (b) the transponder (c) the downlink.

5.1 Link Budget

All gains and losses of an interconnection from the

base station transmitter to the opposite receiver are

accounted for in a link budget. It therefore indi-

cates the signal strength to the noise of the signal

within a link. A so-called margin can be defined by

taking into account the transmitted power, the free

space loss and the noise. Only a positive margin

indicates a proper working link. An example cal-

culation is done to clarify the power levels within

the different subsystems of the link. The related

equations are given in [Rod01, 305ff] and defined

in the Appx.A.6.

One-Way Link Budget

With regard to the uplink the calculation starts

with the output power of the modem (-6dBm in

red) located in the IF (Fig. 5.4(a)). Afterwards,

the conversion of the BUC to the TX frequency

(13.81GHz) results in an output power level of

48dBm (60W) at the WR75 reference plane. Inter-

connection losses to the antenna lower the power

level within 0.5dB. With a ∅2.4m dish the signal

is non isotropically radiated which gains within

48dB to the total EIRP (96dBm=66dBW) of the

transmitting ground station. This antenna can-

not be ideally pointed to the satellite, which is

why mispoint losses (0.5 to 1dB) occur. More-

over, the radiated signal passes through rain (1.5-

6dB) and the atmosphere (≈1dB) which further

decreases the power level. The main degrada-

tion of power occurs within the free space losses

(≈35786km ˆ= 210dB) resulting in a power level of

only -113dBm at the GEO position of the satellite.

The budget of the satellite transponder is visu-

alized in Fig.5.4(b), starting with -113 dBm, as

previously described, which increases with the

RX antenna. The internal LNAs as well as the

conversion, changing the TX frequency to the

RX frequency, levels the signal before the high

power amplifier (HPA1) amplifies the level up to

the transponder TX power level. At the end, the

TX antenna of the satellite increases the power

level to 89dBm=59dBW. Spot beams or conven-

tional dishes are used depending on the type of

satellite. It can be noted that the TX power level

of the satellite is normally less than the TX power

used from the earth station terminal. Special care

must be taken not to overdrive the transponder

with a high output power coming from the uplink

base station. The transponder works in a FDMA

converting multiple signals coming in to multiple

frequencies going out. Therefore, each and every

user has to maintain a certain power level from

its base station, not to exceed the saturation flux

density of the HPA located on the satellite.

Up to now, the noise (in blue) is not calculated for

the uplink as well as the transponder. The receiv-

ing thermal noise of the transponder is highly re-

lated to the orbital position and the position of the

HUB. Within the transponder the C/N is located in

the range of 20 to 30dB. For a 4MHz QPSK signal

α=0.25 the noise-density can be calculated to a rep-

resenting power level, which therefore determines

1conventionally a TWTA

Chapter 5. Satellite Link

TABLE 5.1: (a) Uplink calculation within the FWL; (b) Downlink calculation within the FWL; (c) resulting total link

margin within the FWL (Berlin to AM44; 14.0722GHz (H) up; 11.5222 GHz (V) down; 0.5 MSym/s; QPSK; FEC 3/4;

α=0.35; Pout =10W; 99.5% availability ITU-R)

(a)

uplink clear sky rain up

uplink EIRP 53 53 dBW

transponder IBO 7.85 7.85 dB

IBO/carrier 28.29 29.95 dB

antenna mispoint 0.3 0.3 dB

free space loss 207.23 207.23 dB

total attenuation 0.18 1.86 dB

C/N (th) 21.98 20.3 dB

C/(N+I) 21.96 20.28 dB

Eb/(N0+I0)20.55 18.87 dB

(b)

downlink clear sky rain down

sat EIRP 50.5 50.5 dBW

transponder OBO 5.18 5.18 dB

OBO/carrier 25.62 25.62 dB

antenna mispoint 0.3 0.3 dB

free space loss 205.5 205.5 dB

total attenuation 0.14 1.16 dB

total system noise 127.75 180.62 K

G/T 17.44 15.93 dB/K

C/N (th) 8.28 5.76 dB

Eb/(N0+I0)6.82 4.32 dB

(c)

totals per carrier (end to end) clear sky rain up rain down dual fade

C/N (th) 8.1 6.42 5.564 3.97 dB

C/(N+I) = [Es/(N0+I0)] 8.05 6.38 5.62 3.95 dB

system margin 1 1 1 1 dB

net Es/(N0+I0)7.05 5.38 4.62 2.95 dB

required Es/(N0+I0)(for QPSK) 3.1 3.1 3.1 3.1 dB

excess margin 3.95 2.28 1.52 -0.15 dB

the distance to the signal level.

The downlink path (Fig.5.4(c)) can take advantage

of less free-space losses (≈205dB) than the uplink,

due to the slightly lowered frequency (11.012GHz).

In addition, the atmospheric and rain losses are

summed up to the physical losses (3dB). An an-

tenna size of ∅1.2m will result in a gain of 41dB

boosting the signal level to -78dBm. As can be

obtained from Fig.5.4(c), the signal-to-noise ratio

(SNR) degrades extremely at the budged position

of the RX antenna (only ∅1.2m). The next signifi-

cant decrease of SNR is related to the Noise-Figure

of the LNA located in the receiving earth station.

The receiving antenna on earth cannot take ad-

vantage of a cold surrounding, which is why in

combination with the LNA a gain to noise temper-

ature (G/T) of 16dB/K limits the signal quality. A

total system SNR of 12dB is visualized, which is

sufficient for a demodulation. It has to be pointed

out, that an increased absorptive rain attenuation

directly reduces the earth station G/T which is

why the receiving antenna diameter has to be in-

creased, preventing an increase of rain attenuation

in the downlink.

The complexity of the used signal determines the

requirements regarding the normalized SNR. Dur-

ing a link period of high SNR the modulation can

be increased by maintaining the same signal band-

width. In consequence, the data rate increases as

well. During a period of rain fade the SNR is de-

creased which makes a decrease of the modulation

or an increase of the forward error correction (FEC)

necessary. However, the link budget is calculated

for one modulation that requires a certain Es/(N0+

I0). In addition, losses due to rain in the uplink,

downlink or both are added to the calculation.

Apart from these simple calculations additional up-

link intermodulation needs to be considered.

Two-Way Link Budget

The link budget as well as the transmission plan

is normally calculated by the satellite provider

for the end-user. Nevertheless, to prove a proper

working link between VSAT and VSAT or VSAT

and HUB the margin is calculated for an inter-

connection between Berlin (52◦31’51”N) and a

satellite called Express-AM44 (11◦W). The result-

ing angle for the VSAT is 209.63◦azimuth, with

25.83◦elevation. The previous shown link budget

Chapter 5. Satellite Link

TABLE 5.2: (a) Uplink calculation within the RTL; (b) Downlink calculation within the RTL; (c) resulting total link

margin within the RTL (Berlin to AM44; 14.0737GHz(H) up; 11.5237GHz(V) down; 0.3MSym/s; QPSK; FEC 3/4;

α=0.35; Pout =10W; 99.5% availability ITU-R)

(a)

uplink clear sky rain up

uplink EIRP 48 48 dBW

transponder IBO 7.85 7.85 dB

IBO/carrier 33.38 35.07 dB

antenna mispoint 0.3 0.3 dB

free space loss 207.23 207.23 dB

total attenuation 0.18 1.87 dB

C/N (th) 19.12 17.43 dB

C/(N+I) 19.09 17.41 dB

Eb/(N0+I0)17.68 16 dB

(b)

downlink clear sky rain down

sat EIRP 50.5 50.5 dBW

transponder OBO 5.18 5.18 dB

OBO/carrier 30.71 30.71 dB

antenna mispoint 0.3 0.3 dB

free space loss 205.5 205.5 dB

total attenuation 0.14 1.16 dB

total system noise 137.54 190.42 K

G/T 19.97 18.5 dB/K

C/N (th) 7.64 5.21 dB

Eb/(N0+I0)6.19 3.78 dB

(c)

totals per carrier (end to end) clear sky rain up rain down dual fade

C/N (th) 7.35 5.66 5.04 3.35 dB

C/(N+I) = [Es/(N0+I0)] 7.3 5.6 5.1 3.33 dB

system margin 1 1 1 1 dB

net Es/(N0+I0)6.3 4.63 4.01 2.33 dB

required Es/(N0+I0)(for QPSK) 3.1 3.1 3.1 3.1 dB

excess margin 3.2 1.53 0.91 -0.77 dB

is proven by the software Satmaster Pro [Arr99]

with an extension of the RTL and a more detailed

intermodulation analysis2.

FWL Budget

The FWL is calculated based on a VSAT with a dish

of ∅1.2m diameter that results in an antenna gain

of 43dBi. Equipped with a 10W BUC (BUC25W)

an EIRP=53 dBW can be achieved. As can be

seen in table 5.1(a) based on the uplink EIRP and

the knowledge of the transponder the normalized

SNR (Eb/(N0+I0)) can be calculated. I, as well

as I0denotes, that a carrier intermodulation is be-

ing considered. Furthermore, the same calculation

can be done for the downlink in table 5.1(b). Here

the dish size of the receiver terminal and its G/T

becomes significant. In addition, the calculation is

divided into one situation with clear sky that rep-

resents the free space losses, and one called rain

that adds losses due to rain-fade. Note that the

influence of rain, clouds or snow can impact the

2The intermodulation within a link is clarified in ap-

pendixA.119 and should not be mixed-up with the IMD that

is related to the saturation of a PA

uplink, the downlink or both. Tab. 5.1 (c) summa-

rizes the margin that is influenced by the uplink

and the downlink as well. A required normalized

SNR in form of Es/(N0+I0)is defined with 3.1dB

that represents the dynamic range necessary, for

demodulating a QPSK (FEC 2/3) [ETS09, 34 ff.].

It can be seen that a link works for the situation

clear sky as well as rain up due to its positive excess

margin. Only for the condition of a dual rain-fade

no link can be achieved.

RTL Budget

The counterpart of the interconnection starts with

the VSAT, its planar antenna (38 dBi) and the devel-

oped BUC25Wresulting in 45dBW EIRP (Tab.5.2).

The lower EIRP compared to the previously re-

ported HUB results in a reduced IBO per carrier at

the satellite (Tab.5.2 (a)). Hence, the OBO per car-

rier of the transponder is reduced as well, which in-

creases the G/T within the downlink (Tab.5.2 (a)).

It can be noted that only a positive excess mar-

gin can be achieved during the situation clear sky,

and rain up while an additional rain down suffers

from the higher OBO of the transponder. Only

Chapter 5. Satellite Link

for the condition of a dual rain-fade no link can be

achieved.

5.2 Link Test

The HUB is realised via a classical satellite terminal

consisting of a dish mounted on a fixed or steer-

able support. A feed-horn is located within the fo-

cal point of the dish. This feed-horn is formed as a

circular wave-guide towards the dish. An orthog-

onal mode transducer (OMT) afterwards splits the

TX from the RX frequency range and ends in rect-

angular wave-guides. The OMT is able to achieve

TX to RX isolation of up to 80dB. The BUC as well

as the LNB gets screwed to this wave-guides. By

twisting this feed around the beam axis in the fo-

cal point a vertical or horizontal polarisation can

be achieved.

The VSAT called EASYSTAR, that is an outcome

of the project ISISTAR [Rau+17b], features an inte-

grated planar LNB as well as the BUC25Won the

backside of a three layer passive planar antenna

[Gei+17] (Fig.1.2). The three layer antenna consists

of an antenna array supported by two feeding net-

works each for the TX as well as the RX frequency

range. It is intentionally designed to provide a 90◦

phase shift between TX and RX to increase the iso-

lation. It can therefore be used without a separate

OMT. All electric components are assembled on

the back-side of the antenna. EASYSTAR can be

easily pointed to the satellite by its spherical head

in the mechanical centre of the backside plate. By

twisting the planar antenna perpendicular to the

beam axis its polarisation is tuned.

HUB to VSAT (Star-Network)

The first measured scenario displays the usage of

a Star-Network with one HUB station located in

Munich directing to a VSAT in Berlin. The anal-

ysed link can be divided into two different mea-

surement scenarios separating the FWL from the

RTL. A detailed Link-Budget analysis is given in

the Appx.A.6.

-210 dB

Eutelsat 33E

4.6m

◊ 0.65 m

~55 dBi

~38 dBi

FIGURE 5.5: FWL HUB to VSAT.

TABLE 5.3: Measured data-rate HUB to VSAT in FWL.

TX RX RX

13930.87MHz 11135.37MHz

5 MSym/s1(C/N 9.8dB) (theor. limit)

FEC 1/2 4.5 MBit/s 5 MBit/s

FEC 2/3 5.2 MBit/s 6.6MBit/s

FEC 3/4 5.9 MBit/s 7.5MBit/s

FEC 5/6 6.9 MBit/s 8.3 MBit/s

16MHz

FWL (HUB to VSAT)

Fig.5.5 shows the FWL directing from the HUB to

the VSAT. The HUB is realised with a ∅4.6m dish

(ND SatCom) that provides a 5MSym/s (≈6MHz)

QPSK uplink (DVB-S1). The TX antenna gain

is 55dBi which is powered by a BUC delivering

Pout =10W resulting in up to 65dBW EIRP.

The downlink ends up at EASYSTAR with a mea-

sured sufficient high C/N of 9.8 dB. Using a for-

ward error correction (FEC) of 1/2up to 4.5MBit/s

throughput is achieved (Tab.5.5). Note that the

TCP overhead lowers the measured data-rate in

comparison to the theoretically 5MBit/s. By re-

ducing the FEC the data-rate increases over 5.2

MBit/s and 5.9MBit/s of up to 6.9MBit/s for FEC

5/6 which represents a spectral efficiency of 1.65.

The modem used (Romantis UHP1000) was only

able to realise a QPSK modulation, by firmware

restrictions, which is why no higher order modu-

lation schemes could be selected. The measured

C/N of 9.8dB is theoretically high enough for the

usage of a 8PSK with FEC 5/6 with a spectral ef-

ficiency of 2.5 [ETS09, 34 ff.]. This would further

increase the data-rate of up to 10.5 MBit/s. With

Chapter 5. Satellite Link

-210 dB

Eutelsat 33E

4.6m

◊ 0.65 m

~53 dBi

~38 dBi

FIGURE 5.6: RTL VSAT to HUB.

TABLE 5.4: Measured data-rate HUB to VSAT in RTL.

RX RX TX

11130.87MHz 13935.37MHz

(C/N 9.7dB) (theor. limit) 0.5 MSym/s1

0.4MBit/s 0.5 MBit/s FEC 1/2

RX RX TX

(C/N 9.4dB) (theor. limit) 1.2 MSym/s2

1MBit/s 1.2 MBit/s FEC 1/2

10.6MHz 21.3MHz

an increased C/N future DVB-S2 compatible mod-

ulation schemes, like 16APSK or 32APSK, have the

ability to significantly increase this data rate.

RTL (HUB to VSAT)

Fig.5.6 shows the RTL directing from the VSAT to

the HUB. The TX antenna gain is 38dBi equipped

with the developed BUC25W, which is able to de-

liver Pout =10W for a DVB-S1 QPSK signal. The

resulting EIRP is 48 dBW for the RTL. Due to the

lower EIRP of the RTL in comparison to the FWL,

the signal bandwidth is lowered to 0.5MSym/s

pursuing a higher spectral density at the receiver

of the HUB. The receiving antenna gain at the HUB

is reduced to 53dBi by the lowered RX frequency.

The measured C/N of 9.7 is sufficiently high for

demodulating the signal at the receiver with a

data-rate of 0.4MBit/s (Tab.5.4). By increasing the

signal bandwidth to 1.2MSym/s up to 1MBit/s

was achieved for the RTL while the C/N was re-

duced to 9.4dB.

-210 dB

AM44

1.2m

◊ 0.9 m

~43 dBi

~38 dBi

FIGURE 5.7: FWL VSAT to VSAT.

TABLE 5.5: Measured data-rate VSAT to VSAT in FWL.

TX RX RX

14072.2MHz 11522.2MHz

0.5 MSym/s1(C/N 6.4dB) (theor. limit)

FEC 1/2 0.4 MBit/s 0.5 MBit/s

1.2 MSym/s2(C/N 6.4dB) (theor. limit)

FEC 5/6 1 MBit/s 1.2MBit/s

10.6MHz 21.3MHz

VSAT to VSAT (Mesh-Network)

The second scenario represents a link connection

between two VSATs which is more difficult either

in terms of a lowered TX EIRP as well as due to the

lowered RX antenna gain. One VSAT was realised

with a smaller dish of only ∅1.2m and a 10 W BUC,

while the other VSAT is the already known EASYS-

TAR. The satellite AM44 was used on transponder

D3. This scenario is equal to the previously calcu-

lated link-budget of Sec.5.1.

FWL (VSAT to VSAT)

The FWL is directed from the dish based VSAT to

EASYSTAR (Fig. 5.7). With the use of 43dBi TX an-

tenna gain the EIRP is 53dBW. With a 0.5 MSym/s

bandwidth a C/N of 6.4dB was achieved during

excessive rain. This results in 0.4MBit/s data-rate

for FEC of 1/2 with up to 1MBit/s for FEC of 5/6

(Tab. 5.5).

Chapter 5. Satellite Link

-210 dB

AM44

1.2m

◊ 0.65 m

~43 dBi

~38 dBi

FIGURE 5.8: RTL VSAT to VSAT.

RTL (VSAT to VSAT)

The RTL from the VSAT to the dish based VSAT

(Fig.5.8) was also realised with 0.5 MSym/s, re-

sulting in a measured C/N=6.1dB (Tab.5.6). An

equal data-rate of 0.4MBit/s was achieved for the

RTL, as with the FWL. One application of this

VSAT to VSAT interconnection could be to pro-

vide two-way (internet) into remote regions. The

achieved data-rate was sufficient for surfing with

the restriction of the additional round trip time

delay. In spite of the rather low data-rate the link

was even sufficient for starting video streams.

TABLE 5.6: Measured data-rate VSAT to VSAT in RTL.

RX RX TX

11523.7MHz 14073.7MHz

(C/N 6.1dB) (theor. limit) 0.5 MSym/s1

0.4MBit/s 0.5 MBit/s FEC 1/2

10.6MHz

5.3 Summary

Within this chapter, the designed BUC equipped

with the previously designed PA was attached to

a planar VSAT. The VSAT was tested in a data

satellite link connected to a HUB station. The

link shows a sufficient C/N level of 9.4dB and up

to 1MBit/s throughput in the RTL directed from

VSAT to HUB. A VoD application was used for

the satellite link. A video request was sent via the

RTL with a low amount of data. The FWL can

take advantage of its high data-rate for providing

up to Full-HD video content (1920x1080 H.264 4-

8MBit/s). The latency of the link is not important

for VoD content. Starting from 0.5MBit/s data-

rate a common VoD stream can be commenced.

By using higher order modulation schemes, the

data-rate could easily fulfil the requirements of 4K

content (3840x2160 H.265/HEVC 16-25MBit/s).

In addition, a Mesh-Network topology was adap-

ted realising a VSAT to VSAT interconnection with

up to 0.5MBit/s data-rate. The intention of realis-

ing a two-way (internet) connection was achieved.

The small mechanical dimension of the BUC as

well as great performance data indicate the good

perspectives of GaN-HEMT for future VSAT re-

lated SatCom applications.

6 Conclusion

In this thesis, an extensive design procedure for

efficient two-stage GaN-HEMT PAs in the Ku-

band has been presented. Starting with an ideal

transistor approximation, the design constraints

were theoretically analysed. A Load/Source-Pull

methodology has been used with a systematic de-

sign approach to develop the matching circuits.

The classical Load/Source-Pull has been extended

to a Multi frequency Load/Source-Pull methodol-

ogy to gather for a more optimum design. Effort

was spent for the EM-modelling of all parasitics

and the matching circuits to reduce the effects of

manufacturing constraints.

The procedure was later validated by implement-

ing the two stage PA based on two 70 W bare-die

GaN-HEMT devices. Simulated and measured re-

sults of this PA showed a very good agreement.

Large-signal measurements (CW) depicted more

than 50W output power in the desired frequency

range of interest with more than 23% PAE. These

results were achieved while maintaining a high

saturated gain of ≥15dB. Linearised modulated

measurements using a 16 MSym/s QPSK (DVB-

S) signal demonstrate an average PAE of 21% by

more than 30W output power (70 W peak) while

holding the linearity requirements.

The derived design methodologies have been used

to build a working adoption of the MIC PA in

a lower (12.75-13.5GHz) as well as extended fre-

quency range (12.75-14.5GHz). Both designs have

shown a good agreement between measurement

and simulation. While the first one enhances the

achieved output power to more than 80W with

more than 34% PAE, the more broadband second

approach suffers from a lower PAE of 20% achiev-

ing 50W output power.

Different manufactured amplifiers have shown

only a small variation in their performance data.

The excellent results obtained indicate that a hy-

brid two stage design approach has significant ad-

vantages towards system design while achieving a

state-of-the-art efficiency.

In addition, a design procedure of a hybrid Ku-

band BUC has been presented. Starting with a de-

sign description, all components of a BUC, namely

the LO generation, up-conversion, filtering as well

as the amplifier and power amplifiers were de-

scribed. All parts were evaluated individually

as well as in the system. CW measurements of

the BUC show an output power up to 39dBm

with η=15%. Furthermore, higher order mod-

ulation schemes 32APSK(DVB-S2), 64APSK(DVB-

S2X) were tested and denote 20W and 16W output

power respectively with a PAE of ≥21% by using

a larger PA.

The BUC has been equipped with an RF-predistortion

capable of improving the ACLR for QPSK mod-

ulated measurements within 10dBc. Real time

centre frequency and signal bandwidth detection

has been realised without access to the baseband

signal, in the IF-range. An IF predistortion de-

livered good results for decreasing the spectral

regrowth as well as minimizing the EVM of mod-

ulated SatCom signals. The technique has been

easily implemented directly in the BUC and ex-

tends the throughput of the basestation as well as

its efficiency.

Particularly very small aperture terminals (VSATs)

in a mesh topology can benefit from an enhanced

output linearity with equal output power. Further-

more, this technique opens up new possibilities for

transistor technologies with strong non-linearities

or long term memory effects like GaN-HEMTs in

higher frequency ranges.

The developed BUC exceeds the commercially

available BUCs regarding their system efficiency

with up to 5% for the low power (20 W) and up to

7% for the high power (40W) version considering

Chapter 6. Conclusion

the 3dB back-off operation. Furthermore, the de-

veloped BUCs are extremely thin and lightweight

compared to other products, which eases the point-

ing of a VSAT.

Finally a planar VSAT has been equipped with the

BUC and tested in a satellite link to a Hub. The link

has shown sufficient C/N level and up to 1Mbit/s

in the return link. The small dimension of the

BUC as well as great performance data indicate

the high perspectives of GaN for future SatCom

applications.

The results of this thesis were summed up in a

workshop for EUMW2017 [Maa+17d]. The de-

rived technologies for matching low impedance

devices can be used for the development of MMICs

as well. SatCom related developments for the Ka-

band can be carried out, with the use of 140nm

GaN-HEMT technologies in future work. Ka-band

terminals are particularly suitable for implement-

ing a linearisation technique in the IF like de-

scribed in this work, due to the equal IF like in

the Ku-band.

A Appendix

A.1 S-Parameter

Within the Microwave theory the behaviour of

linear elements can be explained by the use of S-

Parameters. One term of a port linear circuit can be

defined by a complex voltage Viand a complex cur-

rent Iiwhere (i=1,2). These voltages and currents

can be divided into forward (Vfi) and reflected

(Vri) propagation with the reference Impedance

ZL.

V1=Vf1+Vr1;I1=Vf1

ZL−Vr1

(A.1)

V2=Vf2+Vr2;I2=Vf2

ZL−Vr2

(A.2)

So the voltages and currents can be changed to

wave quantities that are either propagating (ai) or

reflected (bi).

ai=Vfi

√Re{ZLi}=Vi+ZLi ·Ii

2√Re{ZLi}(A.3)

bi=Vri

√Re{ZLi}=Vi−ZLi ·Ii

2√Re{ZLi}(A.4)

Vi=ZLi ·ai+ZLi ·bi

√Re{ZLi}(A.5)

Ii=ai−bi

√Re{ZLi}(A.6)

The unit of this wave quantities is √Wbased on

the definition of the incoming (Pwa) and outgoing

effective power (Pwb):

Pwa =1

2a a∗=VfV∗

2ZL

(A.7)

Pwb =1

2b b∗=VrV∗

2ZL

(A.8)

These incoming aiand outgoing quantities bican

be put in relation via the scattering matrix and lin-

ear equations:

b1=S11a1+S12a2(A.9)

b2=S21a1+S22a2(A.10)

(b1

b2)=(S11 S12

S21 S22)(a1

a2)(A.11)

In addition the wave quantities can be defined in

the T-matrix:

(a1

b1)=(T11 T12

T21 T22)(b2

a2)(A.12)

Among a two port these S-Parameter can be used

as well for n-ports.

Öb1

...

bnè=ÖS11 ... S1n

...

Sn1SnnèÖa1

...

anè(A.13)

The scattering parameters Sij that can be calcu-

lated based on the derivatives of the wave quanti-

ties are defined as follows for a two port:

S11 =b1

a1a2=0

input reflection (A.14)

S22 =b2

a2a1=0

output reflection (A.15)

S12 =b1

a2a1=0

feedback transm. (A.16)

S21 =b2

a1a2=0

forward transm. (A.17)

They can also be calculated based on the Impe-

dance quantities:

Sii =ZEi −ZLi

ZEi +ZLi

(A.18)

ZEi =ZLi

1 + Sii

1−Sii

(A.19)

Sji =2Vj

V0iZLi

ZLj

(A.20)

By the use of these S-Parameters complex systems

can be easily analysed.

Furthermore, based on this S-Parameters common

Appendix A. Appendix

factors of microwave engineering are defined. Be-

ginning with the definition of stability of an am-

plifier. Rollet defined a k-factor which needs to be

positive ≥1over the entire frequency range:

k=1−|S11|2−|S22|2+|S11 ·S22 −S12 ·S21|2

2·|S12 ·S21|(A.21)

In addition stability circles are used to determine

weather the variation of source- and load-impedances

(|det S|) is located outside the smith-chart.

D=|det S|=|S11 ·S22 −S21 ·S12|<1(A.22)

The available gain (GMAX or MAG) of an amplifier

can be analysed for a two port circuit independent

to its source- and load-impedances:

GMAX =|S21|

|S12|·(k−√k2−1) fork ≥1(A.23)

The available gain is undefined when kis less than

one because then √k2−1gets imaginary. There-

fore, for frequencies lower than k= 1 the maxi-

mum stable gain (MSG) is the limit of amplifica-

tion:

MSG =mag|S21|

mag|S12|(A.24)

Stability can be furthermore proven by the factor

B1which should be greater than zero.

B1 = 1 + |S11|2−|S22|2−|det S|2(A.25)

A.2 Transmission line Theory

Here, the MS definitions are cited by [Bah03] us-

ing the same nomenclature. Where possible, the

complicated functions are eased through the use

of symbolic functions. The formulas are given here

for an easier recalculation of the well known trans-

mission line theory. Wheeler defined the wave im-

pedance of a microstrip to be [Whe78]:

ZT L =Z0

2π√2(1 + εr)ln(1 + 4h

ωeff ·TLx)with

(A.26)

TLx =14 + 8

εr

ωeff

+(14 + 8

εr

ωeff

)2+π21 + 1

εr

(A.27)

with ωeff being the width of the microstrip taking

account of the thickness of the metallisation.

ωeff =ω+t1 + 1

εr

2πln Ö4e

√(t

h)2+ ( 1

t+11

)2è

(A.28)

η= 120 ·π(A.29)

if W

h≤π

We,h =W

h+5t(log(4π W

t)+ 1)

4π h (A.30)

else if π

2≤W

We,h =W

h+5t(log(2h

t)+ 1)

4π h (A.31)

if W

h≤1

FW,h =ÅW

h−1ãÅ41 W

1000 h−41

1000ã+1

»12 h

W+ 1

(A.32)

εre =εr

2−C+FW,h Åεr

2−1

2ã+1

2(A.33)

Z0=ηlogÄWe,h

4+8

We,h ä

2π…εr

2−C+

εr

2−1

√12 h

W+1 +1

(A.34)

else if 1<W

FW,h =1

»12 h

W+ 1 (A.35)

εr,eff =εr

2−C+

εr

2−1

»12 h

W+ 1

2(A.36)

Z0=η

√εr,eff ÅWe,h +667 log

(We,h+361

250 )

1000 +1393

1000 ã

(A.37)

Appendix A. Appendix

In addition, we can take the skin effect into ac-

count:

skin =»ρc

f µ0

√π(A.38)

fk,T M0=

c0 arctan(εr»εr,eff −1

εr−εre)

2π h √εr−εr,eff

(A.39)

f50 =−fk,TM0

W(83

250 εr

173

100

−3

h−3

(A.40)

if W

h≤0.7

mc = 1 −

7Ç23 e

−

20 f50

100 −3

20 å

5(W

h+ 1)(A.41)

else mc = 1

m0=1

»W

h+ 1

25 (»W

h+ 1)3+ 1 (A.42)

m= m0·mc (A.43)

εr,eff,f =εr−εr−εr,eff

Äf

f50 äm0 mc + 1

(A.44)

Z0,f =η»εr,eff

εr,eff,f (εr,eff,f −1)

√εr,eff (εr,eff −1) Ξ (A.45)

Ξ = ÇWe,h +667 log(We,h +361

250 )

1000 +1393

1000å

(A.46)

The microstrip losses can be calculated dividing

into conductive and dielectric losses:

u=W

hg=s

hv=ge−g+u(g2+ 20)

g2+ 10

(A.47)

ae=10 logÄ1000 v3

5929741 + 1ä

187 +

logÅv4+v2

2704

v4+54

125 ã

49 + 1

(A.48)

be=

141 (εr−9

εr+3 )53

1000

250 (A.49)

εr,eff,e =εr

εr

2−1

(10

v+ 1)ae be +1

2(A.50)

a0=Äe−179 u

1000 −1ä(7287 εr

2e5−7287 εr,eff,f

1e5+7287

2e5)

(A.51)

b0=747 εr

1000 (εr+3

20 )(A.52)

c0= b0−e−207 u

500 Åb0−207

1000ã(A.53)

d0=347 e−281 u

500

500 +593

1000 (A.54)

εr,eff,o =εr,eff,f + e−co gd0(a0+εr

2−εr,eff,f +1

(A.55)

Considering coupled MS lines additional parame-

ters need to be defined:

Q1=1739 u97

500

2000 (A.56)

Q2=7519 g

10000 +189 g231

100

1000 + 1 (A.57)

Q3=

logÅg10

9.76e6g10

2.015e12+1 ã

241 +1

Ä5.48e9

15625 g6+83

5ä387

1000

+79

400

(A.58)

Q4=−2 Q1

Q2Äe−g−2

uQ3−uQ3e−gä(A.59)

Z0,e =−

Z0f»εr,eff,f

εr,eff,e

Q4√εr,eff,f η

377 √εr,eff (We,h+667 log

(We,h+361

250 )

1000 +1393

1000 )−1

(A.60)

Q5=

57 logÑ319

500 (g+517 g

243

100

1000 )+ 1é

50 +897

500 (A.61)

Appendix A. Appendix

Q6=

10 logÅg10

9.7e6g10

4.20e15+1 ã

2813 +

10 logÅ299 g577

500

500 + 1ã

51 +461

2000

(A.62)

Q7=190 g2+ 10

823 g3

10 + 1 (A.63)

Q8= e−19 log(g)

20 −3.2e6g5

243 −13

2(A.64)

Q9= log(Q7)ÅQ8+2

33ã(A.65)

Q10 =Q2Q4−Q5e

Q6log(u)

ulog(Q7)(Q8+2

33 )

(A.66)

The nominal characteristic line impedance can be

defined with:

Z0,o =−

Z0f»εr,eff,f

εr,eff,o

Q10√εr,eff,f η

377 √εr,eff (We,h+667 log

(We,h+361

250 )

1000 +1393

1000 )−1

(A.67)

resulting in the even mode and odd mode line im-

pedance:

Z0,e =Z0…εr,eff

εr,eff,e

(1 −(Z0/377)(εr,eff )0.5Q4)

(A.68)

Z0,o =Z0…εr,eff

εr,eff,o

(1 −(Z0/377)(εr,eff )0.5Q10)

(A.69)

was extended to nparallel lines by the assumption

that the effect of the coupling decreases with an in-

crease of nby a simple quadratic polynom:

nfit =−8.919e−4n2+ 0.804 n+ 0.2174 (A.70)

to result in:

Z0,en =Z0,e nfit

−1Z0,on =Z0,o nfit

−1

(A.71)

A.3 Amplifier Nomenclature

The dc power consumption of an amplifier is the

sum of the drain and gate power:

Pdc ={VGS ·Igate}+{VDS ·Idrain}(A.72)

The input as well as output power of an amplifier

depends on the definition of the reference-plane,

the frequency as well as the reference impedance.

For an amplifier the typical reference plane is the

input and output connector

Pin =Pin(f) = 1

2Re{Vin ·I∗

in}(A.73)

Pout =Pout(f) = 1

2Re{Vout ·I∗

out}(A.74)

The gain of the amplifier is simply:

gain =Pout(f)

Pin(f)(A.75)

To calculate the efficiency only the output power is

set in relation to the dc power consumption:

η=Pout(f)

Pdc ·100 % (A.76)

By considering the gain instead of only the output

power the power added efficiency is defined:

PAE =Pout(f)−Pin(f)

Pdc ·100 % = η·(1 −1

gain)

(A.77)

The difference between output power and dc

power consumption represents the dissipated power,

while the input power Pin can often be neglected

for high gain amplifiers:

Pdiss =Pdc −Pout (A.78)

Given a two-stage amplifier the total gain can be

derived into the gain of the first stage (gain Q1)

and the second stage (gain Q2). The same can be

done for their drain efficiencies.

gain Q1 = PQ1

η Q1 = P1

Pdc,Q1·100 % (A.79)

gain Q2 = Pout

PQ1

η Q2 = Pout

Pdc,Q2·100 % (A.80)

Appendix A. Appendix

As a result, the total drain efficiency is:

100 % =Pout

Pdc,Q1+Pdc,Q2

=Pout

PQ1

Pdc,Q1+Pout

Pdc,Q2

gain Q2·η Q1+1

η Q2

=η Q1·η Q2

η Q1 + η Q2

gain Q2

(A.81)

In consequence, the PAE is:

PAE =G Q2−1

G Q1

(G Q2

η Q2) + ( 1

η Q1)(A.82)

An increase in η Q1affects G Q1therefore, it is

more convenient to analyse the PAE by defining a

reduction of PAE

∆PAE =PAEQ2−PAE (A.83)

due to the addition of the driver stage PAEQ1=

(PAEQ2−∆PAE)(G Q1−1) ·PAEQ2

[∆PAE ·(G Q2−1) + P AEQ2]·G Q1−PAEQ2

(A.84)

For modulated signals the PAE needs to be calcu-

lated based on the average power level as well as

the average gain:

PAEMOD =Pout,avg −Pin,avg

Pdc ·100 %

=η·(1 −1

G)(A.85)

A.4 Simulation Techniques

Circuit Simulation

Nowadays, circuit simulation is widely used for

hardware design within low- and of-course high-

frequency applications. Microwave circuit simu-

lation solves widely known techniques in its de-

sign environment. The CAE simulation tools ADS1

or MWO2are the most common candidates in the

market.

1Advanced Design System (Keysight)

2Microwave Office (AWR)

The knowledge of the implemented Algorithm is

nevertheless necessary to get a basic understand-

ing. Especially during system faults a deeper un-

derstanding eases the debugging.

DC Simulation

A DC-simulation is carried out before any fre-

quency analysis of a circuit within the CAE tools.

The DC-simulation mainly solves Kirchhoff’s equa-

tion for all notes of the circuit. Initially, all sources

were set to an equal constant value (dv

dt ,di

dt = 0).

A capacitor represent an open, while an inductor

is represented via a short. In conclusion the solu-

tion of this analysis depends on biasing within this

equilibrium analysis and represents one possible so-

lution. This solution does not necessarily needs to

be the only possible solution.

Nearly all CAE tools rely on a SPICE method

which relies on the use of a netlist to connect the

components and the nodes. This Nodal Admit-

tance Matrix is solved iteratively. Afterwards, a

linearisation technique takes place that flattens all

the step depended dc solutions by the usage of a

Taylor series expansion [Kun95].

AC Simulation

Non constant signals are normally analysed through

the use of an AC–simulation. Most analysis regard-

ing AC–, XF–, or S-Parameter–Analysis rely on the

so-called Phasor-Analysis. The small-signal reac-

tion of a circuit is analysed for a certain number

of frequencies. Amplitude as well as the phase re-

sponse of this circuit are defined for its fundamen-

tal wave. The circuit’s response always relies on

the implementation of only one frequency, which

is why no transient behaviour can be covered.

Transient Simulation

For circuits with non converging operation points

the Transient-Analysis takes place. This time-

domain analysis solves the partial differential

Appendix A. Appendix

equations of the circuit stepwise of numeric ap-

proximations. The analysis of highly non-linear

circuits, therefore leads to a high settling time

which leads to a high simulation time. To com-

promise for the simulation time, some pseudo

transient-analysis tools limits all used capacitors

to 1F, reducing the amount of various differential

equations and in conclusion achieving the settling

time faster.

Harmonic–Balance Simulation

For analysing non-linear high-frequency circuits,

almost exclusively Harmonic–Balance (HB) simu-

lations were used. The technique is particularly

good for the analysis of large-signal simulations.

All components of the circuit were analysed in-

dividually in the frequency-domain. The compo-

nents are therefore per definition stable and their

settling time is achieved. The whole circuit is af-

terwards divided into parts that can easily be ex-

plained linearly and those who parts which need

a non-linear representation. The linear part of the

circuit can be solved by using the time-domain

techniques to evaluate the operation points.

Subsequently, different solving techniques were

used for various large-signal input signals. A sin-

gle, multi-tone or a pulsed-tone excitation needs

different large-signal HB solving algorithms. For

example, a Volterra-Series algorithm can be used

to solve weak non-linear systems. For components

with a high quality factor the HB analysis can find

a solution faster than any other analysis that needs

to rely on a steady state situation.

In comparison to the Transient simulation the HB

simulation is not generalised for various signal

types.

Electro–Magnetic Simulation

Very simple geometrical structures can be explained

analytically. Yet even for a simple capacitor that

mainly relies on two parallel plates, the fringing at

the edges is difficult to approximate analytically.

Therefore numerical solutions of the Maxwell

Equations, or a special adaption of its, are used

to solve these structures.

Maxwell described solutions for macroscopic struc-

tures by the definition of an electro (

E) as well as a

magnetic ( 

H) field. By using differential equations

they can be summed up to:

rot 

E=−∂

∂t 

B(A.86)

rot 

H=∂

∂t 

D+

J(A.87)

div 

D=ϱ(A.88)

div 

B= 0 (A.89)

I∂A



E·ds =−d

dt ∫A



B·d

A(A.90)

I∂A



H·ds =∫A

(∂

∂t +

J)·d

A(A.91)

I∂V



D·d

A=∫V

ϱ dV (A.92)

I∂V



B·d

A= 0 (A.93)

To build a bridge between the electric field 

Eand

its potential 

Das well as between the magnetic

field 

Hand the current density 

Jthe material equa-

tions were stated:



D=ε

E=ε0εr

E(A.94)



B=µ

H=µ0µr

H(A.95)



J=κ

E+

Je(A.96)

For solving geometrical structures with these equa-

tions they need to be discretisized within substruc-

tures. For each substructure the EM fields can be

locally solved. The substructures are filled by the

definitions according to the material equation, be-

ing either conductive or isolators. By the definition

of special boundary conditions 3all the substruc-

tures sum up to the previously defined geometrical

structure.

The time-domain approximation can be trans-

formed into the frequency-domain. Each spectral

represent is defined by an amplitude and phasor.

3For an equal electrical potential on the Dirichlet- bound-

ary, an equal magnetical potential is called Neumann-boundary

while neither of both represent an Open-boundary

Appendix A. Appendix

100

Finite Difference Method (FDM)

Finite difference methods use numerical techniques

to approximate the differential equations (E.g.

Maxwell) with difference equations. FDM can

therefore be stated as an discretization method.

Eq.A.97 states a discretization with f′(xi)being

the numerical approximation of f. The sum of all

derivatives form a Taylor series which is the total

approximation of the differential equation.

xi-1 xi+1

xix

f′(xi) = f(xi+ ∆) −f(xi−∆)

2∆ + Θ(∆)2(A.97)

The number of used steps (i) or the distance in be-

tween determines the accuracy of the approxima-

tion. Yee defined a finite differences method for

the time-domain (FDTD) which is especially use-

ful for its application in the microwave engineer-

ing. The differnziation takes place, for the spatial

orientation as well as for the time derivative. Both

derivatives build a grid along their discretization

step width. By definition both grids are allocated

to each other, which lowers the access time. One

drawback of this technique is that the whole struc-

ture needs to be solved for each excitation port sep-

arately. By using a high amount of excitation ports

the amount of time increases.

Finite Integration Method (FIT)

The finite integration method (FIT) is a relative of

FDTD. It is especially designed for the use with

Maxwell’s Equations and it is possible to achieve

near lossless discretization. The original partial dif-

ferential equations can be interpreted within two

differently allocated grids of the FIT. Within these

grid related Maxwell equations (Eq. A.98-A.105)

the electrical ıenand magnetical ı

hnboundary po-

tentials are defined exactly on the gridline. The

electrical- and Ù

dnmagnetical-flux Ù

bnenforce the

surface which is surrounded by this discretisized

gridlines. Muliple Source- (S) and Curl-Matrix (C)

span the grid. This primary grid (Matrix S, C) re-

mains perpendicular to a secondary grid (Matrix

S, ˜

C) which eases the operations in between both

Matrixes (C=˜

CT).

I∂A



E·ds =−d

dt ∫A



B·d

A(A.98)

⇒CÛe=−d

dtÛÛb(A.99)

I∂A



H·ds =∫A

(∂

∂t +

J)·d

A(A.100)

⇒˜

CÛh=d

dt Ù

d+Ûj(A.101)

I∂V



D·d

A=∫V

ϱ dV (A.102)

⇒˜

SÙ

d=q(A.103)

I∂V



B·d

A= 0 (A.104)

⇒SÛÛb= 0 (A.105)

The only approximation of this anaylsis relies in

the approximation of the material definitions. For

example, the permmitivity and conductivity is av-

eraged along the surface of the grid. While the per-

meability is approximated along the gridlines.

d=MεÛe(A.106)

ÛÛb=MµÛh(A.107)

ÛÛj=MκÛe(A.108)

The FIT method is suitable for use within the fre-

quency, as well as for transient fields in the time-

domain. It is one of the most stable and fastest

real 3-D EM-Solver commercially implemented in

CST4.

Finite Element Method (FEM)

The finite element method discretises the geomet-

rical object into differently sized frameworks. The

different sizes of the framework can be more easily

solved on its own as this would be the case if all

frameworks represent the same size. The bound-

ary between all frameworks is constant as already

described for the FDTD boundary conditions. This

4Computer Simulation Technology (Dassault Systemes 3DS)

Appendix A. Appendix

101

technique is applied in a real 3-D EM-Solver com-

mercially implemented into HFSS5or EM-Pro 6.

Moment Method (MoM)

The method of moments only discretisizes the con-

ductive parts of the geometrical structure. The

planar dielectricel part is seperately approximated

for one unit-cell (Substrate Matrix). One additional

advantage of this technique is, that only one Matrix

is defined for the whole structure. Therefore, an

increased number of excitation ports does not in-

crease the calculation time. The solving algorithm

relies on the Green’s equation. It is one of the

commonly used techniques to solve planar (2.5-D)

structures of printed circuit board application.

A.5 Measurement Uncertainty

Small-Signal Uncertainties

The measurement uncertainty of a probed test

circuit is going to be visualized in Fig. A.1. The

GSOLT calibration setup of Fig. 2.14 is used with a

HP8510cTM, two 1000µm Z-ProbesTMand a 5 mm

long RO4003c MS line. Fig.A.1(a) shows that the

whole measurement setup has an un-calibrated IL

of up to 8dB (25GHz), while the un-calibrated RL

is ≈25dB due to the good matching of the VNA

and the high residual losses caused by the IL of the

cable and the probes.

Furthermore, the calibrated version of this mea-

surement is displayed located at the reference-

plane (GSOLT On-Wafer Cal.) through using a

GSOLT Cal-Kit (Cascade CSR-15TM). The uncer-

tainty of this measurement is caused by differ-

ent types of errors. Taking advantage of the de-

tailed uncertainty analysis of the METAS VNA-

Tool different errors can be analysed separately

[Wol+12]. By using a VNA with an excellent Drift

the magnitude error is rather low (0.05dB) for the

transmission-case increasing towards higher fre-

quencies Fig.A.1(c). The VNA Noise (-90dBm/Hz

5High Frequency Structure Simulator (Ansys)

6EM-Pro by ADS (Keysight)

0 5 10 15 20 25 30 35

−10

−8

−6

−4

−2

Frequency (GHz)

S21 (dB)

Cal

unCal

(a)

0 5 10 15 20 25 30 35

−40

−30

−20

−10

Frequency (GHz)

S11 (dB)

Cal

unCal

(b)

0 10 20 30

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

Frequency (GHz)

S21 Uncertainty Mag (dB)

Cable

Connector

VNA Drift

VNA Noise

VNA Switch−Term

Total

(c)

0 10 20 30

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency (GHz)

S11 Uncertainty Mag (dB)

(d)

0 10 20 30

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Frequency (GHz)

S21 Uncertainty Phase (°)

(e)

0 10 20 30

0.5

1.5

2.5

3.5

4.5

Frequency (GHz)

S11 Uncertainty Phase (°)

(f)

FIGURE A.1: Uncertainty analysis of probed TL (a) S21

(b) S11 (c) S21 unc. (d) S11 unc. (e) S21 phase unc. (f) S11

phase unc.

Appendix A. Appendix

102

at 30GHz) causes the largest uncertainty of up

to (0.1dB), while the isolation and directivity of

the switch-terms the lowest. A high connectivity

repeatability was assumed causing only a low un-

certainty. In addition, possible cable movement

can be approximated by the phase and magnitude

variances described by the manufacturer. The to-

tal magnitude uncertainty can be explained with

0.15dB for the magnitude (at 30GHz) in the trans-

mission path. While the reflection uncertainty

sums up to 0.4dB for the magnitude (at 30GHz).

The total phase uncertainty sums up to 1.5◦for the

transmission and up to 3◦for the reflection.

This analysis lacks of the knowledge related to

the calibration standard repeatability. Moreover,

the low RL of the Z-ProbeTM(≤20 dB at 30 GHz)

was only taken into account for the calibration.

Its residual errors were not stated separately as a

phase or magnitude uncertainty while it will prob-

ably causes the highest error of all. Cascade lim-

its the upper operation frequency of their probes

in relation to the pitch between the fingers. For

GSG-Probes the upper operation frequency can

be calculated regarding the pitch and the error as

shown in Tab.A.1. For the use of 500 µm pitch

probes at 14GHz a measurement error of 2% can

be assumed.

TABLE A.1: Measurement uncertainty of 500 and

1000µm pitch GSG Z-ProbesTM

error (%) GSG 500 GSG 1000

max. f (GHz) 1 9.5 4.8

max. f (GHz) 3 19.1 9.5

max. f (GHz) 5 38.1 19.1

Large-Signal Uncertainties

The Large-Signal related uncertainties of the mea-

surement setup given in Fig. 2.15 can be visualized

by its statistical distribution. This way, 10000 sam-

ples were generated with varying phasors chang-

ing the Γin and Γout for a fixed RL of 14 and 20dB.

The statistical distribution is given in Fig.A.2. For

the input-side a Kurtosis of 1.91 was obtained

while the output-side shows a Kurtosis of 2.95

indicating a nearly normal distribution. It can be

obtained that introducing a higher mismatch at the

DUT related plane significantly increases the mea-

surement uncertainty. Taking the RL of 14 dB at the

input coupler into consideration the measurement

uncertainty increases up to Pin, unc =0.14 dB as a

mean value. For the output coupler the Pout, unc

arises up to 0.31dB mean.

−0.1 −0.05 0 0.05 0.1

1000

2000

3000

4000

5000

6000

uncertainties (dB)

normalized samples

30 dB Coupling, 20 dB RL

(a) Pin, unc

−0.4 −0.2 0 0.2 0.4

1000

2000

3000

4000

5000

6000

uncertainties (dB)

normalized samples

30 dB Coupling, 14 dB RL

(b) Pin, unc

−0.2 −0.1 0 0.1 0.2

1000

2000

3000

4000

5000

6000

7000

uncertainties (dB)

normalized samples

40 dB Coupling, 20 dB RL

−1−0.5 0 0.5

1000

2000

3000

4000

5000

6000

7000

8000

uncertainties (dB)

normalized samples

40 dB Coupling, 14 dB RL

(d) Pout, unc

FIGURE A.2: Statistical distribution for a RL=20dB and

a RL=14dB for (a),(b) input (c),(d) output coupler.

A.6 Link Nomenclature

Link calculation

The transmit power directed from a station to-

wards the satellite is defined as the Effective Isotropic

Radiated Power (EIRP). It is calculated based on

the output power of the BUC (Pout) and the effec-

tive TX antenna gain GA,TX. Losses in between the

BUC and the antenna (ILcable) degrade the EIRP

which can be defined:

EIRPup =Pout −ILcable +GA,TX.(A.109)

Appendix A. Appendix

103

Additional mis-point losses (Attmis = 0.3 to 1dB)

degrade the transmitted power. Rain losses (Attrain =

0.3 to 6dB) occur depending on the global position

of the earth-station. ITU-R rain fade calculations

can be done, which can be scaled depending on

the overall year availability (like 99.5%). Attatm de-

picts the atmospheric absorption. These physical

losses can be summed up to (Attphys):

Attphys =Attmis +Attrain +Attatm (A.110)

The main losses of a satellite link are related to the

free-space attenuation (Lspace) which depends on

the used frequency (f) and the distance to ground

(d≈35786km):

Lspace =Å4π·d·f

c0ã2

(A.111)

with c0=299.710km/s. The receiving carrier power

at the satellite can be simply calculated by:

C=EIRPup −Attphys −Lspace +GA,RX (A.112)

To determine the noise within a system the equiv-

alent noise power (N) can be calculated based on

the used bandwidth (B) the temperature of the re-

ceiving system (TRX ) and the Boltzmann constant

(k=1.38e−23 W/Hz K).

N=k·TRX ·B(A.113)

The receiving system noise temperature (TRX ) is

given by the sum of the antenna noise temperature

(TA,RX ) and the effective noise temperature of the

receiver (TR).

TRX =TA,RX +TR(A.114)

Considering the losses of a feeder (ILfeed) and a

LNA (TLNA) the equation has to be extended to:

TRX =TA,RX

ILfeed

+ILfeed −1

ILfeed ·T0+TLNA (A.115)

for the ambient temperature T0=290K. As a figure

of merit the sensitivity of the receiver can be de-

picted by the term GA,RX

TRX which is G/T. Thus, the

uplink carrier power can be linear set into relation

to the satellite receiving noise by:

C/Nup(th) = EIRPdown ·1

Attphys ·1

Lspace ·GA,RX

(A.116)

This C/N is only related to a thermal noise and can

be therefore named C/N (th). The calculation can

also be applied for the downlink:

C/Ndown(th) = EIRPdown ·1

Lspace ·1

Attphys ·GA,RX

(A.117)

The same budget can be calculated for the down-

link pointing from the satellite to the receiving

earth-station. Important is the knowledge, that

both C/N of the uplink (C/Nup) as well as the

downlink (C/Ndown) needs to be taken into ac-

count to determine the total C/N. While normally,

the uplink C/Nup is significantly higher than the

downlink C/Ndown and often negligible.

totalC/N(th) = ((C/Nup)−1+ (C/Ndown)−1)−1

(A.118)

Intermodulation distortion can occur in between

satellites based on the sum of all side-lobes di-

rected from the earth to the satellite. The up-

link interference Iis the sum of all interfering

sources (I=∑Ii). If the interfering uplinks are

known they can be calculated based on the their

orbital separation. Otherwise an adjacent satel-

lite interference value can be assumed, consider-

ing the orbital location of the satellite pointing to

(Csat/ASI0=≈132 dB/Hz). This intermodulation

distortions have the character of an additive ther-

mal noise - which is why it can be easily added to

the previous C/N calculations:

totalC/(N+I) =totalC/N(th)∥C/I)−1(A.119)

For analysing the budget based on digital systems

we can define the Energy per modulated symbol

(Es) with the code rate (RcFEC) and the modula-

tion rate (Rm). The Energy per bit (Eb) can be cal-

culated for BPSK with M=2 or QPSK:M=4... :

Es=Rm·Rc·Ebwith Rm=log2·M(A.120)

Appendix A. Appendix

104

With the knowledge of the bit rate (br) and the

bandwidth (B):

C/N =Eb/N0·br

B(A.121)

the C/N can be converted into the measure of sig-

nal to noise ratio for digital communication sys-

tems (Eb/N0). The Energy per bit (Eb) is related to

the spectral noise density (N0) defined as Eb/N0.

By the usage of forward error correction the ideal

Es/N0can be taken as the reference for a C/N dis-

tance with the knowledge of the bandwidth (B)

and the datarate (dr).

Es/N0=C/N ·B

dr (A.122)

The definition of Eb/N0can be extended by addi-

tional intermodulation, as already shown for the

C/N, by Eb/(N0+I0), or Es/(N0+I0) for a certain

modulation.

HUB to VSAT Link-Budget

A∅4.6m dish (ND SatCom) provides a 5MSym/s

QPSK uplink (DVB-S1) as HUB station. The TX an-

tenna gain is 55dBi which is powered by a BUC de-

livering Pout =10W resulting in up to 65dBW EIRP.

The Link-Budget is described in Tab.A.2. The RTL

fom Easystar to the HUB is calculated based on a

1.2MSym/s QPSK uplinkas follows in Tab. A.3.

Appendix A. Appendix

105

TABLE A.2: (a) Uplink calculation within the FWL; (b) Downlink calculation within the FWL; (c) resulting total link

margin within the FWL (Munich to Eutelsat 33E; 13.939087GHz (H) up; 11.13537 GHz (V) down; 5 MSym/s; QPSK;

FEC 5/6; α=0.35; Pout =10W; 99.5% availability ITU-R)

(a)

uplink clear sky rain up

uplink EIRP 63.97 63.97 dBW

transponder IBO 7.85 7.85 dB

IBO/carrier 17.41 19.09 dB

antenna mispoint 0.3 0.3 dB

free space loss 207.15 207.15 dB

total attenuation 0.17 1.82 dB

C/N (th) 22.87 21.23 dB

C/(N+I) 22.84 21.2 dB

Eb/(N0+I0)20.98 19.34 dB

(b)

downlink clear sky rain down

sat EIRP 50.5 50.5 dBW

transponder OBO 5.18 5.18 dB

OBO/carrier 14.82 14.82 dB

antenna mispoint 0.3 0.3 dB

free space loss 205.2 205.2 dB

total attenuation 0.14 1.08 dB

total system noise 122.6 171.6 K

G/T 17.6 16.15 dB/K

C/N (th) 9.56 7.16 dB

Eb/(N0+I0)7.62 5.25 dB

(c)

totals per carrier (end to end) clear sky rain up rain down dual fade

C/N (th) 9.36 7.72 7.04 5.4 dB

C/(N+I) = [Es/(N0+I0)]9.29 7.67 7 5.37 dB

system margin 1 1 1 1 dB

net Es/(N0+I0)8.29 6.67 6 4.37 dB

required Es/(N0+I0)(for QPSK) 5.18 5.18 5.18 5.18 dB

excess margin 3.11 1.49 0.82 -0.81 dB

TABLE A.3: (a) Uplink calculation within the RTL; (b) Downlink calculation within the RTL; (c) resulting total link

margin within the RTL (Berlin to AM44; 13.93537 GHz (H) up; 11.113087 GHz (V) down; 1.2MSym/s; QPSK; FEC

2/3; α=0.35; Pout =10W; 99.5% availability ITU-R)

(a)

uplink clear sky rain up

uplink EIRP 48 48 dBW

transponder IBO 7.85 7.85 dB

IBO/carrier 33.18 34.83 dB

antenna mispoint 0.3 0.3 dB

free space loss 207.23 207.23 dB

total attenuation 0.18 1.83 dB

C/N (th) 13.38 11.73 dB

C/(N+I) 13.36 11.71 dB

Eb/(N0+I0)13.71 12.06 dB

(b)

downlink clear sky rain down

sat EIRP 50.5 50.5 dBW

transponder OBO 5.18 5.18 dB

OBO/carrier 30.51 30.51 dB

antenna mispoint 0.3 0.3 dB

free space loss 205.18 205.18 dB

total attenuation 0.14 1.06 dB

total system noise 200.29 245.76 K

G/T 28.6 27.7 dB/K

C/N (th) 10.78 8.96 dB

Eb/(N0+I0)11.03 9.41 dB

(c)

totals per carrier (end to end) clear sky rain up rain down dual fade

C/N (th) 8.88 7.23 7.62 5.97 dB

C/(N+I) = [Es/(N0+I0)] 8.8 7.17 7.57 5.93 dB

system margin 1 1 1 1 dB

net Es/(N0+I0)7.8 6.17 6.57 4.93 dB

required Es/(N0+I0)(for QPSK) 3.1 3.1 3.1 3.1 dB

excess margin 4.7 3.07 3.47 1.83 dB

106

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Own Publications

[Maa+13] Maassen, D., C. Schreiber, S. Preis, and G. Boeck (2013). “Performance Optimization of

GaN-HEMT Power Amplifiers using a pre-matched Load-Pull Setup”. In: 2013 Workshop on

Compound Semiconductor Devices and Integrated Circuits hels in Europe (WOCSDICE), pp. 80–

83.

[Maa+15a] Maassen, D., F. Rautschke, and G. Boeck (2015a). “IF predistortion in the block upconver-

sion path for modern satcom applications in the Ku-Band”. In: 2015 European Microwave

Conference (EuMC), pp. 80–83. DOI:10.1109/EuMC.2015.7345704.

[Maa+16a] Maassen, D., F. Rautschke, T. Huellen, and G. Boeck (2016a). “A 12-W GaN-HEMT power

amplifier for Ku-band satellite communication,inc”. In: 2016 21st International Conference

on Microwave, Radar and Wireless Communications (MIKON).DOI:10.1109/MIKON.2016.

7492070.

[Maa+16b] Maassen, D., L. Schenk, M. Muessener, P. Muehlbacher, U. Dalisda, and G. Boeck (2016b).

“An 60 W average power wideband amplifier with envelope tracking for DVB-T applica-

tions”. In: 2016 46th European Microwave Conference (EuMC), pp. 823–826. DOI:10.1109/

EuMC.2016.7824470.

[Maa+16c] Maassen, D., F. Rautschke, and G. Boeck (2016c). “Design and comparison of various cou-

pled line Tx-filters for a Ku-band block upconverter”. In: 2016 German Microwave Conference

(GeMiC), pp. 225–228. DOI:10.1109/GEMIC.2016.7461596.

[Maa+17a] Maassen, D., F. Rautschke, F. Ohnimus, L. Schenk, U. Dalisda, and G. Boeck (2017a). “70W

GaN-HEMT Ku-Band Power Amplifier in MIC Technology”. In: IEEE Transactions on Mi-

crowave Theory and Techniques 65.4, pp. 1272–1283. ISSN: 0018-9480. DOI:10.1109/TMTT.

2016.2636151.

[Maa+17c] Maassen, D., F. Rautschke, Soenke Vehring, S. Barbin, and G. Boeck (2017c). “Ku-Band

Hybrid GaN Block Upconverter for Very Small Aperture Terminals”. In: 2017 SBMO/IEEE

MTT-S International Microwave and Optoelectronics Conference (IMOC).

[Maa+18] Maassen, D., F. Rautschke, and G. Boeck (2018). “A 50 W Wideband Hybrid Ku-band GaN-

HEMT Power Amplifier for Satellite Communication”. In: 2018 11th German Microwave Con-

ference (GeMiC), pp. 5–8. DOI:10.23919/GEMIC.2018.8335014.

[Maa+op] — (forthcoming). “Lower Ku-band GaN-HEMT MIC power amplifier for satel-

lite communication”. In: Electronics Letters, p. 0.

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Co. Authored Publications

[Kon+16] Konc, O., D. Maassen, F. Rautschke, and G. Boeck (2016). “Wideband substrate integrated

waveguide Ku-band coupler”. In: 2016 21st International Conference on Microwave, Radar and

Wireless Communications (MIKON).DOI:10.1109/MIKON.2016.7491958.

[Rau+16b] Rautschke, F., D. Maassen, O. Konc, and G. Boeck (2016b). “Comparison of conven-

tional and substrate integrated waveguide filters for satellite communication”. In: 2016

IEEE MTT-S International Wireless Symposium (IWS).DOI:10. 1109/IEEE - IWS.2016 .

7585467.

[Rau+17b] Rautschke, F., D. Maassen, A. Hamidian, and G. Boeck (2017b). “ISISTAR: Integriertes Satel-

litenterminal für stationäre Vernetzung”. de. In: DOI:10.2314/GBV:1000765903.

[Saa+14] Saad, P., D. Maassen, and G. Boeck (2014). “Efficient and wideband two-stage 100 W GaN-

HEMT power amplifier”. In: Microwave Conference (EuMC), 2014 European. 9, pp. 337–340.

DOI:10.1109/EuMIC.2014.6997861.

Authored Workshops

[Maa+17d] Maassen, D., F. Rautschke, and G. Boeck (2017d). “Linear GaN Transmitter for Ku-Band

VSAT”. In: Workshop High Efficiency Power Amplifiers and Smart Transmitters (EuMC).

Own Publications not cited in this Thesis

[Dre+17] Drews, S., F. Rautschke, D. Maassen, C. T. Nghe, and G. Boeck (2017). “A 10-W S-Band

Power Amplifier for Future 5G Communication”. In: 2017 47th European Microwave Confer-

ence (EuMC), pp. 152–155. DOI:10.23919/EuMC.2017.8230822.

[Ham+14] Hamidian, A., D. Maassen, and G. Boeck (2014). “Power, Bandwidth and Efficiency Con-

siderations for High Power GaN Amplifiers”. In: Workshop High Efficiency Power Amplifiers

and Smart Transmitters (EuMC).

[Maa+15b] Maassen, D., F. Rautschke, E. Stavrou, S. Otto, I. Nistal, G. Boeck, and M. Geissler (2015b).

“ISITAR Innovative Satellite Terminal”. In: 4. Nationale Konferenz Satellitenkommunikation in

Deutschland.

[Maa+17b] Maassen, D., F. Rautschke, E. Stavrou, S. Otto, R. Moll, M. Boettcher, G. Boeck, and M.

Geissler (2017b). “ISITAR Innovative Satellite Terminal”. In: 5. Nationale Konferenz Satel-

litenkommunikation in Deutschland.

[May+17] May, S., D. Maassen, F. Rautschke, and G. Boeck (2017). “Two Stage 4 8 GHz, 5W GaN-

HEMT Amplifier”. In: 2017 47th European Microwave Conference (EuMC), pp. 136–139. DOI:

10.23919/EuMC.2017.8230818.

[Ngh+15] Nghe, C. T., D. Maassen, G. Zimmer, and G. Boeck (2015). “Wideband two-stage 50W GaN-

HEMT power amplifier”. In: 2015 German Microwave Conference, pp. 17–20. DOI:10.1109/

GEMIC.2015.7107741.

[Ngh+16] Nghe, C. T., D. Maassen, G. Boeck, J. Guan, A. Aref, and R. Negra (2016). “160 W peak

highly linear multilevel outphasing transmitter”. In: 2016 46th European Microwave Confer-

ence (EuMC), pp. 1091–1094. DOI:10.1109/EuMC.2016.7824537.

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[Ngh+17] Nghe, C. T., D. Maassen, X. A. Nghiem, and G. Boeck (2017). “Ultra-wideband efficient

linearized 10W GaN-HEMT power amplifier”. In: 2017 IEEE International Symposium on

Radio-Frequency Integration Technology (RFIT), pp. 189–191. DOI:10.1109/RFIT.2017.

8048245.

[Rau+16a] Rautschke, F., D. Maassen, F. Ohnimus, L. Schenk, U. Dalisda, and G. Boeck (2016a). “A

hybrid 50-W GaN-HEMT Ku-band power amplifier”. In: 2016 46th European Microwave

Conference (EuMC), pp. 1079–1082. DOI:10.1109/EuMC.2016.7824534.

[Rau+17a] Rautschke, F., D. Maassen, and G. Boeck (2017a). “Hybrid Ku-Band GaN-PAs for innova-

tive VSAT”. In: 5. Nationale Konferenz Satellitenkommunikation in Deutschland.