Generating Processors from
Specications of Instruction Sets
Dissertation
A thesis submitted to the
Faculty of Electrical Engineering, Computer Science, and Mathematics
of the
University of Paderborn
in partial fulllment of the requirements for the degree of
Doctor rerum naturalium (Dr. rer. nat.)
by
Ralf Dreesen
Paderborn, September 2011
Supervisor:
Prof. Dr. Uwe Kastens (University of Paderborn)
Reviewer:
Prof. Dr. Uwe Kastens (University of Paderborn)
Prof. Dr. Marco Platzner (University of Paderborn)
Prof. Dr.-Ing. Ulrich R¨
uckert (University of Bielefeld)
Additional members of committee:
Prof. Dr. Franz Rammig (University of Paderborn)
Dr. Matthias Fischer (University of Paderborn)
Submitted: 15.09.2011
Examination: 6.12.2011
Published: 9.12.2011
Acknowledgments
I would like to use this opportunity to show my gratitude to all people who
supported me during this thesis.
First of all, I would like to thank my adviser Professor Uwe Kastens, for
the support and guidance he gave me and which significantly contributed to the
quality of this thesis. Professor Kastens allowed me great latitude in the design
of the system and has shown me the right direction during numerous fruitful
discussions. I want to thank Professor Ulrich R¨
uckert and Professor Marco
Platzner for their interest in my thesis and reviewing. In addition, I would like
to thank Professor R¨
uckert for the constructive cooperation with his research
group.
I am obliged to many of my colleagues, who accompanied me in the past
years. In particular, I owe earnest thankfulness to Dr. Michael Thies for many
intensive discussions during coffee break. Special thanks go to Thorsten Junge-
blut for helping me in the area of hardware design and giving me access to the
respective infrastructure.
I would like to show my gratitude to Friederike Sudholt and Paul Jaessing
for proof reading, in particular as the subject is far away from their profession.
My personal thanks go to Johanna Sudholt, who has supported me throughout
this thesis, as she has done for the past 12 years. I am thankful to my parents
for giving me advice and virtues for my life.
Paderborn, 15.09.2011 Ralf Dreesen
Abstract
Most digital systems include microprocessors, as they are very flexible. Some
of these microprocessors are tailored to the respective area of application, to
optimize execution time and power consumption. An efficient development of
such processors necessitates convenient development tools.
This thesis contributes a specification language called ViDL and two gen-
erators for rapid development of application specific processors. A developer
specifies an instruction set in ViDL, then generates an instruction set simulator
as well as a microarchitectural processor implementation from that specifica-
tion. ViDL provides powerful concepts to specify a wide range of instruction
sets at a high level of abstraction. For instance, the pipeline and its control are
not defined by the developer, but contributed automatically by the processor
generator. To demonstrate the power of ViDL, real world instruction sets, such
as MIPS, ARM, Power and CoreVA have been specified. A ViDL specification
is very similar to instruction set manuals, which allows for rapid formalization
(e.g. one day for MIPS).
The generated high speed simulators execute 60 million instructions per sec-
ond (Mips) on average with a peak performance of 140 Mips. The generated
processor implementations yield a clock frequency of 600 MHz on a 65nm ST
Microelectronics low power technology. The processor generator produces a
pipelined n-stage microarchitecture, where nis automatically derived from a
user defined target clock frequency (e.g. 600 MHz) and instruction semantics.
As a result, different microarchitectural implementations (e.g. 2-stage and 6-
stage) can be generated at no extra effort. All processors and the simulator are
guaranteed to be consistent, as they are generated from the very same specifi-
cation. There is no way that a ViDL user can break this consistency, neither by
mistake nor by intention.
To prove the fitness of ViDL for design space exploration (DSE) and in-
struction set extension (ISE), a new application specific processor has been
developed as part of this thesis. The processor called DNACore is based on
MIPS and includes a sophisticated SIMD instruction set extension to acceler-
ate the Smith-Waterman algorithm. The algorithm is used in bioinformatics
to align DNA, RNA and protein sequences. The generated processor is freely
programmable and achieves a throughput of 2.6 billion cell updates per second
(GCUPS) at an estimated power consumption of only 0.05 W.
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