Document [original]

Appl. Phys. Lett. 95, 242114 (2009); https://doi.org/10.1063/1.3275758 95, 242114

Hole-based memory operation in an InAs/

GaAs quantum dot heterostructure

Cite as: Appl. Phys. Lett. 95, 242114 (2009); https://doi.org/10.1063/1.3275758

Submitted: 20 October 2009 • Accepted: 26 November 2009 • Published Online: 18 December 2009

A. Marent, T. Nowozin, J. Gelze, et al.

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Hole-based memory operation in an InAs/GaAs quantum dot heterostructure

A. Marent,a兲T. Nowozin, J. Gelze, F. Luckert, and D. Bimberg

Institut für Festkörperphysik, Technische Universität Berlin, Hardenbergstrasse 36, 10623 Berlin, Germany

共Received 20 October 2009; accepted 26 November 2009; published online 18 December 2009兲

We present an InAs/GaAs quantum dot 共QD兲memory structure with all-electrical data access which

uses holes as charge carriers. Charging and discharging of the QDs are clearly controlled by a gate

voltage. The stored information is read-out by a two-dimensional hole gas underneath the QD-layer.

Time resolved drain-current-measurements demonstrate the memory operation. Present write times

Distinct types of memories will combine the advantages

of nonvolatility of the Flash-memory1and the performance

and endurance of the dynamic random access memory

共DRAM兲.2A large variety of such memory concepts has been

proposed using different approaches, like FeRAM, MRAM,

PCRAM, etc.3One of the most promising options for charge-

based memories is based on self-organized quantum dots

共QDs兲as memory units. Memory operation for III-V QD

structures has been demonstrated, either based on

optically4–6or electrically controlled charge storage.7–9All

these memory structures were based on electron storage. A

two-dimensional 共2D兲electron gas was used to detect the

state of the memory. We have recently proposed an alterna-

tive all-electrical memory concept based on III-V QDs

共QD-Flash兲10,11 which allows the storage of holes.

Hole storage offers significant advantages with respect to

scalability and storage time. The energy levels of confined

holes in a QD are much more closely spaced than those of

electrons due to their larger effective mass.12,13 Thus, at least

one order of magnitude more holes can be stored in a given

volume than electrons. In addition, hole-confining type-II

systems 共e.g., GaSb/AlGaAs QDs兲provide huge hole local-

ization energies leading to storage times of more than ten

years at room temperature,14 a basic prerequisite for a non-

volatile memory.

In this letter, we present the prototype of an InAs/GaAs

QD memory structure which uses holes as charge carriers

instead of electrons. For monitoring, the commonly used

electron channel is replaced by a 2D hole gas 共2DHG兲em-

bedded underneath the QD layer. Static and time-resolved

measurements of storage, write, and erase times demonstrate

the feasibility of the hole-based QD-Flash concept.

The prototype consists of a quantum-well modulation-

doped field-effect transistor with a single InAs/GaAs QD

layer in close vicinity to the 2DHG. A schematic cross sec-

tion of the layer structure grown by metalorganic chemical

vapor deposition is shown in Fig. 1共a兲.A1

␮

m thick un-

doped GaAs buffer layer was grown first on an undoped

GaAs substrate. The 2DHG was formed with 40 nm p-doped

共p=2⫻1018 cm−3兲GaAs,a7nmthick undoped GaAs

spacer layer, and an 8 nm thick In0.25Ga0.75As quantum well.

Subsequently, 20 nm undoped GaAs was deposited, followed

by a single InAs QD layer 共nominally ⬃1.8 ML兲. Finally,

the structure was completed by a 180 nm undoped GaAs cap.

The heterostructure was processed into Hall bars with an

active area of 310⫻460

␮

m2using chemical wet etching

关see Fig. 1共b兲兴. The source and drain areas were metallized

using a Ni/Zn/Au alloy which was annealed at 400 °C for 3

min to form ohmic contacts down to the 2DHG. The gate

was formed by Ni/Au. Hall measurements yielded a charge

carrier density and a mobility of the 2DHG at 77 K of

8⫻1011 cm−2 and 4350 cm2/Vs, respectively.

Figure 2schematically shows the valence band of the

structure for the three memory operations: storage, writing,

and erasing. At the storage position 关Fig. 2共a兲兴, the binding

potential of holes in the QDs represents the emission barrier,

needed to store a logic “1.” To store a logic “0” 共defined as

empty QDs兲a capture barrier is necessary, which is formed

by the band-bending of the Schottky contact. The storage

time for both logic states is limited by the emission and

capture processes of the QDs.15,16 In our structure, thermally

assisted tunneling across the emission and capture barriers

initiates the discharging and charging processes.17,18 The

emission and capture rates depend on the barrier height 共i.e.,

localization energy and capture barrier height兲, the tempera-

ture, and the electric field. To write a logic “1” 关Fig. 2共b兲兴a

negative bias is applied to the gate. This completely elimi-

nates the capture barrier formed by the band-bending and

fast write times down to nanoseconds can be realized.11

Thus, the QD-Flash concept solves the drawbacks of Flash’s

SiO2barriers by using a large barrier height which can, how-

ever, almost be decreased to zero during write operation.

Write times similar to those of DRAMs or even shorter are

possible. To erase the information 关Fig. 2共c兲兴the electric field

at the position of the QDs is increased by applying a positive

bias such that tunnel emission occurs. The read-out of the

stored information is done via the 2DHG below the QD

layer. Carriers stored in the QDs reduce the charge density

and the mobility in the 2DHG resulting in a lower conduc-

tance of the 2DHG when the QDs are occupied.

a兲Electronic mail: [email protected].

In Ga As

0.25 0.75

i-GaAs

Hall-

contacts

7nm

8nm

i-GaAs

Gate

ource Drain

substrate

InAs QDs

i-GaAs

Gate

Source

Drain

(a) (b)

1µm i-GaAs

40nm p-GaAs

180nm

20nm

FIG. 1. 共Color online兲共a兲Schematic cross section of the layer structure. 共b兲

Sketch of the QD-Flash prototype. Hall-contacts are used for transport mea-

surements of the 2DHG.

APPLIED PHYSICS LETTERS 95, 242114 共2009兲

To investigate the influence of holes stored in the QDs

on the conductance of the 2DHG, the drain current IDversus

gate voltage VGwas measured in the dark with a fixed drain-

source voltage of 100 mV. Figure 3共a兲shows the measured

hysteresis at a temperature of 50 K. The measurement cycle

starts with a 10 ms long charging pulse 共VG=−1 V兲, which

shifts the QD states below the Fermi level, charging them

with holes from the 2DHG 关see Fig. 2共b兲兴. When the gate

voltage is now swept to 1.5 V, the drain current decreases

until the 2DHG is pinched off at about 1.1 V. During the

down sweep the QDs remain occupied, if the sweep time is

shorter than the hole storage time in the QDs. At VG

=1.5 V the QD states are far above the Fermi level 关see Fig.

2共c兲兴and tunnel emission discharges the QDs. When the gate

voltage is swept back to ⫺1 V a larger current is observed

leading to a distinct hysteresis opening. The hysteresis origi-

nates from the influence of holes stored in the QDs on the

conductance of the 2DHG during the down sweep. The

charged QDs act as Coulomb scattering centers, reducing the

mobility of the 2DHG.19,20 In addition, using Gauss’ law it

was predicted that the transfer of holes in QDs lead to a

reduction in the carrier density in the 2DHG.21–23 Both, the

lowered charge carrier density and the decreased mobility

reduce the conductance during the down sweep, resulting in

a lower current trace compared to the up sweep.

The maximum hysteresis opening 共with respect to the up

sweep兲is shown in Fig. 3共b兲as a function of temperature for

two different sweep times. Using a sweep time of 1 ms, the

hysteresis opening drops from 32% at 20 K to almost zero at

85 K. The descent has its origin in the reduced charge carrier

storage time of QDs with increasing temperature, i.e., at

higher temperatures more holes are emitted during the down

sweep. Balocco et al.7have previously reported a high-

temperature memory effect due to deep levels for a similar

InAs QD-structure. Here, the absence of such high-

temperature memory effects proves that not deep levels but

in fact the QDs act as memory units. This conclusion is

confirmed by previous investigations of hole emission

from similar InAs/GaAs QDs by deep level transient

spectroscopy,15 which resulted in a thermal emission time

constant of 5 ms at 90 K for the QD hole ground state, in

agreement with the disappearance of the hysteresis at 85 K

for a sweep time of 1 ms. A sweep time of 100 ms further

reduces the hysteresis opening as compared to 1 ms, since

more holes, stored in the QDs, are emitted during the slower

down sweep. An increased maximum hysteresis opening

is expected using larger QD densities and/or multiple QD

layers.

The memory operation of the QD-Flash prototype is

studied by time-resolved measurements of the drain current

at different storage voltages VSt, with either initially occu-

pied or empty QDs. The QDs are charged or discharged by

applying a gate voltage of ⫺0.8 or 2 V, respectively. After

this initialization of the “1” or “0,” the gate voltage was

abruptly changed to the storage voltage and the drain current

was measured as a function of time. Figure 4shows the

transients at 50 K for three different storage voltages 共0, 0.4,

and 0.7 V兲. The upper transients represent hole capture into

initially empty QDs, leading to a decrease in the conductance

of the 2DHG and, hence, to a decrease in the drain current.

The lower transients represent hole emission out of fully oc-

cupied QDs and, thus, the drain current increases to the equi-

librium state. A change of the storage voltage from 0 to 0.4 V

and further to 0.7 V causes multiple effects 关Figs. 4共a兲–4共c兲兴;

the time constants of both transients increase, the amplitude

of the capture transient is reduced, and the amplitude of the

emission transient is increased. These effects can be ex-

plained by the changes of the capture and emission processes

when applying a positive storage voltage to the structure. On

the right hand side of Figs. 4共a兲–4共c兲the valence band pro-

files for the three storage voltages are shown. The amplitudes

of the transients represent the amount of transferred holes

and are correlated with the number of levels which are below

the Fermi level 共for capture兲and above the Fermi level 共for

emission兲. A larger positive storage voltage shifts the Fermi

level toward the QD ground state and, hence, more holes are

emitted, less holes are captured, and thus the amplitudes

vary. The prolongation of the time constants is also related to

the Fermi level shift as it leads to an increased capture and

emission barrier height 共Ebar in Fig. 4兲.

Finally, we measured the write and erase times of the

memory structure. To determine write and erase times, we

used a method which allowed to study emission from or

capture into QDs across an enlarged span of time constants

共described in detail in Ref. 24兲. The hysteresis opening at a

storage position of 0.4 V was measured after applying write/

erase pulses with successively reduced pulse widths down to

10 ns. When the pulse width was too short for any charging/

(

)

Stora

(

)

Erasin

(

)

Writin

Hole Energy

Gate

2DHG

p-doping

Capture

Bias Tunnel

emission

Bias

Emission

barrier Capture

barrier

EFE

FIG. 2. 共Color online兲Schematic illustration of the storage 共a兲, write 共b兲,

and erase 共c兲operations in the QD-Flash prototype.

-0.5

0.0

0.5 1.0 1.5

V (V)

I (µA)

50 K

Temperature (K)

20 40 60 80

(a) (b)

Sweep time:

1ms

100ms

Hysteresis

opening

Relative Hys. opening (%

)

Sweep time 1 ms

FIG. 3. 共Color online兲共a兲Hysteresis at 50 K. 共b兲Temperature dependence

of the hysteresis opening for a sweep time of 1 and 100 ms, respectively.

0 50 100 150 200

Time

(

)

I (µA)

After erasing

After writing

50 K (a)

8.5

7.5

(b)

(c)

V = 0.0 V

V = 0.4 V

V = 0.7 V

Ebar

FIG. 4. 共Color online兲Drain current transients at 50 K at a storage voltage

of 0 V 共a兲, 0.4 V 共b兲, and 0.7 V 共c兲. Insets show the valence band profiles at

the given voltages.

242114-2 Marent et al. Appl. Phys. Lett. 95, 242114 共2009兲

discharging of the QDs, the hysteresis opening vanished. We

defined the write/erase time as the pulse width, at which the

hysteresis opening drops to 50% of the maximum value. Fig-

ure 5共a兲shows the write time in dependence on the write

pulse voltage at 20 and 50 K. A more negative write pulse

leads to a reduction in the capture barrier during writing and,

hence, the write time decreases exponentially. For write

pulses larger than 兩0.5兩V the write time starts to saturate and

reaches a minimum at 80 ns for a write pulse of ⫺1.75 V.

This saturation has presently its origin in a parasitic cutoff

frequency of about 2 MHz of the RC low pass of our present

devices. Much faster write times are expected for smaller

devices having larger parasitic cut-off frequencies. The erase

times are shown in Fig. 5共b兲. A minimum erase time of 350

ns at 50 K was obtained for an erase pulse of 2.5 V. The

temperature dependence of the write and erase times reflects

again the increased thermal capture and emission rates at

higher temperatures.

In conclusion, we presented the prototype of a hole-

based memory device using InAs/GaAs QDs for charge car-

rier storage. Charging and discharging of the QDs are clearly

controlled by a gate voltage. We demonstrated read-out of

the stored information using a 2DHG, with a relative hyster-

esis opening up to 32%. Write and erase times were studied.

Write times down to 80 ns only a factor of 8 larger than for

a typical DRAM25 and erase times of 350 ns four orders

faster than for a typical Flash1were demonstrated. The re-

sults support our assumption that the QDs act as memory

units and confirm the feasibility of our hole-based memory

concept.

The work was partly funded by the DFG in the frame-

work of the NanoSci-E+ project QD2D of the European

Commission and project BI 284/29-1. The authors thank M.

Geller for valuable discussions.

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(a) (b)

20 K

50 K

Write pulse voltage (V)

0.0 -0.5 -1.0 -1.5 -2.0

50% write time limit (s)

10-

10-4

10-5

10-6

10-7

10-5

10-6

50% erase time limit (s)

1.5 2.0 2.5

Erase pulse voltage (V)

20 K

50 K

FIG. 5. 共Color online兲Write times 共a兲and erase times 共b兲in dependence on

the pulse voltage.

242114-3 Marent et al. Appl. Phys. Lett. 95, 242114 共2009兲