Document [original]

High-Power GaAs-Based Diode Lasers

with Novel Lateral Designs for Enhanced

Brightness, Threshold and Efficiency

vorgelegt von

M. Sc.

Mohamed Elattar

ORCID: 0000-0003-0822-0297

an der Fakultät IV – Elektrotechnik und Informatik

der Technischen Universität Berlin

zur Erlangung des akademischen Grades

Doktor der Ingenieurwissenschaften

– Dr.-Ing. –

genehmigte Dissertation

Promotionsausschuss:

Vorsitzender: Prof. Dr. Wolfgang Heinrich

Gutachter: Prof. Dr. Günther Tränkle

Gutachter: Prof. Dr. Peter M. Smowton

Gutachter: Prof. Dr. Michael Kneissl

Tag der wissenschaftlichen Aussprache: 23. Februar 2024

Berlin 2024

Abstract

In an ever-growing multi-billion-dollar laser device market, semiconductor diode lasers continue

to be in high demand as one of the most widely-used device types, generating a large share of the

total revenue. GaAs-based broad-area diode lasers (BALs) operating in the 9xx

wavelength

range offer the highest optical power (

Popt

) among diode lasers and the highest power conversion

efficiency (

ηE

) among all light sources. This makes them ideal for high-power material processing

applications such as metal cutting and welding, where they are either utilized directly or as pump

sources for solid-state and fiber lasers. In addition to high

Popt

and

ηE

, these applications also

benefit from high beam quality, which is offered by BALs along the vertical (fast) axis but less

so along the lateral (slow) axis, corresponding to relatively high lateral beam parameter product

(

BPPlat

) and low lateral brightness (

Blat

Popt/BPPlat

). To enhance material-processing

systems and enable new applications, BALs with ever-higher

Popt

ηE

and

Blat

are highly

desirable, with high degree of polarization (

DoP

) as an additional requirement that enables

Popt

doubling with no

BPPlat

penalty via polarization beam combining. Such performance

enhancements are dependent on identifying the thermal and non-thermal mechanisms that

limit different aspects of BAL performance, and implementing design changes to minimize

their negative impacts. In this dissertation, novel designs based on lateral structuring are

devised and developed, aiming to address various performance-limiting mechanisms acting

along the lateral axis, thereby enabling enhanced BAL performance.

The first novel lateral design is the enhanced self-aligned structure (eSAS), an improved

version of the established self-aligned structure, based on integrating laterally-structured

current-blocking layers outside the BAL stripe. By confining current (and charge carriers) to

the center, it aims to enhance BAL performance by minimizing two non-thermal performance-

limiting mechanisms, namely lateral current spreading and lateral carrier accumulation (LCA)

at the stripe edges. A detailed and comprehensive eSAS study constitutes the main part of this

dissertation, starting with developing and optimizing two eSAS design variants using device

modeling and simulation tools, which are then realized in trial and full wafer processes

with quality control tests used to verify their correct implementation, followed by test

device mounting and characterization under continuous-wave operation at 25

°C

, and finally

performance analysis and benchmarking. In comparison to gain-guided reference BALs, eSAS

BALs are found to have strongly reduced threshold current with power-current slope and series

resistance roughly unchanged, leading to an increase in peak

ηE

by up to 1.5 percentage points,

reaching up to 69%. They also demonstrate strong narrowing of the near-field width with the

far-field angle roughly unchanged, leading to a

Blat

increase by up to 13

5%, reaching up to

43 W

(

mm·mrad

). In addition, they exhibit very high

DoP

(

∼

99% on average), showing no

degradation resulting from the lateral structuring. Overall, eSAS BALs are shown to exhibit

state-of-the-art performance, demonstrating simultaneously high

ηE

Blat

and

DoP

up to high

Popt levels.

The second novel lateral design is based on confining heat flow under the central stripe

and limiting its dissipation outside it, with the aim of flattening the lateral temperature

profile around the active zone, corresponding to reduced thermal lens curvature, which is

associated with reduced far-field blooming and enhanced beam quality. This is achieved by

laterally structuring p-side epitaxial layers, replacing them outside the stripe with heat-blocking

materials with low thermal conductivity (

), with examples including InGaP or InGaAsP

(lattice-matched to GaAs), a superlattice of alternating InGaP and InGaAsP layers, photonic

crystals with air holes, porous oxides or nitrides, or simply air in a mesa configuration. Similar

approaches have previously been implemented outside the semiconductor chip (structuring

p-side metallization), exhibiting

Blat

enhancement, but their impact is expected to be limited

by the experimentally-observed thermal barrier at the p-side semiconductor–metal interface,

thus motivating this alternative chip-internal approach. Using a detailed two-dimensional

mounted BAL model, finite-element thermal simulations, calibrated against thermal camera

images, are carried out to compare heat distribution within different lateral design variants

in comparison to the gain-guided reference. Significant reduction of thermal lens curvature

is demonstrated using the novel design, reaching up to 13%,17% and 73% using InGaP,

superlattice, and air, respectively, coming at the expense of increased process complexity (in

case of InGaP and superlattice), or increased thermal resistance and risk of

DoP

degradation

(in case of air). The simulation results nonetheless demonstrate that this novel lateral design is

a promising approach for enhancing beam quality and increasing

Blat

, thereby motivating its

practical realization as an exciting topic for future studies.

Kurzfassung

In einem ständig wachsenden, mehrere Milliarden Dollar schweren Markt für Laserbauelemente

sind Halbleiterdiodenlaser nach wie vor sehr gefragt, da sie zu den am weitesten verbreiteten

Bauelementen gehören und einen großen Anteil am Gesamtumsatz ausmachen. GaAs-basierte

Breitstreifen-Diodenlaser (BAL), die im Wellenlängenbereich von 9xx

arbeiten, bieten

die höchste optische Leistung (

Popt

) unter den Diodenlasern und die höchste Leistungsum-

wandlungseffizienz (

ηE

) unter allen Lichtquellen. Damit sind sie ideal für Hochleistungs-

Materialbearbeitungsanwendungen wie Metallschneiden und -schweißen, wo sie entweder

direkt oder als Pumpquelle für Festkörper- und Faserlaser eingesetzt werden. Zusätzlich

zu den hohen

Popt

- und

ηE

-Werten profitieren diese Anwendungen auch von der hohen

Strahlqualität, die BAL entlang der vertikalen (schnellen) Achse bieten, aber weniger entlang

der lateralen (langsamen) Achse, was einem relativ hohen lateralen Strahlparameterprodukt

(

BPPlat

) und einer geringen lateralen Brillanz (

Blat

Popt/BPPlat

) entspricht. Um

Materialbearbeitungssysteme zu verbessern und neue Anwendungen zu ermöglichen, sind

BAL mit immer höheren

Popt

ηE

- und

Blat

-Werten äußerst wünschenswert, wobei ein hoher

Polarisationsgrad (

DoP

) eine zusätzliche Voraussetzung ist, die eine

Popt

-Verdoppelung ohne

BPPlat

-Nachteil durch Polarisationskopplung ermöglicht. Solche Leistungsverbesserungen

hängen von der Identifizierung der thermischen und nicht-thermischen Mechanismen ab, die

verschiedene Aspekte der BAL-Leistung einschränken, und von der Implementierung von

Designänderungen, um deren negative Auswirkungen zu minimieren. In dieser Dissertation

werden neuartige, auf der lateralen Strukturierung basierende Designs entworfen und entwickelt,

die darauf abzielen, verschiedene leistungsbegrenzende Mechanismen entlang der lateralen

Achse anzugehen und dadurch eine verbesserte BAL-Leistung zu ermöglichen.

Das erste neuartige laterale Design ist die “enhanced self-aligned”-Struktur (eSAS), eine

verbesserte Version der etablierten “self-aligned”-Struktur, die auf der Integration lateral

strukturierter stromsperrender Schichten außerhalb des BAL-Streifens basiert. Durch die

zentrale Begrenzung von Strom (und Ladungsträgern) soll die BAL-Leistung verbessert werden,

indem zwei nichtthermische leistungsbegrenzende Mechanismen minimiert werden, nämlich

die laterale Stromausbreitung und die laterale Ladungsträgerakkumulation (LCA) an den

Streifenkanten. Eine detaillierte und umfassende eSAS-Studie bildet den Hauptteil dieser

Dissertation, beginnend mit der Entwicklung und Optimierung von zwei eSAS-Designvarianten

unter Verwendung von Bauelementemodellierungs- und Simulationssoftware, die dann in

Versuchs- und Vollwafer-Prozessen mit Qualitätskontrolltests zur Verifizierung ihrer korrekten

Implementierung realisiert werden, gefolgt von der Montage und Charakterisierung von

Testbauelementen im Dauerstrichbetrieb bei 25

°C

und schließlich der Leistungsanalyse und

dem Benchmarking. Im Vergleich zu verstärkungsgesteuerten Referenz-BAL weisen eSAS-BAL

einen stark verringerten Schwellenstrom auf, wobei der Leistungs-Strom-Anstieg und der

Serienwiderstand in etwa unverändert bleiben, was zu einer Steigerung des Spitzen-

ηE

bis zu 1,5 Prozentpunkte auf bis zu 69% führt. Sie zeigen auch eine starke Verengung der

Nahfeldbreite bei ungefähr unverändertem Fernfeldwinkel, was zu einem

Blat

-Anstieg um

bis zu 13

5% auf bis zu 3

43 W

(

mm·mrad

)führt. Darüber hinaus weisen sie eine sehr hohe

DoP auf (∼99% im Durchschnitt), die durch die laterale Strukturierung nicht beeinträchtigt

wird. Insgesamt zeigt sich, dass die Leistung der eSAS-BAL dem neuesten Stand der Technik

entspricht, und dass sie bis zu hohen

Popt

-Werten gleichzeitig hohe

ηE

Blat

- und

DoP

-Werte

aufweisen.

Das zweite neuartige laterale Design basiert auf der Begrenzung des Wärmeflusses unter dem

zentralen Streifen und der Minimierung der Wärmeableitung außerhalb des Streifens mit dem

Ziel, das laterale Temperaturprofil um die aktive Zone herum abzuflachen, was einer geringeren

thermischen Linsenkrümmung entspricht, die mit einem geringeren Fernfeld-Blooming und

einer verbesserten Strahlqualität verbunden ist. Dies wird durch die laterale Strukturierung

der p-seitigen Epitaxieschichten erreicht, die außerhalb des Streifens durch wärmeblockierende

Materialien mit geringer Wärmeleitfähigkeit (

) ersetzt werden. Beispiele hierfür sind InGaP

oder InGaAsP (gitterangepasst an GaAs), ein Übergitter aus abwechselnden InGaP- und

InGaAsP-Schichten, photonische Kristalle mit Luftlöchern, poröse Oxide oder Nitride, oder

einfach Luft in einer Mesa-Konfiguration. Ähnliche Ansätze wurden bereits außerhalb des

Halbleiterchips implementiert (Strukturierung der p-seitigen Metallisierung) und zeigten

einen

Blat

-Anstieg, aber ihre Wirkung dürfte durch die experimentell beobachtete thermische

Barriere an der p-seitigen Halbleiter-Metall-Grenzfläche begrenzt sein, was die Motivation

für diesen alternativen chipinternen Ansatz ist. Anhand eines detaillierten zweidimensionalen

Modells eines montierten BALs werden thermische Finite-Elemente-Simulationen durchgeführt,

die anhand von Wärmekamerabildern kalibriert werden, um die Wärmeverteilung innerhalb

verschiedener lateraler Designvarianten im Vergleich zur verstärkungsgesteuerten Referenz zu

vergleichen. Mit dem neuartigen Design wird eine erhebliche Verringerung der thermischen

Linsenkrümmung nachgewiesen, die bei InGaP, Übergitter und Luft bis zu 13%,17% bzw.

73% beträgt, was jedoch auf Kosten einer erhöhten Prozesskomplexität (im Falle von InGaP

und Übergitter) bzw. eines erhöhten thermischen Widerstands und des Risikos einer

DoP

Degradation (im Falle von Luft) geht. Die Simulationsergebnisse zeigen jedoch, dass dieses

neuartige laterale Design ein vielversprechender Ansatz zur Verbesserung der Strahlqualität

und zur Erhöhung der

Blat

ist, was seine praktische Umsetzung zu einem interessanten Thema

für zukünftige Studien macht.

List of Publications

The following articles and contributions have been published within the context of the author’s

doctoral studies, and include work that is reproduced in parts of this dissertation.

Journal articles:

–

M. Elattar, O. Brox, P. Della Casa, A. Maaßdorf, D. Martin, H. Wenzel, A. Knigge,

and P. Crump, “High-brightness broad-area diode lasers with enhanced self-aligned

lateral structure”, Semiconductor Science and Technology, vol. 35, 095011 (2020). doi:

10.1088/1361-6641/ab9bec

–

P. Crump, M. Elattar, M. J. Miah, M. Ekterai, M. M. Karow, D. Martin, A. Maaßdorf,

S. McDougall, C. Holly, S. Rauch, S. Gruetzner, S. Strohmaier, and G. Tränkle,

“Experimental Studies Into the Beam Parameter Product of GaAs High-Power Diode

Lasers”, IEEE Journal of Selected Topics in Quantum Electronics, vol. 28, no. 1:

Semiconductor Lasers, 1501111 (2022). doi:10.1109/JSTQE.2021.3095660

–

M. Elattar, O. Brox, P. Della Casa, A. Mogilatenko, A. Maaßdorf, D. Martin, H. Wenzel,

A. Knigge, M. Weyers, and P. Crump, “High-power diode lasers with in-situ-structured

lateral current blocking for improved threshold, efficiency and brightness”, Physica

Scripta, vol. 98, no. 1, 015506 (2023). doi:10.1088/1402-4896/aca637

Conference contributions and proceedings papers:

–

M. Elattar, O. Brox, P. Della Casa, A. Maaßdorf, D. Martin, H. Wenzel, A. Knigge, and

P. Crump, “Enhanced self-aligned structure for improved lateral brightness in 940

high-power broad-area diode lasers”, Proceedings of SPIE, vol. 11705, 117050N (2021).

doi:10.1117/12.2578190

–

M. Elattar, O. Brox, P. Della Casa, A. Maaßdorf, D. Martin, H. Wenzel, A. Knigge, and

P. Crump, “Improved lateral brightness in 940

high-power broad-area diode lasers

using enhanced self-aligned structure”, 34

Semiconductor and Integrated Optoelectronics

Conference (SIOE), Cardiff, U.K. (2021)

–

M. Elattar, J. Rieprich, and P. Crump, “Impact of vertical structure on thermal lensing

and lateral beam quality in high-power broad-area diode lasers”, European Semiconductor

Laser Workshop (ESLW), Paris, France (2021)

–

P. Crump, M. Elattar, M. J. Miah, M. Ekterai, M. M. Karow, D. Martin, P. Della Casa,

A. Maaßdorf, S. McDougall, C. Holly, S. Rauch, S. Gruetzner, S. Strohmaier, A. Knigge,

and G. Tränkle, “Progress in experimental studies into the beam parameter product of

GaAs-based high-power diode lasers”, Proceedings of SPIE, vol. 11983, 1198307 (2022).

doi:10.1117/12.2610277

–

M. Elattar, O. Brox, P. Della Casa, A. Mogilatenko, A. Maaßdorf, D. Martin, H.

Wenzel, A. Knigge, and P. Crump, “High-brightness broad-area diode lasers with a novel

enhanced self-aligned lateral structure”, Proceedings of 28

International Semiconductor

Laser Conference (ISLC), TuA–02 (2022). doi:10.23919/ISLC52947.2022.9943315

–

P. Crump, M. Elattar, M. J. Miah, J. Fricke, O. Brox, D. Martin, P. Della Casa, A.

Maaßdorf, H. Wenzel, A. Knigge, and G. Tränkle, “Progress in efforts to increase power

in GaAs-based high-power diode lasers”, Proceedings of 28

International Semiconductor

Laser Conference (ISLC), TuA–01 (2022). doi:10.23919/ISLC52947.2022.9943301

Patent applications:

–

P. Della Casa, M. Elattar, P. Crump, and H. Wenzel, “Diodenlaser mit Stromblende”,

German Patent DE 10 2020 120 703 A1 & International Patent WO 2022/029254 A1

(2022)

–

P. Della Casa, P. Crump, M. Elattar, and M. M. Karow, “Laserdiode mit integrierter

thermischer Blende”, German Patent DE 10 2020 133 368 A1 & International Patent

WO 2022/129075 A1 (2022)

–

P. Crump, H. Wenzel, M. Elattar, A. Maaßdorf, D. Martin, and O. Brox, “Breitstreifen-

Diodenlaser mit integriertem p-n-Tunnelübergang”, German Patent DE 10 2022 111 977

(2023)

viii

Acknowledgements

First and foremost, I would like to express my sincere gratitude to Prof. Dr. G. Tränkle, the

former scientific managing director of the Ferdinand-Braun-Institut gGmbH, Leibniz-Institut

für Höchstfrequenztechnik (FBH), for granting me the opportunity to conduct my doctoral

research under his supervision. It has been a privilege to work under his wise leadership, and I

would not have reached this point without his support in challenging moments.

I extend my gratitude to Prof. Dr. P. M. Smowton and Prof. Dr. M. Kneissl for assuming

the roles of second (external) and third reviewers, respectively. Their time and effort dedicated

to reviewing and evaluating this work are greatly appreciated.

I would also like to thank Dr. P. Crump, leader of the High-Power Diode Laser (HPDL)

research group, for overseeing my research progress and regularly providing valuable advice

based on his vast experience. I am especially thankful for the time and effort he dedicated to

reading an earlier draft of this dissertation and providing helpful feedback.

My gratitude also goes to TRUMPF Laser GmbH, Niederlassung Berlin (TLB), especially

Dr. S. Strohmaier, and TRUMPF Photonics Inc. (TUSP), especially Dr. S. McDougall, for the

financial support and friendly collaboration on multiple exciting research projects.

This work would not have been possible without the contributions of many colleagues at

the FBH, whose support is greatly appreciated. From the Optoelectronics department, I would

especially like to thank Dr. H. Wenzel, Dr. O. Brox, Dr. D. Martin and Dr. A. Knigge. From

the Materials Technology department, I would especially like to thank Dr. P. Della Casa, Dr.

A. Maaßdorf, Dr. A. Mogilatenko and Prof. Dr. M. Weyers. I extend my gratitude to the

colleagues from the Process Technology and the Mounting and Assembly departments.

On a personal level, I would like to thank the current and former FBH colleagues with

whom my connection has transcended the shared workplace, making valuable memories over

the years. This includes (but is not limited to) Jan-Philipp K., Hady Y. and Mahmoud T., as

well as many HPDL group colleagues, especially A. Boni, Seval A., Martin W. and Jarez M.

I feel blessed to be able to share this achievement with my family. I am deeply thankful

to my wife Nayera for her love and companionship, for providing motivation in challenging

times, and for accepting my long working hours. I am forever indebted to my parents for their

love and support and for inspiring my passion for science, and I am grateful for my brother

and the bond we share. I would also like to acknowledge the efforts of all the teachers and

professors through every level of my education. Finally, I would like to thank my friends in

Berlin, Ulm and elsewhere, who have accompanied and encouraged me over the course of this

work, especially Ayman K. and M. Mokhtar.

This work is dedicated to my late friend Karim Sherif (1993–2019); wish you were here.

Table of Contents

Abstract iii

Kurzfassung v

List of Publications vii

Acknowledgements ix

1 Introduction 1

1.1 High-power GaAs-based broad-area diode lasers . . . . . . . . . . . . . . . . . . 1

1.2 Scope and structure of this work . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Research Methods and Techniques 9

2.1 Device modeling and simulation tools . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Device fabrication technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Characterization techniques and measurement setups . . . . . . . . . . . . . . . 15

3 Literature Review 19

3.1 Performance of state-of-the-art devices . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Limiting factors to device performance . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 Thermalmechanisms............................. 22

3.2.2 Non-thermal mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Previous lateral design approaches: benefits and limitations . . . . . . . . . . . 26

4 Enhanced Self-Aligned Lateral Structure (eSAS) 33

4.1 Device design and simulation results . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.1 Vertical (epitaxial) layer structure . . . . . . . . . . . . . . . . . . . . . 34

4.1.2 eSAS first variant (V1): lateral structure design . . . . . . . . . . . . . . 36

4.1.3 eSAS second variant (V2): lateral structure design . . . . . . . . . . . . 38

4.1.4 Estimated performance benefits . . . . . . . . . . . . . . . . . . . . . . . 44

4.2 eSAS first variant (V1): realization and quality control . . . . . . . . . . . . . . 47

4.3 eSAS second variant (V2): realization and quality control . . . . . . . . . . . . 49

4.4 Device characterization and measurement results . . . . . . . . . . . . . . . . . 55

4.5 Overviewandoutlook ................................ 66

TABLE OF CONTENTS

5 Chip-Internal Thermal Path Engineering: Design and Outlook 69

5.1 Motivationandpriorart............................... 69

5.2 Thermal simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3 Thermal simulation results and analysis . . . . . . . . . . . . . . . . . . . . . . 72

6 Summary and Conclusion 77

List of Figures 81

List of Tables 83

Symbols and Acronyms 85

References 87

xii

Introduction

1.1 High-power GaAs-based broad-area diode lasers

Since the first demonstrations of lasing in the early 1960s and the subsequent realization of

different types of laser devices, the field has evolved into an ever-growing multi-billion-dollar

market, with a revenue reaching $17 billion in 2020 and projected to experience 10% annual

growth to reach

∼

$28 billion by 2025 [1]. This remarkable market growth has been enabled

by continuous performance improvements of laser devices as the corresponding technologies

matured, leading to their utilization in a wide array of applications. As shown in Fig. 1.1, the

largest of these applications is industrial manufacturing and materials processing, representing

roughly one-third of total revenue in 2020. The second largest application in terms of revenue

is communications, followed by aerospace and defence, having the highest projected annual

growth rate, in addition to sensing (e.g. LIDAR), electronics manufacturing (e.g. lithography),

and medical applications, among others.

Among the different types of laser devices, semiconductor diode lasers are the most widely

used, constituting a 39–40% share of total revenue, as shown in Fig. 1.1. This is attributed

to diode lasers having favorable properties in comparison to other device types, one of which

is being electrically rather than optically pumped, which enables higher power conversion

efficiencies. Modern diode lasers also demonstrate high reliability and long lifetime, enabled

by progress in crystal growth, processing technology, facet passivation and chip packaging (see

section 2.2). In addition, they are relatively inexpensive, making use of wafer-scale processing

for mass production, and tend to have smaller component size, even after packaging [2,3].

Since their first realization in 1962 [4], many variations of diode lasers have been developed and

realized, making use of different material systems to extend the range of emission wavelength

(

), as well as different device configurations, e.g. edge-emitting ridge waveguide lasers and

vertical-cavity surface-emitting lasers (VCSELs), each offering certain desirable performance

characteristics that make them ideal for specific applications. For applications that require

high optical power levels, the most widely-used variant is edge-emitting broad-area diode lasers

(BALs) based on gallium arsenide (GaAs), which are the subject of this work.

Figure 1.2 shows a schematic diagram of a standard high-power BAL with stripe width

and resonator length

, with the output laser beam emitted from its front facet. The

1. Introduction

Figure 1.1: Metrics and future trends of the global laser device market (adapted from [1]): total

revenues (in $ billion) of the overall market and the four largest application areas in 2020 and their

projected growth up to 2025 (top), and relative shares of the total revenue (in %) of the different

laser device types in 2020 and the corresponding projected values in 2025 (bottom). (©McKinsey

and Company)

steps involved in the fabrication of these devices are presented in section 2.2, with the final

configuration providing mechanisms for optical mode guiding and electrical charge carrier

confinement in the three directions (vertical, lateral and longitudinal). The vertical layer

structure of the diode laser is epitaxially grown on a GaAs substrate, and includes an active

zone at the p-n-junction with thickness

dAZ

, typically containing one or multiple quantum

wells (QWs), each with a thickness of few

. Lasing (light generation) takes place inside these

QWs, with

determined by their material composition, thickness and incorporated strain. The

optical guiding of generated light in the vertical direction is enabled by the layers surrounding

the active zone on the n- and p-sides, namely waveguide layers (with higher refractive index)

surrounded by cladding layers (with lower refractive index). In the lateral direction,

defined by lateral structuring techniques based on selective ion implantation and/or etching, in

some cases involving buried structures via multi-step epitaxial growth (see chapter 3). Finally,

in the longitudinal direction, mirror facets are formed by cleaving BALs along crystal planes

of the wafer, thus defining a Fabry-Pérot resonator with length L, followed by passivation to

improve facet stability and coating to set the reflectivities of the front and rear facets (typically

0.5–5% and 95–98%, respectively) [5–8].

GaAs-based BALs offer the highest optical power (

Popt

) among diode lasers and the highest

power conversion efficiency (

ηE

) among all light sources.

ηE

is defined as the ratio of output

1.1 High-power GaAs-based broad-area diode lasers

θ95%

W95%

front facet

active zone

n-side

p-side

vertical

lateral

longitudinal

Figure 1.2: Three-dimensional schematic diagram of a standard high-power broad-area diode

laser with stripe width

and resonator length

, where lasing (light generation) takes place inside

the active zone at the p-n-junction, and the output laser beam is emitted from the front facet.

The lateral beam parameters, namely near-field width (

W95%

) and far-field angle (

θ95%

) with 95%

power content, as well as the current path inside the device are indicated on the diagram.

(optical) to input (electrical) power, i.e.

ηE=Popt

I·U=Popt

I·(U0+RsI),(1.1)

where

is the operating (bias) current and

RsI

is the operating voltage, with

as the turn-on voltage and

as the series resistance [2,8]. In these devices, the vertical

structure is grown on a GaAs substrate, with all the epitaxial layers made of binary, ternary

and quaternary materials from the (AlGaIn)(AsP) III-V compound semiconductor family [6].

This wide variety of available material systems allows the realization of GaAs-based BALs

with a very wide range of

, roughly between 630 and 1200

, although peak

Popt

and

ηE

are significantly lower at the extremes [9]. High peak

ηE>

70% has been reported from

GaAs-based BALs over the

range between 790 and 1060

, with the highest

Popt

levels to

date achieved in the 9xx nm range [9,10].

As a result, these high-power GaAs-based BALs operating in the 9xx

range are widely

used in material processing applications, such as metal cutting and welding and additive

manufacturing, where they are either used to optically pump solid-state and fiber lasers (e.g.

Yb-doped fiber laser), or directly utilized in so-called direct diode laser systems [3,9]. In

addition to high

Popt

and

ηE

, these applications also require high brightness, i.e. maintaining

high beam quality at high

Popt

. Beam quality essentially refers to the smallest spot size into

which the laser beam can be focused, and can thus significantly affect the coupling efficiency of

the generated

Popt

into a given optical system. For example, for pumping a fiber with a specific

core diameter and numerical aperture, low beam quality of the BAL source can limit the

amount of useful

Popt

coupled into the fiber, thus reducing the overall system efficiency [3]. The

1. Introduction

beam shape in near- and far-field regions of a high-power BAL is schematically illustrated in

Fig. 1.2. The vertical waveguide is typically designed to exclusively guide a single (fundamental)

mode, which leads to the output beam having an almost diffraction-limited profile along the

vertical (fast) axis, i.e. very high vertical beam quality, despite the strong divergence shown in

the diagram. Conversely, the output beam profile along the lateral (slow) axis deviates strongly

from the ideal diffraction-limited case, corresponding to limited lateral beam quality, due to

the broad stripe allowing the guiding of a large number of modes. Lateral beam quality is

typically quantified in terms of the lateral beam parameter product (

BPPlat

), which is defined

BPPlat = 0.25 ×W95%×θ95%,(1.2)

where

W95%

is the lateral near-field width (beam waist) and

θ95%

is the lateral far-field

angle (divergence angle), both including 95% of the optical power content (see Fig. 1.2). For

improving lateral beam quality,

W95%

and

θ95%

should be minimized, corresponding to lower

BPPlat

Popt

and

BPPlat

can be combined into one key BAL performance metric, namely

lateral brightness (Blat), which is defined as

Blat =Popt

BPPlat

.(1.3)

The demand for 9xx

BALs with ever-higher power, efficiency and brightness remains high,

with the aim of realizing material processing systems with enhanced capabilities and reduced

operation costs, in addition to enabling new applications. Ongoing efforts to develop novel

BAL designs with enhanced performance in terms of

Popt

ηE

and

Blat

are therefore highly

beneficial and commercially valuable.

The peak performance achievable by a single BAL emitter (as shown in Fig. 1.2) is strongly

dependent on its dimensions and vertical structure, as well as the operating conditions. BALs

with

in the 90–120

µm

range are typical, as they tend to exhibit the best overall performance.

However, broader stripes with

as high as 1200

µm

have been used to achieve higher

Popt

while maintaining high

ηE

, but this comes at the expense of increased

BPPlat

and thus lower

peak

Blat

. Conversely, narrower stripes with

as low as 20

µm

can be used to maximize

Blat

at the expense of

Popt

and

ηE

[9]. Typical values of

are in the 1–6

range, with reported

values up to 10

. Increasing

in BALs reduces thermal resistance (

Rth

), corresponding to

enhanced heat extraction (see section 2.3), which enables higher

Blat

. However, this comes

at the expense of higher threshold current (

Ith

) and lower peak

ηE

[9,11]. Up to a certain

(around 4

), the reduced

Rth

also enables higher peak

Popt

, but with further increase

, this benefit is limited by the increasing asymmetry of the longitudinal optical profile

(longitudinal spatial hole burning; see subsection 3.2.2), which contributes to power saturation

and can thus have the opposite effect of reducing peak

Popt

[12,13]. Similar trade-offs are also

involved in the vertical structure design of high-power BALs. For example, it is mentioned

above that high vertical beam quality is typically achieved by designing the vertical waveguide

for single mode operation. It is usually desirable for this fundamental mode to have a limited

overlap with the active zone, i.e. a high

dAZ/

Γratio, where Γis the optical confinement factor

with a value typically lower than 1

5% [3,14]. This is necessary in modern high-power BALs

with large

in order to reduce internal optical losses (

αi

), with the aim of maintaining high

ηE

1.1 High-power GaAs-based broad-area diode lasers

and reducing the risk of catastrophic optical mirror damage (COMD), thus improving reliability

and enabling higher

Popt

levels. However, reducing Γcorresponds to lower modal gain, therefore

having the disadvantage of increasing

Ith

. In the presence of many such trade-offs, an optimized

vertical structure is thus crucial for enhancing the peak performance of high-power BALs.

State-of-the-art BALs with typical dimensions of

= 100

µm

and

= 3–5

have exhibited

peak

Popt

levels around 25 W under continuous-wave (CW) operation. However, operating

under pulsed conditions enables much higher

Popt

from the same devices, with short pulses

reaching up to 145 W [9,13–15]. In addition, peak performance is strongly affected by the used

mounting configuration and cooling technique, as well as the operating heat-sink temperature

(THS) [12,16–18].

For many material processing applications, the power and brightness requirements are

far beyond the capabilities of a single BAL emitter, which are limited by the degradation of

ηE

and

BPPlat

at higher

Popt

and heat levels. This necessitates the use of beam combining

techniques, which enable

Popt

scaling by combining the output beams of multiple BALs, ideally

with no beam quality penalty and thus proportional scaling of brightness. Depending on

application requirements, different beam combining techniques can be used, often with a

trade-off between simplicity and the properties of the output (combined) beam, which can

enable

Popt

scaling up to the

range. These techniques include spatial beam combining

using bar or stack configurations, spectral beam combining of multiple laser beams (from

individual BALs) with slightly varying

, and coherent beam combining based on controlling

the relative phases of multiple laser beams with identical

to obtain constructive interference,

which is the most challenging to implement but offers the highest beam quality [19–22]. A

further widely-used technique is polarization beam combining (PBC); a relatively simple

technique which enables (up to) two-fold

Popt

scaling with no beam quality penalty. In PBC,

two linearly-polarized beams with mutually perpendicular polarization states, i.e. tranverse

electric (TE) and transverse magnetic (TM) polarization, are combined using a polarizing

beam splitter [20–23]. One of the key factors that determine the polarization state of a BAL

output beam is the aforementioned strain incorporated into QWs during their growth, which

splits valence band degeneracy by separating the heavy-hole and light-hole subbands, thus

favoring light emission with a specific polarization. For example, GaAs-based 9xx

BALs

are realized using In

1−x

As QWs, which are compressively strained due to having a larger

lattice constant than GaAs. This results in heavy-hole transitions having the lowest energy,

which corresponds to TE polarization being favored, i.e. with the electric field oscillating in

the QW plane [2,23]. To apply PBC on two beams with identical polarization (e.g. output

beams of two 9xx

BAL emitters), a half-wave plate can be used to rotate the orientation of

one of them by 90

, thereby changing its polarization state. To minimize combining losses and

achieve high PBC efficiency, the beams must have high polarization purity, typically quantified

in terms of the degree of polarization (

DoP

). For BALs with predominantly TE-polarized

output beams, DoP is commonly defined as [22–25]

DoP =Popt,TE

Popt,TE +Popt,TM

,(1.4)

1. Introduction

where

Popt,TE

and

Popt,TM

are the TE- and TM-polarized optical powers, respectively. It is

sometimes alternatively defined as [26]

DoP ∗=Popt,TE −Popt,TM

Popt,TE +Popt,TM

,(1.5)

but unless stated otherwise, the former definition (Eq. 1.4) is used by default in this work. Along

with maximizing

Popt

ηE

and

Blat

, efforts to maintain high

DoP

and avoid its degradation in

novel BAL realizations are also highly important, especially due to the wide use of PBC in

industrial systems.

1.2 Scope and structure of this work

As discussed earlier, the development of novel concepts for improved designs of 9xx

BALs

remains highly beneficial and commercially valuable, with the aim of enabling enhanced BAL

performance in terms of

Popt

ηE

, and

BPPlat

(and thus

Blat

), while maintaining high

DoP

This is the motivation and objective of this work, carried out at the Ferdinand-Braun-Institut

gGmbH, Leibniz-Institut für Höchstfrequenztechnik (FBH), with specific focus on novel design

approaches based on lateral structuring. In the following, the content and structure of the

work are described.

Chapter 2 provides an overview of the methods and techniques used to study, realize, and

evaluate BALs in this work. It starts by introducing the device modeling and simulation

software used for design optimization and performance estimation. It then reviews the

fabrication technology used to realize BALs, starting with epitaxial wafer growth, followed by

wafer processing, facet passivation and coating, and device mounting and packaging. Finally,

it introduces the measurement techniques and setups used to characterize the different aspects

of BAL performance.

A literature review is provided in chapter 3, starting with an overview of state-of-the-art

BAL performance using the best results from notable 9xx

realizations in recent publications.

This is followed by brief descriptions of the important thermal and non-thermal performance-

limiting mechanisms that have been identified over many years, highlighting the specific

performance aspects each mechanism is associated with limiting or degrading. The chapter

concludes with a review of notable lateral structuring techniques that have been developed

and implemented in previous studies to confine the flow of current and charge carriers under

the central BAL stripe, explaining the working principle of each technique and highlighting its

benefits to BAL performance as well as its limitations and drawbacks.

Chapter 4 contains a comprehensive study (involving multiple simulations and experimental

realizations) of a novel technique for current and carrier confinement based on integrating

structured current-blocking layers outside the stripe. It is found that this technique successfully

demonstrates simultaneously high

ηE

Blat

and

DoP

up to high

Popt

levels, as well as high

process quality and repeatability despite relatively high complexity. The chapter begins with a

detailed design study using modeling and simulation tools, starting with selecting a well-suited

epitaxial structure, then optimizing the blocking layer parameters and vertical position in two

design variants, and finally estimating performance benefits relative to standard gain-guided

1.2 Scope and structure of this work

BALs. This is followed by presenting the first successful realizations of both variants using

modified wafer processes that involve two-step epitaxial growth and additional processing steps,

and the results of various quality control tests carried out to verify their correct implementation.

In the following step, a large number of BALs (with and without blocking layers) are mounted

and characterized under continuous-wave operation. These measurement results are presented

and analyzed, comparing the experimentally demonstrated performance benefits to simulation

estimates, followed by benchmarking exemplary results against state-of-the-art performance.

The chapter concludes with a brief summary, providing an outlook for the novel design and

proposing related topics for future studies.

Chapter 5 presents a simulation-based design study of a novel lateral structuring technique

which follows a different approach, namely the central confinement of heat flow (rather than

current), with the aim of reducing the curvature of the lateral temperature profile around the

active zone and the associated

BPPlat

degradation. This is realized by laterally structuring

certain epitaxial layers and replacing them outside the stripe with materials with low thermal

conductivity, thereby engineering a chip-internal thermal path. The chapter starts with a

brief review of approaches implemented in previous studies to flatten the temperature profile,

presenting their benefits as well as their limitations which motivate the proposed design. This

is followed by presenting a detailed two-dimensional BAL model that is used in finite-element

thermal simulations, calibrated against thermal camera images, to calculate heat distribution

within a mounted BAL chip under given operating conditions. Using this model, the lateral

temperature profiles in multiple design variants are compared to a reference BAL (with no

heat blocking), demonstrating the expected curvature reduction. This novel design has not

been practically realized within the scope of this work, but the promising simulation results

make it an attractive approach for future realizations of high-brightness BALs.

Research Methods and Techniques

This chapter is dedicated to providing an overview of the research methodology used to study

the semiconductor devices that are the subject of this work, namely high-power edge-emitting

broad-area diode lasers (BALs) based on GaAs. It starts with section 2.1, which introduces

the software used in BAL modeling and performance simulation, followed by section 2.2, which

describes the fabrication steps used to realize them and the underlying technological aspects.

Finally, section 2.3 presents the measurement setups and techniques used to characterize the

different performance aspects of the realized BALs.

2.1 Device modeling and simulation tools

This section provides a brief introduction to the software used in this work to model high-

power BALs and simulate their different performance aspects. These simulation tools are

used for design development and optimization, and for estimating the impact of novel design

approaches prior to realization. Detailed descriptions of the full capabilities and the underlying

mathematical framework of each tool are not provided here, instead focusing on their application

within the context of this work.

The first simulation tool is a waveguide equation solver called “QIP2”, that was developed

at the FBH [27]. Based on the refractive index profile of a given epitaxial (vertical) layer

structure, QIP2 uses the effective refractive index (

neff

) method, as described in [27,28], to

solve the waveguide equation for the guided vertical modes and simulate their optical intensity

profiles (e.g. Fig. 4.1), thereby enabling the calculation of various key parameters for each

mode, including the QW optical confinement factor (Γ), internal optical loss (

αi

), near-field

width and far-field angle. Γis defined as the fraction of the total mode intensity that overlaps

with the QW, i.e.

Γ = 





dAZ/2

∫︂

−dAZ/2Iy(y)dy 



/︄



∞

∫︂

−∞ Iy(y)dy 

,(2.1)

where

(

)is the vertical mode intensity profile (with

= 0 at the QW center) and

dAZ

the active zone thickness [2,5,29]. Although multiple loss mechanisms contribute to

αi

, free

carrier absorption can generally be assumed to be the dominant factor [8,30,31], and can be

2. Research Methods and Techniques

calculated as

α(FCA)

i=∫︂Iy(y)n(y)

neff

(σnNn(y) + σpNp(y)) dy, (2.2)

with

(

)as the refractive index profile,

(

)and

(

)as the electron and hole density

profiles, respectively, and

σn

and

σp

as the corresponding free carrier absorption cross sections.

In this simulation,

αi

is therefore approximated as

αi≈α(FCA)

i,QW

α(FCA)

i,WG

, with the two terms

corresponding to free carrier absorption in the QW and in its surrounding layers that form the

optical waveguide, respectively. The first term is separately calculated by reducing equation 2.2

(assuming quasi-neutrality) to

α(FCA)

i,QW

= Γ

Nth (σn+σp)

, where

Nth

is the threshold carrier

density in the QW, estimated based on calculations of material gain spectra using another

FBH internal software called “kp8” [29,32]. Following equation 2.2,

α(FCA)

i,WG

is calculated by

QIP2 as the sum of contributions of all the other layers, with the loss contribution of each

layer estimated by calculating its modal confinement factor (analog to equation 2.1) and

replacing

and

with the corresponding doping concentration (i.e. ignoring minority

carriers). For both the QW and waveguide calculations,

σn

and

σp

are given as 3

−18

and 11

−18 cm2

, respectively, as empirically estimated in [8,33], i.e. three times higher free

carrier absorption for holes (on the p-side) than for electrons (on the n-side). In addition,

QIP2 also calculates the total sheet resistance of the layer structure, based on the thickness

and resistivity of each layer [8,27]. Moreover, this simulation can be extended to two regions

with similar but non-identical layer structures, representing the central and outer regions in

a laterally-structured BAL. This enables, for example, the estimation of the lateral effective

refractive index step (∆

neff

) and thus the expected lateral waveguiding in such devices (e.g.

Figs. 4.4 and 4.9).

Another simulation tool is “WIAS-TeSCA”, which was developed at the Weierstrass

Institute for Applied Analysis and Stochastics (WIAS) [34,35]. For a given device cross section,

it numerically solves the system of equations corresponding to the drift-diffusion model for

two-dimensional charge carrier transport, as well as the Helmholtz waveguide equation for

the guided vertical modes. Assuming spatial homogeneity along the longitudinal axis, the

optical power (

Popt,j

) of a vertical mode

can be calculated self-consistently by solving the

rate equation d

dtPopt,j=vg,j(Gj−αs,j−γj)Popt,j+P

˙spont

opt,j,(2.3)

where

vg,j

is the group velocity,

is the net gain (i.e. absorption losses subtracted),

αs,j

corresponds to additional losses (mainly due to scattering), and

γj

corresponds to outcoupling

mirror losses, while

˙spont

opt,j

is the rate of spontaneous emission into the mode [35]. For a BAL

at a given bias voltage (

), TeSCA is used in this work to calculate the corresponding current

(

) and total optical power (

Popt

), as well as the energy band diagrams and two-dimensional

current and carrier density profiles along the lateral and vertical axes (e.g. Figs. 4.11 and

4.6). A simpler version of this simulation, based on using the drift-diffusion model to simulate

one-dimensional carrier transport, is used to calculate the I-U characteristics of a given vertical

structure, which is required in this work to enable the comparison of different current-blocking

configurations (e.g. Figs. 4.2 and 4.5(a)).

The “Ansys Mechanical” finite element analysis (FEA) software is also used in this

work to simulate heat distribution within BAL chips [36,37]. Following [38,39], a detailed

2.2 Device fabrication technology

Figure 2.1: Photograph showing a GaAs wafer (with 3

′′

diameter) being placed inside a

metalorganic vapor-phase epitaxy (MOVPE) reactor for epitaxial growth of the vertical layer

structure. (©FBH)

two-dimensional cross-sectional model of a mounted BAL chip is created using “Ansys

Parametric Design Language (APDL)”, including the whole vertical layer structure as well

as the metallization layers and the package (see section 2.2), with a uniform longitudinal

thermal profile assumed for simplicity. The thermal conductivity of each material (both

semiconductor and metal) is obtained from the literature and included in the model [40,41].

At each operating point, the generated heat is calculated and appropriately distributed along

the layer structure under the BAL stripe (see section 5.2), which serves as an initial state for

the simulation. As boundary conditions for the simulation, the bottom surface of the package

is assumed to have a constant temperature (i.e.

THS

), corresponding to ideal temperature

regulation (see section 2.3), and minimal heat extraction via air convection is modeled at the

other surfaces [38]. Ansys then uses the FEA method to simulate the two-dimensional heat

flow within the chip and generate steady-state thermal profiles with high spatial resolution

along the lateral and vertical axes. This is used in this work for estimating the active-zone

temperature increase (∆

TAZ

TAZ −THS

) as well as the strength of the thermal lens (e.g.

Figs. 5.1 and 5.3).

2.2 Device fabrication technology

In this section, the sequential fabrication steps used to realize high-power GaAs-based BALs

are briefly described. The techniques used in the fabrication of GaAs-based devices in general,

and BALs in particular, have been developed and optimized over many decades, and are

comprehensively reviewed in the literature, e.g. [42,43]. BAL fabrication consists of four main

steps: epitaxial growth of the vertical layer structure, wafer processing, facet passivation and

coating, and finally device mounting and packaging.

High-quality wafer growth is a crucial requirement for the realization of high-power BALs.

To this end, one has to start with high-quality GaAs substrates which fulfill two main

2. Research Methods and Techniques

requirements: low dislocation density to avoid device failure and extend its lifetime, and high

n-type doping to minimize device

, with the substrate later (after thinning and metallization;

see below) forming the n-side contact of the laser diode [44]. The GaAs substrates used

here have (100) surface orientation, a 3

′′

) diameter, and n-doping concentration on

the order of 10

18 cm−3

. The vertical diode laser layer structure is epitaxially grown over the

substrate inside a metalorganic vapor-phase epitaxy (MOVPE) reactor, shown in Fig. 2.1.

The basic epitaxial layer structure consists of (in growth direction): n-AlGaAs cladding and

waveguide layers, an active zone at the p-n-junction (not intentionally doped), p-AlGaAs

waveguide and cladding layers, and finally a p

-GaAs contact layer. In the epitaxial structure

variant used in this work (see subsection 4.1.1), the active zone is composed of a single InGaAs

quantum well (QW), in which lasing (light generation) takes place, sandwiched between GaAsP

spacer layers, with both QW and spacer layers having thicknesses of few

. Utilizing the

lattice mismatch between In

1−x

As and GaAs, the composition and thickness of the QW are

designed to intentionally incorporate compressive strain during its growth, which is necessary

to obtain the target emission wavelength (

= 940

), reduce threshold current density,

and enable higher

DoP

by preferentially emitting TE-polarized light (see section 1.1). To

balance the strain in the QW, tensile strain is incorporated into the adjacent GaAsP spacer

layers, similarly utilizing the mismatch between GaAs

1−y

and GaAs. Conversely, the lattice

mismatch between Al

1−x

As and GaAs is very small (

13%), meaning that relatively

thick waveguide and cladding layers with strongly varying compositions (and thus refractive

indices) can be grown without introducing significant strain [6,8,45]. The p- and n-doped

waveguide and cladding layers together form a vertical waveguide for the generated light,

ideally designed for single mode guiding to minimize fast-axis divergence and optimize vertical

beam quality. Similar to the substrate on the n-side, the p

-GaAs contact layer is highly

doped to the order of 10

19 cm−3

to minimize

and ensure ohmic contact formation upon

subsequent metallization [7]. The p

-contact layer can additionally protect the active zone

from external strain that can possibly be introduced during subsequent fabrication steps (see

subsection 3.2.2).

The next step is processing the grown epitaxial wafers into BALs, making use of widely-used

techniques in semiconductor technology, including photolithography, ion implantation, wet

chemical and dry etching, metal and dielectric layer deposition, lift-off and electroplating.

Following standard FBH procedure, a 3

′′

wafer is processed into 10 test fields, each with

∼

width and composed of a number of bars with equal length (2, 4 or 6 mm, depending on test

field), as shown in Fig. 2.2(a). Each bar is either processed for further division into multiple

separate BAL chips, i.e. single emitters (SEs), or as a single large device where all emitters are

simultaneously contacted and operated, i.e. a laser bar. The former case is demonstrated in

Fig. 2.2(b), showing a test field composed of 7 bars, each including 19 SE chips with 4

length and 500

µm

chip width. Such SE chips will be the primary test devices used throughout

this work. Details of the wafer process and used techniques have been thoroughly discussed in

the literature, e.g. [7,8,42], but a brief description of the sequence of processing steps followed

here is provided for completeness. The first step is defining p-side contact windows for current

injection. This is achieved using selective shallow He

ion implantation of the p

-GaAs contact

layer, leading to strongly increased electrical resistance in the implanted areas, while the

2.2 Device fabrication technology

(a) (b)

Figure 2.2: Microscope images showing: (a) a 3

′′

wafer fully-processed into 10 test fields, each

with

∼

width, and (b) a closer view of a single test field, composed of 7 bars with 4

length,

each including 19 adjacent single-emitter (SE) chips with 500 µmchip width.

flow of current and carriers is confined to unimplanted areas which remain highly conductive.

In standard BALs with no advanced lateral structuring techniques, this shallow implant is

used to define the stripe width (

), as shown in Fig. 2.3. None of the BALs realized in

this work employ process-induced index guiding, meaning that lateral optical waveguiding is

only regulated by the injected current and carrier profiles and the associated material gain;

a mechanism referred to as gain guiding. Such gain-guided (GG) BALs, with

defined by

the shallow contact implant, represent the simplest BAL lateral configuration, and will be

used as reference devices throughout this work. After contact implantation, the next step is

etching deep separation trenches between adjacent emitters down to the substrate. These

deep trenches define the aforementioned chip width (note: different from stripe width

)

and serve the purpose of isolating each emitter electrically and optically, which is especially

important in laser bars to suppress undesired lasing along the lateral axis. This is followed by

selective deposition of a Si

isolation layer to cover the exposed layers within the etched

trenches and avoid the possibility of short circuits occurring during subsequent processing

or packaging steps. Metal layers are then selectively deposited over the unimplanted contact

windows, thereby forming an ohmic contact with the p

-GaAs contact layer, as mentioned

above. The thickness of the p-side metallization is gradually increased up to a few

µm

using

a combination of evaporation and electroplating, with the purpose of providing homogenous

current injection and efficient heat extraction, and enabling subsequent soldering (for p-down

mounting) while mechanically shielding the semiconductor surface. With p-side processing

complete, the final processing steps are substrate thinning (down to

∼

130

µm

) followed by

metallization to form the n-side contact, as mentioned above. Since substrate doping is not as

high as the p

-contact layer, an adapted metallization sequence (including AuGe) is deposited

on the n-side, that is subsequently alloyed with GaAs using rapid thermal annealing to ensure

ohmic contact formation. Further metal layers are deposited (using evaporation), ending with

a relatively thick Au layer (few hundred

) that enables subsequent wire bonding to the

2. Research Methods and Techniques

n-substrate

n-cladding

n-waveguide

p-waveguide

active zone

WHe+ ion implant

p-cladding

p-contact

n-metallization

Si3N4 isolation

p-metallization

separation

trench

Figure 2.3: Schematic transverse cross section of two adjacent gain-guided (GG) BAL emitters at

the conclusion of the wafer process, indicating the outcome of each processing step in relation to

the vertical layer structure, as well as the stripe width (

), current path and output laser beam

corresponding to each emitter.

n-side (for p-down mounting). The final configuration of two adjacent GG BAL emitters at

the end of the wafer process is schematically shown in Fig. 2.3, illustrating the outcome of

each of the aforementioned processing steps.

With the conclusion of on-wafer BAL processing, the remaining steps have the purpose

of transforming said BALs into packaged chips for testing and characterization. First, the

aforementioned bars are cleaved out of the processed wafers, thereby defining the resonator

length (

) of the BALs, as shown in Fig. 2.4(a) for a bar with

= 4

(and

∼

total

width). Following FBH procedure at the time, bar cleaving was carried out in air [46]; however,

a recent FBH study has shown improved reliability (at a different

) by cleaving in ultra-high

vacuum [47]. Bar cleaving exposes the front and rear facets (resonator mirrors) of the BALs,

which have to be prepared for high-power laser emission. First, cleaving in air necessitates

a facet cleaning step using atomic hydrogen irradiation, which is then followed by in situ

epitaxial deposition of a ZnSe passivation layer on the clean facets [46]. These steps improve

facet stability, which is especially important at the light-emitting front facet which experiences

the highest optical power density and heat levels. Facet passivation is thus crucial for realizing

reliable high-power BALs, as it increases the threshold of catastrophic optical mirror damage

(COMD), thus reducing the probability of device failure. The next step is facet coating to set

the front- and rear-facet reflectivites (

and

, respectively). For the light-emitting front

facet,

= 1% is realized by depositing a single Al

layer as anti-reflection coating. For the

rear facet,

= 98% is realized by depositing a sequence of alternating SiO

and Ta

layers

as high-reflection coating [5,7].

After facet passivation and coating, the BAL chips are finally mounted and assembled into

standard packages, with customized variants for different chip configurations and geometries.

In general, the purpose of these packages is enabling the testing and characterization of

high-power BALs by providing isolated electrical connections to both contacts, as well as a

mechanism for efficient heat extraction to enable temperature regulation (i.e. as a heat sink).

2.3 Characterization techniques and measurement setups

(a) (b)

Figure 2.4: Photographs of: (a) a bar of adjacent BAL emitters after cleaving, with

∼

total width and

= 4

, shown in relation to a 1 euro-cent coin for scale, and (b) a BAL

single-emitter (SE) chip, with 500

µm

chip width and

= 4

, mounted in p-down configuration

on a 4

-long screening submount (SSM), with bond wires connecting the n-side of the SE chip

to isolated bond pads on both sides of the SSM. (©FBH)

As mentioned above, the primary test devices used in this work are SE chips with 500

µm

chip

width and

= 4

, so this discussion focuses on their mounting and packaging [8,24,48].

First, each 500

µm

-wide SE is separated from the

∼

-wide bar (Fig. 2.4(a)) by cleaving

along the deep separation trenches. The SE is then mounted, with its p-side facing downwards

(i.e. p-down configuration), onto a so-called screening submount (SSM) with the same length

), as shown in Fig. 2.4(b). The SSM consists of a base, mostly made out of expansion-

matched CuW with high thermal conductivity, and two bond pads, with ceramic electrically

isolating them from the base. The p-contact of the SE is soldered using AuSn to the SSM

base, followed by wire bonding of the upward-facing n-contact to the bond pads. Prior to

testing, the assembled SSM is clamped with a specific torque to a standard measurement

fixture (made of gold-plated copper), that is specifically customized to the dimensions of 4

SSMs. This fixture enables simple electrical connections to both chip contacts for supplying

current and measuring voltage, and additionally includes a built-in temperature sensor that

comes in direct contact with the rear side of the SSM, and thus in close proximity to the rear

facet of the BAL chip. Therefore, the reading from this sensor, herein referred to as heat-sink

temperature (

THS

), represents a relatively good estimate of the internal temperature of the

BAL, thus enabling highly effective temperature regulation for high-power operation.

2.3 Characterization techniques and measurement setups

Throughout this work, the standard characterization of BALs is carried out under continuous-

wave (CW) operation at 25

°C

, and involves a sequence of measurements, each characterizing

a different aspect of BAL performance. However, all the used measurement setups include

the same mounting and cooling configuration for the device under test, referring here to a

-long BAL SE, mounted on a SSM, in turn clamped to a customized measurement fixture

(see above). For testing, the fixture is bolted to a base plate with an attached Peltier element

(thermo-electric cooler), which is fixed to a water-cooled gold-plated copper block for heat

sinking. The temperature sensor inside the fixture is connected to a controller which regulates

2. Research Methods and Techniques

current supply to the Peltier element, thereby regulating the extraction of the generated heat

via thermal conduction (i.e. passive cooling) and maintaining THS at 25 °C[24,48,49].

As a first characterization step, the power-voltage-current (PUI) characteristics of the

device are measured. A four-terminal configuration is used to accurately measure

across

the device and eliminate resistance contributions from the rest of the circuit, while the

Popt

measurement uses a thermoelectric detector which is regularly calibrated against national

standards and has been shown using repeated measurements over multiple years to have

a standard error margin (precision limit) of

5% [10]. Using the measured

and

Popt

values,

ηE

can then be calculated at each

level. From the resulting PUI characteristics

(e.g. Fig. 3.1), different performance metrics are then extracted for further analysis.

ηE,peak

is simply the highest obtained value of

ηE

, and

Popt,max

is the highest measured

Popt

value,

typically corresponding to the highest applied bias current (

Imax

Ith

is calculated by applying

a linear fit between the points on the P-I curve corresponding to 5% and 25% of

Popt,max

, then

extrapolating it such that

Ith

is the intercept point with the x-axis (

Popt

= 0). Two different

P-I slope (

) parameters are extracted, namely

1and

2, representing the slope at low and

high current (and heat) levels, respectively. To calculate them, the P-I data points between

Ith

(0%

·Popt,max

) and

Imax

(100%

·Popt,max

) are divided, such that

1is the slope in the 10–55%

range and

2is the slope in the 55–100% range. Finally, a linear fit is applied to the U-I

curve beyond Ith, with its slope representing Rsand its extrapolated y-axis intercept (I= 0)

representing U0[48].

The next step is measuring the spectrum at varying

levels, typically matching those used

in the PUI measurement. For this measurement,

Popt

is collected inside an integrating sphere

and homogeneously dispersed over its inner surface, and an optical fiber is used to transmit a

fraction of

Popt

onto a grating spectrometer with 0

FWHM spectral resolution [24,48].

The measured spectrum is then used to extract the centroid wavelength (

λc

), defined as

the intensity-weighted mean of the spectrum, in addition to the spectral width. From these

measurements, a significant increase of

λc

is observed with increasing

, implying a proportional

increase of the active-zone temperature (

TAZ

), with a known (

-dependent) constant rate

of ∆

λ/

∆

T≈

nm/

Kat

λc≈

940

. As previously mentioned, GaAs-based BALs are

the most efficient of all light sources, but the

ηE,peak

of state-of-the-art devices is still in the

65–75% range, meaning that a significant portion of the input electrical power is lost as heat

generated within the device, that can be quantified at a given operating point by the dissipated

power

Pdiss

I·U−Popt

. As presented above, BALs are typically mounted on large metal

submounts and heat sinks to extract the generated heat, but this heat extraction process is

not ideal, as demonstrated by the increase in

λc

and

TAZ

inside the device, despite effectively

maintaining a constant

THS

at the rear side of the SSM, just outside the device (see above).

For a given BAL mounting configuration under given measurement conditions, heat extraction

is typically quantified in terms of thermal resistance (

Rth

), defined as

Rth

= ∆

TAZ/Pdiss

, with

∆

TAZ

TAZ −THS

representing the active-zone temperature increase. To calculate

Rth

λc

plotted as a function of

Pdiss

resulting in a roughly linear curve, whose slope is then divided

by the aforementioned constant ∆λ/∆Tfactor.

The next step is beam quality characterization by measuring the lateral near- and far-field

intensity profiles at

values corresponding to defined

Popt

levels. Following [24,48,50], a

2.3 Characterization techniques and measurement setups

telescopic lens arrangement is used to image the beam profiles onto a laterally-moving slit with

a photodetector behind it. In near-field configuration, the telescopic arrangement consists of

two lenses; a collimating lens followed by a focusing lens, leading to a magnified image of the

near-field profile produced at the detector plane. In far-field configuration, a third lens is added

between the focusing lens and the moving slit, enabling the projection of the angle-dependent

far-field profile onto the detector plane. After proper scaling and background subtraction,

the measured profiles are used to extract

W95%

and

θ95%

, which are then used to calculate

BPPlat

and

Blat

at each operating point. For analysis and comparison of different devices, the

obtained metrics are typically plotted as functions of

Popt

or ∆

TAZ

(see above). The latter is

preferred in this work, as it enables a fair comparison of lateral beam quality under similar

conditions, i.e. excluding the influence of

ηE

Rth

variation. Following [24,39,51], insight into

the factors regulating the lateral beam quality of each device can be obtained by analyzing

the development of

BPPlat

with increasing ∆

TAZ

, which typically follows a roughly linear

trend. Quoting the author’s work [52], this analysis is carried out “by applying linear fits to

the

BPPlat

values and using the simple empirical model

BPPlat

BPP0

Sth ·

∆

TAZ

. In

this model, the intercept term

BPP0

represents a background level, regulated by non-thermal

contributions such as process- or packaging-induced waveguiding, while the slope term

Sth

represents the impact of heat- and bias-dependent mechanisms.”

The final step is characterizing the polarization purity of the BAL output. To this end,

Popt,TE

and

Popt,TM

are measured and used to calculate

DoP

at defined operating points.

For these measurements, two successive lenses (fast- and slow-axis collimators) are used to

collimate the laser beam onto a polarizing beam-splitter (PBS) cube with an integrating

sphere behind it, in which the output

Popt

of the PBS cube is collected and measured using

an attached photodetector. Moreover, the PBS cube is placed on a motorized rotation stage

that controls its rotation angle around the propagation axis [24,48]. This setup enables the

evaluation of the measured

Popt

as a function of the rotation angle, with

Popt,TE

and

Popt,TM

as the measured values at rotation angles of 0

and 90

relative to the plane of the active zone,

respectively. As mentioned in sections 1.1 and 2.2, the BALs realized in this work (

λ≈

940

)

have a compressively-strained InGaAs QW, resulting in predominantly TE-polarized emission.

Therefore, as expected, their

Popt,TE

and

Popt,TM

are found to correspond to the maximum

and minimum values of Popt, measured over a full 180°rotation of the PBS cube.

Literature Review

Before proceeding to novel lateral designs, it is crucial to have an overview of the findings of

studies published over multiple decades, in which great efforts have been undertaken to identify

and minimize the various factors that limit broad-area diode laser (BAL) performance. This is

the aim of this chapter, which starts by presenting some of the best-performing realizations

from recent publications, thus establishing a baseline for state-of-the-art BAL performance

(section 3.1). Section 3.2 then describes some of the mechanisms which are known to negatively

affect BAL performance, in terms of electro-optical characteristics as well as lateral beam

quality. Finally, section 3.3 reviews some notable prior approaches to BAL lateral design,

indicating the benefits and drawbacks of each of them.

3.1 Performance of state-of-the-art devices

In this section, notable state-of-the-art BAL realizations operating in the

9xx nm

range

are reviewed, including the wavelength of interest for this work (i.e. 940

). This review is

limited to single emitters (SEs), mounted on passively-cooled heat sinks (p-side down) and

characterized under continuous-wave (CW) operation at

THS

= 25

°C

, thus matching the device

configuration and measurement conditions used for BAL testing in this work (see sections 2.2

and 2.3), whereas more extensive reviews can be found in the literature, e.g. [8–10,53]. In

addition to presenting some of the best results published by various research groups in recent

years, the latest results of standard BAL SEs developed at the Ferdinand-Braun-Institut

gGmbH (FBH) outside the scope of this work are also presented, which have been realized

using standard techniques (i.e. no advanced lateral structures). The performance of these

standard BALs, obtained from three recent publications, can subsequently be used as a baseline

for the novel devices realized in this work to be benchmarked against.

High-brightness BAL SEs with

= 4

and

= 90

µm

, operating at 940 and 955

have been demonstrated by researchers from JENOPTIK AG [26,54]. In their studies, SEs

were mounted p-side down on passively-cooled heat sinks, resulting in low

Rth

of 1

8 K

and were characterized at

THS

= 25

°C

. In 2012, highly efficient 940

SEs were reported,

having a peak efficiency (

ηE,peak

) of 70%, and

ηE

= 64% at

Popt

= 12 W. In terms of beam

quality, they exhibited

θ95%≈

at 8 W and 11

at 11

5 W [54]. Subsequently in 2013 [26],

3. Literature Review

Table 3.1: Key performance metrics of state-of-the-art

9xx nm

BAL single emitters (SEs),

mounted p-side down on passively-cooled heat sinks and characterized under continuous-wave

(CW) operation at THS = 25 °C, as published by various research groups in recent years.

Reference λ L W Popt,max ηE,peak

ηEθ95%Blat [at Popt]

(nm) (mm) (µm)[at Popt] [at Popt](W/(mm·mrad))

JENOPTIK 940 4 90 70% 64% [12 W]8.8°[8.5 W],

(2012–13) 11.1°[12.5 W]

[26,54] 955 4 90 74% 69% [12 W]

915 4 100 24 W 68% 62% [13 W]9°[12 W] 2.79 [12 W]

Optoenergy 915 6 100 60% [15 W]9°[16 W] 3.48 [16 W]

(2015–20) 915 4 150 28 W 68% 65% [17 W]

[55–59] 915 4 220 33 W 68% 60% [27 W]

975 4 220 >30 W 73.6% 69% [20 W]

IPG (2017) 976 4 100 23 W 73% 65% [16.5 W]

[60] 976 5.1 100 30.5 W

FBH 970 4 90 19 W 67% 3.0 [10 W]

(2019–21) 935 4 95 69% 65% [11.4 W]

[8,31,61,62] 940 4 186 71%

nominally identical 940

SEs exhibited similar results, with

θ95%≈

at 8

5 W and 11

at 12

5 W. In that work, a performance benchmark was also set for 955

SEs through the

use of an innovative epitaxial layer structure, resulting in low

= 14

mΩ

, low

Ith

= 237

and high

of up to 1

125 W

A, that is maintained up to high current levels. As a result, very

high conversion efficiency could be achieved, with a peak value (

ηE,peak

) of 74%, and

ηE

= 69%

at 12 W. High polarization purity was also demonstrated by these 955

SEs, achieving

DoP ∗= 97% at 12.5 W, corresponding to DoP = 98.5% (see section 1.1).

Researchers from Optoenergy Inc., a subsidiary of Fujikura Ltd., have demonstrated

incremental progress in SE performance over the years, specifically at 915

and 975

Their BALs are realized using variants of the asymmetric decoupled confinement heterostructure

(ADCH) as vertical (epitaxial) designs, and the self-aligned structure (SAS) laterally (see

section 3.3). The SEs were mounted p-side down on ceramic-base sub-mounts with

Rth

3–3.2 K/W, and characterized under CW operation at THS = 25 °C.

In 2015 [55,56], the Optoenergy group demonstrated a 915

SE with

= 4

and

= 100

µm

reaching a maximum

Popt

(

Popt,max

) of 24 W, while maintaining

ηE≥

60%

up to 13 W. At 12 W, it had

θ95%

= 9

and

BPPlat

= 4

mm·mrad

, which corresponds to

Blat ≈

79 W

(

mm·mrad

). An SE with a longer

) achieved higher brightness, with 9

and 4

mm·mrad

at 16 W, corresponding to

∼

48 W

(

mm·mrad

). Despite its higher

Ith

, it

showed slightly higher

ηE

at high current levels, maintaining 60% up to 15 W. Alternatively,

keeping

constant at 4

and increasing

to 150

µm

led to a more significant

ηE

increase,

with 60% maintained up to 18 W, as well as increasing

Popt,max

to 28 W. In 2017 [57], an

SE with the same dimensions (4

and 150

µm

) was used to demonstrate an enhancement

ηE

∼

4percentage points at 915

, achieved by optimizing the vertical structure. It

3.1 Performance of state-of-the-art devices

0 5 10 15 20 25

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Voltage U (V)

Current I (A)

Optical power Popt (W)

Conversion efficiency ηE (%)

λ = 970 nm, W = 90 µm, L = 4 mm

Rf = 1%, Rr = 98%, THS = 25°C

(a)

0 2 4 6 8 10 12 14 16

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

THS = 25°C

THS = 75°C

Voltage U (V)

Current I (A)

Optical power Popt (W)

λ = 935 nm, W = 100 µm, L = 4 mm

Γ ≈ 1%, Rf = 1%, Rr = 98%

Conversion efficiency ηE (%)

(b)

Figure 3.1: Voltage, optical power and conversion efficiency as functions of current under CW

operation for the following FBH-fabricated BAL SEs, grown using one-step epitaxy and processed

using standard techniques (

= 4

= 1%,

= 98%): (a) 970

SE with

= 90

µm

°C

(adapted from [61]), and (b) 935

SE with

= 100

µm

and a Γ

≈

1% vertical design at

25 °Cand 75 °C(adapted from [8,31]).

exhibited

ηE,peak

= 68% and maintained

ηE

= 65% up to 17 W. SEs with narrower and wider

(100, 180 and 220

µm

) all had the same

ηE,peak

(68%), with the 100

µm

variant maintaining

∼

62% up to 13 W and the 220

µm

variant maintaining 60% up to 27 W. Using this optimized

vertical structure,

Popt,max

levels of about 22.5, 26.5, 28 and 33 W were achieved by the SEs

with

= 100, 150, 180 and 220

µm

, respectively. Additionally, it was demonstrated in 2018

that these 915

SEs have very high polarization purity, with an average

DoP

of 98

4% and

an exemplary device maintaining

DoP ≈

99% up to 18 W, making them suitable for PBC

applications [25].

Analog to the progress at 915

, the Optoenergy group also demonstrated a

∼

4percentage-

point

ηE

improvement at 975

in 2019 by optimizing the vertical structure [58]. An SE

with

= 4

and

= 220

µm

achieved

ηE,peak

= 72

5%,

ηE

= 66

7% at 20 W, and

Popt,max >

30 W at 975

. Further tuning of the vertical structure allowed further progress in

2020 [59], increasing

ηE,peak

to 73

6% and

ηE

at 20 W to 69%. At roughly the same wavelength

(

λ≈

976

), researchers from IPG Photonics Corp. have demonstrated passively-cooled SEs

with

= 100

µm

using two vertical design variants [60]. The first variant, optimized for

high conversion efficiency, was realized as an SE with

= 4

, achieving

ηE,peak

= 73%

and maintaining

ηE≥

65% up to

∼

5 W. The second variant, optimized for high optical

power, achieved

Popt,max ≈

23 W from a 4

-long SE (

Rth

= 2

73 K

W) and

∼

5 W from

a5.1 mm-long SE (2.21 K/W).

Outside the scope of this work, which will focus on the lateral design, continuous efforts

are ongoing at the FBH to further develop the epitaxial (vertical) structure of BALs operating

in the 9xx

range. Recently-published results are summarized here for the best-performing

BALs from wafers grown using standard one-step epitaxy, which are then fabricated using

standard processing techniques into SEs, with

defined by selective shallow ion implantation

of the p-contact layer at the BAL surface (see section 2.2). Recent results have shown that even

without advanced lateral structures, improvements to

ηE

Popt,max

and

Blat

in CW-operated

SEs are enabled by enhancing and optimizing the vertical structure.

3. Literature Review

In one recent example [61], an exemplary 970

SE (

= 4

= 90

µm

), mounted p-

side down on a CuW submount (

THS

= 25

°C

Rth

= 2

. . .

3 K

W), has achieved

ηE,peak

= 67%

and

Popt,max

= 19 W, as shown in its PUI characteristics in Fig. 3.1(a). In terms of beam

quality, it achieved

Blat ≈

3 W

(

mm·mrad

)at 10 W, and using the empirical linear fit of

BPPlat

(see section 2.3), values of

BPP0

= 1

mm·mrad

and

Sth

= 0

mm·mrad/

Kwere

obtained. In another example [8,31], 935

SEs with

= 95

. . .

100

µm

and an otherwise

similar configuration were used to study the impact of vertical design (more specifically the

optical confinement factor (Γ), see section 2.1) on

Ith

and

(under pulsed operation), as well

ηE

(under CW operation), and their stability with increasing temperature. One exemplary

SE with a Γ

≈

5% vertical design had

Ith

= 650

= 1

16 W

Aand

ηE,peak

= 69%,

and maintained

ηE≥

65% up to

Popt

= 11

4 W. Another SE with increased Γ

≈

1%, whose

PUI characteristics under CW operation are shown in Fig. 3.1(b), achieved

Ith

= 520

= 1

10 W

Aand

ηE,peak

= 68% at

THS

= 25

°C

. Compared to the 0

5% variant, the 1%

variant had slightly reduced

ηE

(by less than 1 percentage point), but exhibited significantly

improved temperature stability, with

ηE≥

50% maintained up to 13 W at an elevated

THS

of 75

°C

. A follow-up study on 940

SEs with a wider stripe (

= 186

µm

) has shown

that the dependence of

ηE

on the asymmetry between

and

is stronger for low-Γvertical

designs [62]. SEs with different Γand

combinations were characterized, achieving

ηE,peak

values between 62 and 71%, with the most efficient variant having Γ

≈

5%,

= 3% and

Rr= 98%.

3.2 Limiting factors to device performance

After giving an overview of the state of the art in the previous section, the next step is to review

the most important mechanisms that limit BAL performance, both in terms of electro-optical

characteristics as well as lateral beam quality. Studies have been conducted over many years,

involving both simulations and experiments, to identify these limiting factors and gain a better

understanding of the mechanisms behind them, as reviewed e.g. in [10,12,13,24,39]. This has

enabled the subsequent development of novel BAL designs to tackle these limits and eliminate

or minimize their effects, thereby enabling significant improvements in BAL performance.

These limiting factors can be roughly divided into two categories: thermal and non-thermal

mechanisms.

3.2.1 Thermal mechanisms

Thermal performance-limiting mechanisms are connected to the active-zone temperature

increase (∆

TAZ

) due to the heat generated during BAL operation. As detailed in section 2.3,

this self-heating is a consequence of non-ideal power conversion, i.e.

ηE

Popt/

(

I·U

)

100%,

and non-ideal heat extraction, i.e.

Rth >

0, leading to ∆

TAZ

Rth ·

(

I·U−Popt

)

0, that

increases with increasing current level.

One of these mechanisms is thermal roll-over, which refers to the degradation of the

external differential quantum efficiency (

ηd

) and the directly proportional P-I slope (

) at

higher current levels, therefore limiting the

Popt,max

achievable by a BAL, as observed e.g. in

Fig. 3.1(a). Thermal roll-over is caused by an increase in

αi

and a reduction of the internal

3.2 Limiting factors to device performance

differential quantum efficiency (

ηi

) at higher temperatures, corresponding to higher photon

and carrier losses [8,31]. As temperature increases,

αi

inherently becomes higher as a result

of the temperature dependence of free carrier absorption in the QW and its surrounding

waveguide layers [8,31,63], which generally dominates

αi

as mentioned in section 2.1. This

can be represented in equation 2.2 by temperature-dependent free carrier absorption cross

sections for electrons and holes (σn(T)and σp(T), respectively), following [8,31]. In addition

to that, the material gain (

) becomes lower with increasing temperature due to increased

quasi-Fermi level separation [31,64], which results in higher carrier density becoming necessary

to compensate the losses and maintain lasing (i.e. carrier non-pinning). This in turn leads to

higher carrier losses via non-radiative and spontaneous recombination as well as leakage, thus

reducing

ηi

. In case of elevated operating temperatures (i.e high

THS

), the

αi

increase and

reduction also mean that higher carrier density is needed to reach

gth

, corresponding to an

increase in Ith, which can also limit Popt,max.

Another important mechanism is thermal lensing; a heat-dependent lateral waveguiding

mechanism that strongly limits the lateral brightness of BALs. Thermal lensing has been

studied intensively, and has been shown using both simulations and experiments to be a

dominant cause of beam quality degradation in high-power BAL operation [50,65–67]. The

injection of current under the laser stripe leads to a local temperature increase, caused by

Joule heating, non-radiative recombination and optical absorption (see section 5.2). With

increasing current, this local current-induced heating becomes stronger, and a temperature

gradient arises between the central and outer regions of the device. This in turn gives rise to a

lateral refractive index step, since refractive index is directly proportional to temperature with

dn/dT

factor of about 2

−4

−1

in typical GaAs-based structures, which results in an

effective refractive index step (∆

neff

) on the order of +10

−3

[65,68]. This thermally-induced

index step leads to stronger lateral waveguiding within the BAL, thereby inducing a lensing

effect that significantly alters the lateral mode guiding behavior. The stronger waveguiding

broadens the far-field (FF) angle of each guided mode, and in addition, enables the guiding of

an increasing number of higher-order lateral modes having wider FF angles, as they become

more strongly confined leading to narrower intensity profiles and better overlap with the

pumped central region. The resulting strong broadening of the FF angle (i.e.

θ95%

increase)

with increasing thermal lensing is commonly referred to as thermal far-field blooming [66,67].

In terms of the near field (NF), the trend with increasing thermal lensing is not as clear. As

mentioned above, while the thermally-induced waveguiding narrows the intensity profile (i.e.

reduces the NF width) of each individual guided mode, it simultaneously enables the guiding of

higher-order modes with broader NF widths as they become more strongly confined [50,67,69].

Additionally, as current increases, some lower-order modes have been observed to develop

additional side peaks that end up broadening their modal

W95%

[50]. For a typical BAL

with highly asymmetric facet reflectivities (see section 1.1), it has been shown in [69,70] that

W95%

initially remains roughly constant with increasing current, as the increasing number of

modes (broadening NF) is counteracted by the stronger confinement (narrowing NF). However,

beyond a certain current level, clear differences develop between the low-reflectivity front facet

and the high-reflectivity rear facet, resulting from strong longitudinal temperature variation

(LTV) which is associated with the asymmetric gain and intensity profiles along the resonator.

3. Literature Review

n-substrate

n-cladding

n-waveguide

p-waveguide

active zone

Wshallow ion implant

p-cladding

p-contact

(a)

-30 -20 -10 0 10 20 30

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Carrier density (× 1018 cm-3)

Lateral position (µm)

Current density

(kA/cm2)

1.2

3.0

W = 50 µm

(b)

Figure 3.2: (a) Schematic transverse cross section of a standard gain-guided (GG) broad-area

diode laser with stripe width

, defined using shallow ion implantation. The current path is

indicated to demonstrate lateral current spreading, and (b) simulated carrier density within the

active zone as a function of lateral position, demonstrating lateral carrier accumulation (LCA)

with increasing current density (adapted from Piprek & Simon Li, 2013 [71]).

With significantly higher temperature at the front facet, it experiences much stronger thermal

lensing, resulting in

W95%

narrowing and

θ95%

broadening, and vice versa at the rear facet.

Although the overall beam quality (

BPPlat

) is shown to remain comparable at the two facets,

a significant

BPPlat

disadvantage is found upon comparison to a similar BAL with symmetric

facet reflectivites [39,70]. Moreover, LTV is associated with a non-thermal mechanism that

can reduce

ηd

, as explained in the next section. To sum up, it has been shown in many studies

that with increasing current and heat levels in BALs, thermal lensing (in the presence of LTV)

causes a significant

BPPlat

increase (i.e. beam quality deterioration), corresponding primarily

to strong blooming of the FF angle.

3.2.2 Non-thermal mechanisms

In addition to the aforementioned thermal mechanisms, BAL performance can also be

significantly limited by various non-thermal mechanisms, which are not linked to self-heating,

but rather to optical gain/loss and carrier profiles, as well as mechanical strain introduced

during processing and packaging.

One such mechanism is lateral current spreading, referring to the electrical pumping of

a wider section of the active zone than the nominal stripe width (

) as a result of two-

dimensional current flow and carrier drift and diffusion between the defined contact stripe and

the active zone. This is demonstrated in Fig. 3.2(a) via the blue arrows, indicating that the

lateral current profile at the active zone is significantly broader than

due to the lateral

component of current flow, which arises due to the finite sheet resistance of the epitaxial layers.

It has been estimated via simulation and experiment that lateral current spreading can be a

limiting factor to

ηd

and the proportional

[72,73]. As bias current increases above threshold,

current spreading leads to more carriers injected into the regions outside the stripe with

non-pinned Fermi levels. The poor overlap between the carrier density and optical intensity

3.2 Limiting factors to device performance

profiles leads to an accumulation of carriers outside the stripe which do not contribute to lasing.

This current loss mechanism was estimated to reduce the internal differential efficiency

ηi

14–18% [72], which in turn leads to reduced

ηd

and

. In addition, it has been demonstrated

in [74] that lateral current spreading strongly increases

Ith

, as a result of increased transparency

current density

Jtr

. In that study, the current loss at threshold due to lateral current spreading

is estimated using a simple empirical method, in which BALs with a constant

and varying

are characterized, their measured

Ith

values are plotted as a function of

, and a linear fit

of the values is extrapolated to intercept with the y-axis (

= 0). The intercept point, which

is referred to here as

Ith,0

, represents an empirical estimate of the spreading current lost at

threshold. Using this method, it was demonstrated that by reducing lateral current spreading,

Ith,0

can be reduced by up to 88%, corresponding to a significant

Ith

reduction for BALs of

different dimensions. It is important to note that current spreading is strongly dependent on

the implemented lateral structure. For example, in Fig. 3.2(a), a standard gain-guided (GG)

BAL is shown, with its stripe defined using shallow ion implantation and otherwise no lateral

current confinement, thereby allowing strong current spreading. Different lateral structuring

techniques for current confinement have been implemented, which are reviewed in the next

section 3.3.

Another important non-thermal mechanism is spatial hole burning (SHB) along the lateral

and longitudinal axes of the BAL. SHB refers to the spatial carrier depletion and gain saturation

in sections of the active zone with the highest optical intensity and therefore highest stimulated

recombination rate. Carrier injection is subsequently increased in order to maintain fulfillment

of the lasing threshold condition, which leads to increased carrier density in other sections of the

active zone, resulting from the finite rate of carrier transport into the depleted sections due to

the finite conductivity of the epitaxial layers. Lateral SHB can be explained as follows: as bias

increases beyond threshold, the fundamental lateral mode with its single intensity peak depletes

carriers in the stripe center, leading to higher carrier density outside the center with better

overlap with the first-order mode (i.e. higher modal gain). The first-order mode eventually

reaches threshold and its modal intensity increases until carriers are depleted at its intensity

peaks and increase elsewhere, increasing the modal gain for higher-order modes that eventually

reach threshold, and so on [75,76]. Longitudinal SHB is also bias-dependent, and is especially

strong in BALs with long resonators and highly asymmetric facet reflectivities. With increasing

bias in such BALs, the longitudinal optical intensity profile becomes increasingly asymmetrical,

with high photon density at the low-reflectivity front facet and vice versa, which in turn leads

to an inhomogenous carrier density distribution, i.e. high carrier density at the high-reflectivity

rear facet and vice versa [63,77–81]. It has been shown in many studies that lateral and

longitudinal SHB are detrimental to BAL performance, as they contribute to power saturation

alongside the aforementioned thermal roll-over as well as other non-thermal mechanisms.

The increased carrier injection to compensate SHB leads to higher average carrier density

(i.e. carrier non-pinning), which increases carrier losses via spontaneous and non-radiative

recombination as well as internal optical losses, thereby reducing

[31,63,79–82]. Additionally,

SHB is associated with other mechanisms which degrade beam quality, as described in the

following.

3. Literature Review

Lateral carrier accumulation (LCA) is a further non-thermal performance-limiting

mechanism, which refers to pronounced peaks in the lateral carrier density profile within

the active zone near the edges of the BAL stripe. The peaks become more pronounced with

increasing current, because the mechanisms causing LCA are all bias-dependent, namely

lateral spatial hole burning, current crowding at the p-side contact edges, and lateral current

spreading [51,71,76]. As current increases, LCA leads to an increasingly non-uniform gain

profile, with higher modal gain for higher-order lateral modes at the expense of lower-order

ones. This favoring of higher-order modes, which typically exhibit stronger FF divergence as

well as wider NF profiles, is commonly referred to as non-thermal FF blooming, and results in

a significant reduction of the overall BAL beam quality (increase of

BPPlat

). In the earlier

discussion of thermal lensing (see subsection 3.2.1), it was mentioned that in BALs with highly

asymmetric facet reflectivites, LTV at higher current levels results in stronger thermal lensing

at the low-reflectivity front facet and thus smaller NF width. As W95%becomes significantly

narrower than the stripe width

, LCA arises in the outer sections of the stripe (towards

the edges), where optical intensity and stimulated recombination rate are lowest and carrier

density is therefore non-pinned [68,69,81]. As previously discussed, these accumulated carriers

do not contribute to lasing (lower ηi), thereby limiting ηdand S.

In addition to the aforementioned non-thermal mechanisms which are all bias-dependent,

there are other mechanisms, which are temperature and bias-independent, that can also

limit BAL performance. For example, the lateral waveguiding introduced by etching index-

guiding trenches can significantly limit beam quality. A detailed discussion of the benefits and

limitations of index-guiding trenches is provided in the next section 3.3. Another example

is mechanical strain, which is typically induced during processing (e.g. trench etching) or

mounting (e.g. soldering to submount) and tends to accumulate at mechanical edges. This

induced strain limits

DoP

and can also introduce parasitic lateral waveguiding [24]. It is

important to note that the impact of these temperature and bias-independent mechanisms on

beam quality can be observed through the change in background level

BPP0

of the empirical

linear fit of BPPlat (see section 2.3).

3.3

Previous lateral design approaches: benefits and limitations

In the previous section, lateral current spreading and lateral carrier accumulation (LCA)

were identified as non-thermal mechanisms that can lead to significant deterioration of BAL

performance. More specifically, current spreading causes

ηd

reduction and

Ith

increase, while

LCA causes NF and FF broadening and thus higher

BPPlat

. These detrimental effects can be

minimized by implementing lateral structuring techniques to alter the lateral configuration

of BALs, thereby ensuring the central confinement of current and/or charge carriers under

the laser stripe. In earlier studies over many years, a variety of lateral structuring approaches

have been developed and implemented, with each approach having benefits and drawbacks.

A review of some notable approaches was included in a publication by the author of this

dissertation [83], and is adapted and expanded upon here.

3.3 Previous lateral design approaches: benefits and limitations

n-substrate

n-cladding

p-contact

deep ion implant

n-waveguide

p-waveguide

active zone

p-cladding

(a)

n-substrate

n-cladding

n-waveguide

p-contact

p-cladding

p-waveguide

active zone

shallow ion implant

index

trench

(b)

Figure 3.3: Schematic transverse cross sections of broad-area diode lasers with the following

lateral structuring techniques: (a) high-energy deep ion implantation [51,84], and (b) etching of

index-guiding trenches [24]. On each diagram, the stripe width (

) and current path are indicated.

High-energy deep ion implantation

One of the most important techniques for current and carrier confinement is high-energy deep

ion implantation of the outer regions (i.e. outside the laser stripe), as schematically shown

in Fig. 3.3(a). The implanted regions have strongly reduced electrical conductivity, which

prevents the lateral flow of current into the outer regions. In addition, the implantation

introduces point defects that act as rapid non-radiative recombination centers for carriers that

laterally diffuse outside the stripe, thus preventing their accumulation at the stripe edges [51].

Quoting the author’s work [83], “implantation profiles that reach the n-doped side of the BAL,

i.e. through the active zone, ... result in reduced

W95%

(10%) and

θ95%

(27%), but

ηE

and

Popt,max

are strongly compromised [51]. A tailored implantation profile, with the implant

halted above the active zone (Fig. 3.3(a)), has demonstrated a significant reduction of

BPPlat

with minimal reduction of ηE[84].”

Index-guiding trenches

Another technique is the etching of index-guiding trenches [24], as demonstrated in Fig. 3.3(b).

Besides introducing a refractive index step that leads to stronger lateral waveguiding, the

trenches also confine carriers to the device center, especially if the residual layer thickness

between the active zone and the bottom of the trenches is small. It has been shown in [24] that

the improved overlap between the lateral optical and carrier profiles enhances

ηE

∼

2%, but

other performance aspects are compromised. The trenches induce strong built-in waveguiding

which increases

BPP0

by at least 1

mm·mrad

, and they also induce strain fields that reduce

DoP

and can further increase

BPPlat

. On the other hand, the index guiding makes the beam

quality less sensitive to thermal lensing (i.e. lower

Sth

; see section 2.3), which could counteract

the other effects and result in overall lower BPPlat at high Popt and ∆TAZ levels.

Real-index guided self-aligned structure (RISAS)

The aforementioned techniques are realized by adding one or more steps to the standard

process carried out after conventional one-step epitaxial wafer growth. However, other lateral

3. Literature Review

n-substrate

n-cladding

n-waveguide

p-contact

n-current block (n↓)

p-cladding

p-waveguide (n↑)

active zone

dres

(a)

n-substrate

n-cladding

n-waveguide

p-contact (GaAs)

n-current block

(GaAs)

p-cladding

p-waveguide

dres

active zone

(b)

Figure 3.4: Schematic transverse cross sections of broad-area diode lasers with the following

lateral structuring techniques: (a) real-index guided self-aligned structure (RISAS) [85–87], and (b)

self-aligned structure (SAS) [25,55–59]. On each diagram, the stripe width (

), residual thickness

(dres), regrowth interface (dashed), and current path are indicated.

confinement techniques which utilize two-step epitaxial growth have also been developed

and realized. In these techniques, the additional processing steps for lateral structuring are

carried out between the two growth steps (i.e. before epitaxial regrowth). Quoting the author’s

work [83], “one such technique is the real-index guided self-aligned structure (RISAS), which

was developed to enhance the performance of single-mode high-power lasers and overcome

the limitations of ridge waveguide diode lasers [85–87]. In this structure, a sequence of layers,

one of which is n-doped, are grown within the p-doped waveguide layer of the diode laser,

resulting in a current-blocking reverse-biased junction in close proximity to the active zone. An

intermediate etch step between two growth stages removes the n-doped layer from the central

stripe, and since the n-doped layer is designed to have a lower refractive index than the regrown

layers, the final structure exhibits lateral index guiding and current confinement.” A schematic

diagram of the RISAS structure is provided in Fig. 3.4(a). “Despite the complex growth

process, RISAS diode lasers have demonstrated low

Ith

and high

ηE

and

Popt

= 1

and

varying between 3 and 50

µm

. However, the strong lateral index guiding in the RISAS

would significantly increase

BPPlat

, making it unsuitable for realizing high-brightness BALs”.

Self-aligned structure (SAS)

This issue is eliminated in the self-aligned structure (SAS), which has recently been utilized

to realize state-of-the-art high-brightness BALs [25,55–59], as presented in section 3.1. In

these realizations, it was demonstrated that SAS BALs can simultaneously achieve high

ηE

low

BPPlat

and high

DoP

up to high

Popt

levels. Similar to the aforementioned RISAS, the

SAS also involves an n-doped layer grown within the p-doped side of the diode laser, which is

selectively etched in the center between two epitaxial growth steps. Current flow in the outer

regions is blocked by the reverse-biased p-n-junction, and is thereby confined to the etched

aperture corresponding to the central stripe. The difference, however, is that in the SAS,

the blocking layer is made of n-GaAs and is grown near the bottom of the p-GaAs contact

layer, as shown in Fig. 3.4(b). This means that there is no refractive index difference between

the blocking layer and the regrown material surrounding it, and no built-in lateral effective

3.3 Previous lateral design approaches: benefits and limitations

refractive index step is created (∆

neff

= 0), thus avoiding the beam quality degradation

associated with index guiding. It is clear that the SAS approach reduces the mechanical

flatness of the BAL surface after regrowth, with a step height roughly corresponding to

the thickness of the blocking layer. However, this height (given in [25] as 600

) is small

compared to that of a typical ridge waveguide laser, meaning that strain fields induced at the

mechanical edges upon soldering are less of an issue in SAS devices. Moreover, the buried

current-blocking layer allows the regrowth of a thicker contact layer on top of it with no added

current spreading, which limits the overlap of any strain fields with the optical field. It was

experimentally demonstrated that SAS BALs with different mounting configurations maintain

very high

DoP

up to high bias levels, proving that mechanical strain that is potentially induced

at the surface does not significantly affect polarization purity [25]. As mentioned, recent SAS

realizations have shown positive results, with incremental performance enhancements and no

significant drawbacks. These enhancements are nonetheless limited by the degree of current

and carrier confinement under the stripe, which is dependent on the proximity of the structured

current block to the active zone, which is herein defined as the residual thickness (

dres

). In the

aforementioned realizations, the n-GaAs blocking layer is grown within the p-GaAs contact

layer, meaning that

dres

is by definition larger than the combined thicknesses of the p-AlGaAs

cladding and waveguide layers. With the cladding layer thickness given as 1

µm

in [58], it is

clear that

dres

is relatively high. It can thus be reasonably expected that if

dres

is minimized,

further performance benefits can be obtained from the SAS.

Buried mesa (BM) structure

The buried mesa (BM) structure, which is shown in Fig. 3.5(a), is another technique based

on two-step epitaxial growth. This structure simultaneously introduces lateral electrical and

optical confinement by etching the active zone outside the stripe after a first growth step,

followed by regrowth of the p-side over the structured active zone [88,89]. Although this

structure does not include a current block in the outer regions like the aforementioned SAS

and RISAS, it still demonstrates effective central confinement of current and carriers. This

results from the p-i-n diode in the center (with the QW as the intrinsic layer) having a lower

turn-on voltage than the p-n diode outside the stripe, leading to current preferentially flowing

through the center. In addition, lateral carrier diffusion is suppressed by the energy barrier

between the QW (central) and the adjacent regrown p-waveguide layers (outer) with higher

band-gap energy. The BM structure also introduces strong built-in lateral index guiding, as

etching the active zone outside the stripe results in a significant ∆

neff

of 3

−3

. It has

been demonstrated in [88] that in comparison to standard GG BALs (with the active zone

unetched) from the same wafers, BM BALs can exhibit lower

Ith

(

∼

15%) and higher

ηd

(

∼

5%),

resulting in higher

Popt

and

ηE

at a given current level. They also maintain high

DoP

, which

is favorable compared to BALs where index guiding is introduced by etching trenches. On

the other hand, the BM structure results in degraded beam quality, as the built-in index step

allows the guiding of a larger number of higher-order lateral modes, which leads to BM BALs

having broader NF widths and FF angles and thus higher BPPlat.

3. Literature Review

n-substrate

n-cladding

n-waveguide

p-contact

p-cladding

p-waveguide

active zone

(a)

n-substrate

n-cladding

n-waveguide

p-contact

heavy ion implant

p-cladding

p-waveguide

active zone

(b)

Figure 3.5: Schematic transverse cross sections of broad-area diode lasers with the following

lateral structuring techniques: (a) buried mesa (BM) structure [88,89], and (b) lateral buried

implant (LBI) structure [90–92]. On each diagram, the stripe width (

), regrowth interface

(dashed) and current path are indicated.

Lateral buried implantation (LBI) structure

A further confinement technique based on two-step epitaxial growth is the lateral buried

implantation (LBI) structure, alternatively referred to as the buried regrown implant structure

(BRIS), which is demonstrated in Fig. 3.5(b). In this structure, heavy ions such as O

or Si

are selectively implanted outside the central stripe between two growth steps. This implant

has an insulating effect, leading to current blocking in the implanted regions [90–92]. Typical

implant insulation using light ions such as He

or H

cannot be used here, because the

implant-induced lattice defects that give the insulating effect would be removed during the

subsequent epitaxial regrowth that acts as a high-temperature annealing. O and Si, on the other

hand, become incorporated within the lattice upon implantation, thus achieving insulation by

changing the chemical properties of the material. For example, Si can change the doping of

GaAs/AlGaAs from p- to n-type, thus creating a reverse-biased junction within the p-side

or shifting the position of the p-n-junction away from the QW, while oxygen can neutralize

p-doping, introduce deep levels within the band gap, or reduce hole mobility. Compared to the

aforementioned structuring approaches involving intermediate etching followed by regrowth

on a patterned surface, the LBI offers a lower degree of technological complexity, by using

selective implantation of the surface without altering its topology. In one design variant, the

implant-regrowth interface is located near the bottom of the p-contact layer, i.e. implantation

through the p-cladding, as shown in Fig. 3.5(b). LBI BALs of this variant (mounted p-up) have

been shown in [91] to exhibit lower

Ith

(up to 12%) and higher

ηd

(up to 15%) than GG BALs

from the same wafers (two-step growth with no intermediate implant), which in turn exhibited

similar performance to standard GG BALs from one-step epitaxial wafers. In terms of beam

quality, the

BPPlat

values exhibited by LBI BALs were lower than their GG counterparts, but

still comparable to values that can be obtained using simpler techniques [91]. An optimized

realization of this variant has recently been presented, with BALs having a thicker p-contact

layer and mounted p-down [92]. Relative to GG BALs from the same wafers, the

Ith

and

BPPlat

benefits of LBI BALs could be reproduced, but

(and

ηd

) were roughly unchanged.

3.3 Previous lateral design approaches: benefits and limitations

Nonetheless, LBI BALs demonstrated increased

ηE,peak

(

∼

1%) and clearly enhanced

Blat

over

the whole

Popt

range. A second design variant was also realized in the earlier study [91],

with the implant-regrowth interface located within the p-waveguide layer, i.e. implantation

through or very close to the active zone. For LBI BALs of the second variant (mounted

p-up),

Ith

and

ηd

were slightly better than GG BALs from the same wafers, but worse than

standard GG BALs from one-step epitaxial wafers, which is likely caused by contamination

and defects at the regrowth interface as well as implant-generated non-radiative recombination

centers in close proximity to the active zone. This variant demonstrated a more significant

BPPlat

enhancement than the first, resulting from stronger NF and/or FF narrowing, but at

the expense of reduced

ηE

, in a similar manner to the aforementioned BALs with deep ion

implantation through the active zone [51].

Enhanced Self-Aligned Lateral Structure

(eSAS)

In section 3.3, a review of notable BAL lateral structuring techniques that have been

implemented in previous studies is presented, highlighting the benefits and limitations of

each of them. In general, the purpose of these techniques is the lateral confinement of current

and charge carriers under the central BAL stripe, aiming to minimize lateral current spreading

and lateral carrier accumulation (LCA) and reduce their detrimental effects on the electro-optic

performance and beam quality of BALs. One of the techniques reviewed is the self-aligned

structure (SAS), which utilizes two-step epitaxial growth with an intermediate selective etching

step to obtain a structured n-doped layer within the p-doped side of the diode laser (see

Fig. 3.4(b)). With this configuration, a p-n-p layer sequence (including a current-blocking

reverse-biased p-n-junction) is created in the outer regions, and current flow is confined to

a central aperture, corresponding to the BAL stripe. As discussed in the review, promising

results have recently been presented using this structure, simultaneously demonstrating high

ηE

, low

BPPlat

and high

DoP

up to high

Popt

levels, thereby enabling the realization of

state-of-the-art high-brightness BALs.

A major part of this dissertation is thus dedicated to a detailed study of this structure,

including the optimization of every design aspect to develop an improved version, herein referred

to as the enhanced self-aligned structure (eSAS), aiming to obtain significant performance

benefits over BALs fabricated using standard techniques. This detailed study is presented in

this chapter, starting with the development of two novel eSAS design variants in section 4.1,

including device modeling and simulation results to optimize the different design aspects and

estimate performance benefits. These two eSAS variants have been implemented as part of this

work, with each of them requiring modifications to the standard wafer process. Sections 4.2

and 4.3 thus focus on the realization of the two variants, respectively, including trial processes

and quality control tests to verify the correct implementation of the intended designs. In

section 4.4, mounted devices of both eSAS variants are characterized, along with gain-guided

reference devices processed on the same wafers for a fair comparison, and the measurement

results are evaluated and analyzed in detail, concluding with a discussion of the findings and

an outlook for the eSAS structure.

4. Enhanced Self-Aligned Lateral Structure (eSAS)

The work presented in this chapter has been presented in multiple publications by the

author of this dissertation [52,83,93–95], and is adapted and expanded upon here.

4.1 Device design and simulation results

The design and development of the eSAS variants and their expected benefits are presented in

this section. It starts with the study and optimization of various design aspects, including the

vertical (epitaxial layer) structure, the layer(s) of the current-blocking structure (i.e. materials,

thicknesses and doping concentrations), as well as the vertical position of the blocking structure

within the p-side, represented by the residual thickness (

dres

) between the blocking structure

and the active zone. Subsequently, simulations are carried out to estimate the performance

benefits of the proposed optimized designs compared to standard gain-guided devices, before

proceeding to design realization. A description of the modeling and simulation tools used here

is provided in section 2.1.

4.1.1 Vertical (epitaxial) layer structure

The first design step is selecting a high-performance vertical structure for the epitaxial wafers,

that is well-suited for realizing the eSAS lateral structure. A variant of the extreme-triple-

asymmetric (ETAS) design is selected, which is designed for single vertical mode operation,

i.e. the fundamental mode (mode 0), at

λ≈

940

using standard techniques. The ETAS

design concept and development are presented in detail in [8,31,96], and are summarized

here. Quoting the author’s work [93], “the ETAS design is characterized by the extreme

asymmetry between the p- and n-doped sides of the diode laser, in terms of the thicknesses

and compositions of the waveguide, cladding and graded-index (GRIN) layers adjacent to the

active zone.” Quoting the author’s work [52], “the ETAS structure enables highly efficient BAL

performance up to high current levels, by combining thin p-side waveguide and cladding layers

with high optical confinement and modal gain. The thin layers ensure low series resistance,

optical absorption and carrier leakage, while the high modal gain reduces

Ith

and thermal

power saturation, thus resulting in high

ηE

at high

Popt

.” The ETAS variant used in this

Table 4.1: Simplified epitaxial layer structure of the extreme-triple-asymmetric (ETAS) vertical

design variant used in this work.

Number Name Material Doping Thickness

(8) p-contact GaAs p+(very high) thin

(7) p-sub-contact GaAs p (high) thick

(6) p-cladding Al0.8GaAs p (moderate) ∼600 nm

(5) p-waveguide AlGaAs p (low) ∼180 nm

(4) active zone

(3) n-waveguide AlGaAs n (low) thick

(2) n-cladding AlGaAs n (moderate)

(1) n-buffer GaAs n (high)

n-substrate GaAs

4.1 Device design and simulation results

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

(7)

(6)(5)

(4)

Refractive index n

Vertical position (µm)

(3)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized intensity

Figure 4.1: Simulated refractive index and normalized optical intensity of the fundamental

vertical mode as functions of vertical position along the extreme-triple-asymmetric (ETAS) layer

structure variant used in this work. The blue numbers and dashed lines indicate the different

layers, corresponding to table 4.1 (adapted from [83]).

work has an optical confinement factor Γ

≈

1% and internal optical loss

αi≈

cm−1

[83],

calculated using QIP2 as described in section 2.1, and is similar to the 935

FBH design

(also with Γ≈1%), whose measurement results are shown in Fig. 3.1(b).

A simplified epitaxial layer structure of the used ETAS variant is presented in table 4.1.

It has thin p-waveguide and p-cladding layers (both made of AlGaAs), having a combined

thickness

800

. On top of these thin p-AlGaAs layers, a relatively thick low-resistance

p-GaAs sub-contact layer is grown, to ensure the p-side has sufficient thickness to shield the

active zone from mechanical damage and strain during processing, handling and soldering. The

refractive index and fundamental mode intensity profiles are plotted in Fig. 4.1, showing the

mode strongly shifted towards the n-side, which mainly results from the very thin p-waveguide

layer and the high Al content (80%) of the p-cladding layer. In addition to the aforementioned

benefits of reduced series resistance and optical absorption, the thin p-AlGaAs layers and

shifted mode profile make this design particularly suitable for realizing the eSAS lateral

structure. If the blocking structure is grown within the p-GaAs (sub-)contact layer (analog

to the SAS structure, see section 3.3), then the thin p-AlGaAs layers in this ETAS design

enable a significant reduction of

dres

compared to established SAS realizations (c.f. p-cladding

layer with 1

µm

thickness in [58]) [83]. Moreover, if even smaller

dres

can be achieved by

growing the blocking structure within the p-AlGaAs layers, then the impact of the blocking

structure on the effective refractive index of the fundamental mode (

neff,0

) is reduced as a

result of its shifted intensity profile. The lateral index step ∆

neff,0

, corresponding to undesired

lateral index guiding, can thus be minimized to avoid the degradation of beam quality [52]

(see sections 3.2 and 3.3). The dependence of ∆

neff,0

on the blocking structure is one of the

key lateral design aspects that are investigated in detail in the next subsections.

4. Enhanced Self-Aligned Lateral Structure (eSAS)

012345678

10-3

10-2

10-1

100

101

102

103

12345678 123456789

dblock = 60 nm

ND,block = 2×1018 cm-3

dblock = 60 nm

dblock (nm)

Current density (A/cm2)

Applied voltage (V)

(a) (b) (c)

ND,block = 2×1018 cm-3

ND,block (cm-3)

2×1018

1×1018

Applied voltage (V)

GaAs + InGaP

GaAs

Applied voltage (V)

Figure 4.2: Simulated current density as a function of applied voltage for eSAS-V1 p-n-p blocking

structure variants (

dres ≈

850

) with: (a) varying total thickness (

dblock

) at constant doping

concentration (

ND,block

), (b) varying

ND,block

at constant

dblock

, and (c) two n-doped blocking

layers (GaAs on top of InGaP) compared to one n-GaAs layer. In each case, the black solid line

corresponds to the selected variant (adapted from [83]).

4.1.2 eSAS first variant (V1): lateral structure design

After selecting the vertical structure, the next step is setting the design parameters of the

eSAS lateral structure. The current-blocking structure in the outer regions offers several

degrees of design freedom, including the materials, thicknesses and doping concentrations of

the blocking structure layers, as well as their vertical position within the p-side (i.e.

dres

Ideally, the blocking structure design should offer small

dres

to maximize lateral current

confinement, while also minimizing ∆

neff,0

to avoid beam quality degradation. Additionally,

strong current-blocking capability in the outer BAL regions should be ensured, while keeping

the total thickness of the blocking structure (

dblock

) as small as possible, in order to minimize

the mechanical step height at the BAL surface to avoid

DoP

degradation (see SAS review in

section 3.3), and also reduce the risk of defect formation during the epitaxial regrowth step

over the laterally-structured blocking layers. As previously mentioned, two eSAS variants have

been implemented as part of this work.

In the first variant (eSAS-V1) [83,93,94], the blocking structure is located near the bottom

of the highly p-doped GaAs sub-contact layer. As discussed in the previous subsection 4.1.1,

this is analog to established SAS realizations, but a significant

dres

reduction is enabled here

by the ETAS vertical structure. With the used ETAS variant,

dres

for eSAS-V1 has a value of

∼

850

, which roughly corresponds to half the total thickness of the p-side, meaning that

current spreading is eliminated through the top half of the p-side.

In established SAS realizations, current blocking was provided by a single n-GaAs layer,

surrounded by p-GaAs in a p-n-p configuration (see Fig. 3.4(b)). For eSAS-V1, this n-GaAs

layer is replaced by two n-doped layers: a GaAs layer on top of an InGaP layer, which is

beneficial for the intermediate etching step between the two epitaxial growth steps, in which

the blocking layers are selectively etched to create a central current aperture. The added

n-InGaP layer allows a highly-precise definition of the etching depth using wet chemical

etching, as InGaP acts as an etch-stop layer for the etching solution of GaAs and vice versa [88].

This combination of n-GaAs and n-InGaP blocking layers thus improves process control and

repeatability compared to the single-layer variant, and also compared to implantation-based

lateral designs (see section 3.3).

4.1 Device design and simulation results

n-buffer (GaAs) &

n-substrate (GaAs)

n-cladding (AlGaAs)

n-waveguide (AlGaAs)

p-waveguide (AlGaAs)

active zone

p+-contact (GaAs)

p-sub-contact (GaAs)

n-current block

dres

n-GaAs

n-InGaP

p-cladding (Al0.8GaAs)

Figure 4.3: Schematic transverse cross section of an eSAS-V1 BAL with a p-n-p current block

outside the central stripe, located near the bottom of the p-GaAs sub-contact layer. The stripe

width (

), residual thickness (

dres

), regrowth interface (dashed), and current path are indicated

on the diagram (adapted from [83,93]).

To estimate the current-blocking capability of a given blocking structure variant, WIAS-

TeSCA is used to numerically solve the one-dimensional drift-diffusion equation (see section 2.1)

and simulate the current-voltage (I-U) characteristics of the whole vertical structure including

the blocking layers. Representative examples are shown in Fig. 4.2, with the blocking capability

quantified here by the voltage corresponding to a current density of 10

−3

/cm2

(i.e. the

x-axis intercept), referred to as the turn-on voltage (

Uon

). Simulation results show that

Uon

is dependent on many factors: the materials, thicknesses (

dblock

) and doping concentration

(

ND,block

) of the blocking layers, as well as the material composition and doping concentration

of the surrounding p-side material. Figure 4.2(a) shows the dependence of

Uon

on the total

dblock

, with a 2:1 ratio maintained between the thicknesses of n-GaAs and n-InGaP and a

constant

ND,block

= 2

18 cm−3

for both layers. By increasing

dblock

from 30 to 60

Uon

is increased by about 4

5 V. Even higher

Uon

can be achieved by further increasing

dblock

, but

as previously mentioned, this is avoided to minimize step height at the surface and reduce

the risk of defect formation upon epitaxial regrowth. Similarly, a

Uon

increase of 4

1 V is

observed in Fig. 4.2(b) upon increasing

ND,block

from 1

to 2

18 cm−3

, at a constant

dblock

= 60

. A further increase of

ND,block

would result in even higher

Uon

, but n-doping

greater than 4–5

18 cm−3

is not easily realized, since at such high concentrations, the

dopant (Si) tends to self-compensate or form precipitates [97], which can lead to device failure.

In Fig. 4.2(c), another benefit of the two-layer blocking structure variant with the added

n-InGaP layer is demonstrated, in addition to the aforementioned etch depth precision. With

constant

dblock

and

ND,block

, the two-layer variant has higher

Uon

, as a result of InGaP having

a higher band-gap energy than GaAs. However, due to the small thickness of the InGaP layer

(20 nm), the benefit is minor, as Uon is only increased by 0.2 V.

The proposed configuration for the eSAS-V1 blocking structure is thus a p-n-p layer sequence

with

dblock

= 60

(40

n-GaAs and 20

n-InGaP) and

ND,block

= 2

18 cm−3

, located

near the bottom of the p-GaAs sub-contact layer (

dres ≈

850

), as shown in Fig. 4.3. For

4. Enhanced Self-Aligned Lateral Structure (eSAS)

1.5 2.0 2.5 3.0 3.5 4.0 4.5

3.0

3.2

3.4

3.6 (a) (b)

No blocking

Refractive index n

Vertical position (µm)

Blocking (V1)

∆neff,0 = 0

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Vertical position (µm)

0.0

0.2

0.4

0.6

0.8

1.0

Normalized intensity

Figure 4.4: Simulated refractive index and normalized optical intensity of the fundamental

vertical mode as functions of vertical position along the layer structure of an eSAS-V1 BAL in:

(a) the central aperture (no blocking), and (b) the outer blocking region, with the blue arrow

indicating the position of the blocking structure. The dashed lines indicate the effective refractive

index of the mode (

neff,0

) in each case, and the difference (∆

neff,0

) is given in the legend (adapted

from [83]).

this configuration, the simulation estimates

Uon

= 6

1 V, much higher than the BAL operating

voltage range, thus indicating very strong current-blocking capability.

To estimate the lateral waveguiding in the proposed eSAS-V1 configuration, QIP2 is used

to solve the waveguide equation and simulate the guided vertical mode(s) in the central and

outer regions, based on the refractive index profile of the layer structure (see section 2.1).

Figure 4.4 shows the refractive index and fundamental mode intensity profiles in each case,

indicating the position of the blocking layers within the vertical structure. It is observed that

although the n-InGaP blocking layer has a lower refractive index than the surrounding GaAs,

it has no spatial overlap with the mode profile. It therefore has no effect on

neff,0

in the outer

region, meaning that it does not induce a lateral index step (∆neff,0 = 0).

To sum up, in terms of the aforementioned blocking structure design criteria, the proposed

eSAS-V1 configuration combines relatively small

dres

(

∼

850

) with strong current blocking

(

Uon

= 6

1 V) using relatively thin blocking layers (

dblock

= 60

), without inducing undesired

lateral index guiding (∆neff,0 = 0).

4.1.3 eSAS second variant (V2): lateral structure design

In the second eSAS variant (eSAS-V2) [52,95], a further reduction of

dres

is obtained by growing

the blocking structure within the p-AlGaAs layers, in closer proximity to the active zone (see

table 4.1). Stronger current and carrier confinement is thus achieved, aiming to increase the

performance benefits of the eSAS structure. However, due to the fact that aluminium oxidizes

rapidly, the p-AlGaAs layers cannot be exposed to air between the two growth steps, especially

the cladding layer with high aluminium content (80%). Otherwise, aluminium oxide – an

electric insulator – would be formed within the current aperture, increasing series resistance

and degrading BAL performance. Higher process complexity is thus inevitable to enable the

lateral structuring of the eSAS-V2 blocking structure without exposing the underlying AlGaAs,

which is achieved here by introducing an in situ etching step (i.e. inside the MOVPE reactor),

as performed e.g. in [98].

4.1 Device design and simulation results

0 1 2 3 4 5 6 7 8 9 10

10-3

10-2

10-1

100

101

102

103

Current density (A/cm2)

Applied voltage (V)

Ref.

dres (nm)

150

300

(a)

140 160 180 200 220 240 260 280 300

-1x10-2

-8x10-3

-6x10-3

-4x10-3

-2x10-3

p-waveguide

Effective refractive index difference ∆neff,0

Residual thickness dres (nm)

p-cladding

(b)

Figure 4.5: Simulation results of eSAS-V2 p-n-p blocking structures (n-GaAs/n-InGaP,

dblock

ND,block

= 2

18 cm−3

) with varying

dres

, corresponding to a varying location within

the p-side waveguide and cladding layers, compared in terms of: (a) current density as a function

of applied voltage, and (b) effective refractive index difference of the fundamental mode (∆

neff,0

)

between the central aperture and outer blocking regions.

For the eSAS-V2 blocking structure design, the p-n-p configuration optimized for eSAS-V1

is used as a starting point, consisting of two n-doped current-blocking layers (n-GaAs on top

of n-InGaP) with

dblock

= 60

and

ND,block

= 2

18 cm−3

(see subsection 4.1.2). A thin

p-doped GaAs layer is added at the bottom of the blocking structure (i.e. grown before the

n-doped layers), which is essential for the aforementioned in situ etching step as detailed later

in section 4.3.

To optimize the vertical location of the blocking structure within the p-AlGaAs layers,

TeSCA and QIP2 are again used to simulate the current-blocking capability and lateral

waveguiding, respectively, with

dres

varied between 150 and 300

as shown in Fig. 4.5.

The simulation results in Fig. 4.5(a) demonstrate that

Uon

is strongly dependent on

dres

increasing from 1

1 V at 150

to 9 V at 300

. This is explained by the varying composition

and doping concentration of the surrounding p-AlGaAs layers, i.e. the p-waveguide layer

(

dres <

180

) having lower Al content (and thus lower band-gap energy) than the p-cladding

layer (

dres >

180

), and the gradual reduction of doping with increasing proximity to the

active zone (see table 4.1). Figure 4.5(b) shows that for eSAS-V2 in the simulated

dres

range,

∆

neff,0 

= 0 between the central and outer regions, unlike the eSAS-V1 configuration with

no lateral waveguiding (c.f. Fig. 4.4). The negative ∆

neff,0

represents index anti-guiding,

corresponding to the blocking structure having a higher refractive index than the surrounding

p-AlGaAs, thus increasing

neff,0

in the outer region. The increasing magnitude of ∆

neff,0

with

decreasing

dres

indicates increasingly stronger spatial overlap of the blocking structure with

the vertical fundamental mode profile.

These findings demonstrate a design trade-off: the selected

dres

should ideally be as low

as possible to minimize current spreading, but reducing

dres

leads to weaker current-blocking

capability and stronger index anti-guiding. It is clear from the simulation results that growing

the blocking structure within the p-waveguide layer (

dres <

180

) should be avoided, due

to the relatively weak current blocking with

Uon <

2 V (comparable to the BAL operating

4. Enhanced Self-Aligned Lateral Structure (eSAS)

voltage range), as well as the strong anti-guiding (∆

neff,0 <−

−3

). On the other hand,

all variants with the blocking structure within the p-cladding layer (

dres >

180

) are shown

to have sufficient current-blocking capability (

Uon >

2 V), meaning that the selection becomes

a trade-off between

dres

and ∆

neff,0

. A

dres

∼

250

is therefore proposed for the eSAS-V2

configuration, which is estimated (for the p-n-p blocking structure) to have

Uon ≈

6 V

and ∆

neff,0

−

−3

. This still represents significant index anti-guiding, but it has

been demonstrated in [68] that under CW operation at

Popt

values close to the operating

point, BALs experience thermally-induced index guiding (thermal lensing) between the central

and outer regions, with a varying magnitude of

∼

9–2

−3

along

(due to LTV; see

section 3.2). Since the two opposing waveguiding mechanisms have similar magnitudes, it can

reasonably be expected that under CW operation, the thermal guiding would counteract the

anti-guiding, thus potentially minimizing the beam quality degradation.

As previously mentioned, the

Uon

estimated by TeSCA for the p-n-p blocking structure

at the proposed

dres ≈

250

is about 4

6 V, indicating strong current-blocking capability.

However, the TeSCA simulation model does not include quantum-mechanical carrier transport

mechanisms such as band-to-band tunneling, which under certain conditions can significantly

affect the I-U characteristics of a p-n-junction. As the applied voltage across the p-n-p blocking

structure increases, the voltage drop across the forward-biased p-n-junction does not increase

beyond its threshold (or knee) voltage, while the voltage across the reverse-biased junction

keeps increasing, thereby increasing the electric field. It is well-known that at sufficiently large

reverse electric fields, p-n-junction breakdown occurs as a result of the Zener effect or avalanche

multiplication, allowing a large current to flow [99–101]. The Zener effect in a p-n-junction

refers to the band-to-band tunneling of electrons under high reverse electric field, specifically

from the valence band of the p-side to the conduction band of the n-side. The resulting current

flow reaches significant levels for electric fields (

) on the order of 10

/cm

; a value that is

frequently reported in the literature as a rule-of-thumb [99–101], but can significantly vary

depending on the band-gap energy (

) of the junction material. Band-to-band tunneling

can also occur through the forward-biased p-n-junction, allowing current flow at bias voltages

lower than threshold followed by a negative differential resistance region, which is the working

principle of a tunnel (or Esaki) diode [100]. For this to occur, however, the p- and n-sides

both typically have to be degenerate, meaning that they are so highly doped that the Fermi

level (under thermal equilibrium) is located within the conduction band on the n-side and

the valence band on the p-side. This leads to a sharper transition over a narrower depletion

region than in a typical forward-biased p-n-junction under thermal equilibrium, corresponding

to higher

which can approach the rule-of-thumb 10

/cm

value and thus enable significant

tunneling current to flow through the forward-biased junction at low bias voltages.

To estimate whether band-to-band tunneling can have an impact on the I-U characteristics

and

Uon

of the p-n-p blocking structure, TeSCA is used to generate band diagrams at varying

bias voltages

(applied across the whole vertical structure), with the section around the

blocking structure shown in Fig. 4.6. At thermal equilibrium (

= 0 V), it is observed that the

n-doped layers are partially degenerate, namely where the conduction band edge is lower than

the Fermi level in Fig. 4.6(a), but the surrounding p-doped layers are not. The band diagrams

can be used to obtain the peak

across each p-n-junction using the derivative curves of the

4.1 Device design and simulation results

Fermi level

Valence band

Conduction band

Valence band

3.85 3.90 3.95 4.00 4.05 3.85 3.90 3.95 4.00 4.05 4.10

(b)

Voltage = 0 V

(thermal equilibrium)

Energy

Vertical position (µm)

Voltage = 3.7 V

dblock dblock

(a)

Vertical position (µm)

Figure 4.6: Energy band diagrams (based on TeSCA simulation) of a representative eSAS-V2

vertical structure, showing a section within about

100

of the p-n-p blocking structure with

dblock

= 60

(indicated on the diagrams) and

ND,block

= 2

18 cm−3

under the following bias

conditions: (a) thermal equilibrium (

= 0 V), with the Fermi level indicated by a dashed blue

line, and (b) high bias voltage (U= 3.7 V).

energy bands. Since the junctions here are both heterojunctions, the magnitude of

is not

identical on the p- and n-doped sides, varying by up to 0

/cm

, so an average value is

used. For the reverse-biased junction, the peak

is found to increase from 0

/cm

= 0 V to 0

/cm

at 1

7 V, and reaches 1

/cm

at 3

7 V (Fig. 4.6(b)), while

for the forward-biased junction,

is found to peak at about 0

/cm

= 0 V and

becomes weaker upon applying a bias voltage. It is thus deduced that band-to-band tunneling

is more likely to take place through the reverse-biased junction, due to

reaching a significantly

higher level across it, on the order of 10

/cm

. Overall, the findings of this TeSCA simulation

suggest that in p-n-p blocking structures, there is a high risk that band-to-band tunneling,

especially through the reverse-biased junction, can lead to lower

Uon

in practice than estimated

from simulation, so the blocking structure design must be optimized to minimize tunneling

probability, as explained in the following.

A simple analytical model is used to estimate the band-to-band tunneling probability

through the p-n-junctions [99–101], in which the band gap is modeled as a triangular potential

barrier with a uniform

, and the Wentzel-Kramers-Brillouin (WKB) approximation is used

to calculate the tunneling probability as

Pbbt ≈exp (︄−4√2m∗·E3/2

3qℏE)︄,(4.1)

where

m∗

is the effective electron mass,

is the elementary charge and

ℏ

is the reduced Planck

constant. The tunneling current density through the reverse-biased junction can then be

calculated as

Jbbt =√2m∗·q3EUR

4π3ℏ2√︁Eg·Pbbt,(4.2)

where

is the reverse voltage across the junction, which can also be obtained from the

simulated band diagram. These equations show that

Pbbt

and

Jbbt

can be minimized by

reducing

, which can be achieved by widening the depletion region of the junction. To this

4. Enhanced Self-Aligned Lateral Structure (eSAS)

0 5 10 15 20 25 30

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

Tunneling current density Jbbt (A/cm2)

Undoped layer thickness di (nm)

Applied voltage

1.7 V

3.7 V

ND,block = 2×1018 cm-3

(a)

012345678

10-3

10-2

10-1

100

101

102

103

Current density (A/cm2)

Applied voltage (V)

p-n-p, 60 nm, 2×1018 cm-3

p-i-n-i-p, 100 nm, 1×1018 cm-3

(b)

Figure 4.7: (a) Estimated band-to-band tunneling current density

Jbbt

at two bias voltage levels

(based on analytical tunneling probability model [99–101]) as a function of undoped layer thickness

in an eSAS-V2 p-i-n-i-p blocking structure with

ND,block

= 2

18 cm−3

, with the dashed

line indicating

Jbbt

corresponding to

= 1

/cm

, and (b) simulated current density as a

function of applied voltage for the eSAS-V2 p-n-p and p-i-n-i-p blocking structure variants, both

at dres ≈250 nm, with the corresponding dblock and ND,block values indicated in the legend.

end, an undoped layer is added between the p- and n-doped layers, thereby changing the p-n-

junction into a p-i-n-junction. With increasing thickness of the undoped layer (

becomes

weaker and

Jbbt

is therefore reduced by multiple orders of magnitude (in agreement with [102]),

as shown in Fig. 4.7(a) with the

Jbbt

corresponding to

= 1

/cm

indicated as a reference

value. Moreover, an undoped layer is similarly incorporated within the forward-biased junction,

despite its lower

peak, with the aim of fully eliminating the risk of band-to-band tunneling.

With an undoped layer on each side of the n-doped blocking layers, the eSAS-V2 blocking

structure is thereby transformed from a p-n-p into a p-i-n-i-p configuration [103]. As previously

mentioned, in an eSAS design, the total

dblock

should be kept as small as possible in order

to minimize step height at the surface and reduce the risk of defect formation upon epitaxial

regrowth, so

= 20

is selected, corresponding to a total

dblock

of 100

. In addition, the

ND,block

of the n-doped blocking layers is reduced from 2

to 1

18 cm−3

, in order to

further widen the depletion regions and reduce E.

The proposed configuration for the eSAS-V2 blocking structure is thus a p-i-n-i-p layer

sequence with

dblock

= 100

(in growth direction: 20

i-InGaP, 20

n-InGaP, 40

n-GaAs, 20

i-GaAs) and

ND,block

= 1

18 cm−3

for the n-doped blocking layers, located

within the p-Al

0.8

GaAs cladding layer at

dres ≈

250

, as shown in Fig. 4.8. The I-U

characteristics of the proposed p-i-n-i-p structure are simulated using TeSCA (i.e. not including

tunneling) and compared to the original p-n-p structure, with both located at the same

dres

While the

ND,block

reduction weakens the blocking capability, it is counteracted by the

dblock

increase, resulting in an overall higher

Uon

of 6

0 V for the p-i-n-i-p blocking structure, as

shown in Fig. 4.7(b). It was previously demonstrated using QIP2 that with the p-n-p blocking

structure outside the stripe at

dres ≈

250

, a lateral index step of ∆

neff,0

−

−3

induced, representing significant anti-guiding. Due to the larger

dblock

in the p-i-n-i-p blocking

structure, ∆

neff,0

becomes

−

−3

, with the increased magnitude corresponding to

4.1 Device design and simulation results

n-buffer (GaAs) &

n-substrate (GaAs)

n-cladding (AlGaAs)

n-waveguide (AlGaAs)

p-waveguide (AlGaAs)

active zone

p+-contact (GaAs)

p-sub-contact (GaAs)

dres

p-cladding (Al0.8GaAs)

i-n-i current block

n-GaAs

n-InGaP

i-InGaP

p-GaAs

i-GaAs

Figure 4.8: Schematic transverse cross section of an eSAS-V2 BAL with a p-i-n-i-p current

block outside the central stripe, located within the p-Al

0.8

GaAs cladding layer. The stripe width

(

), residual thickness (

dres

), regrowth interface (dashed), and current path are indicated on the

diagram (adapted from [52,95]).

1.5 2.0 2.5 3.0 3.5 4.0 4.5

3.0

3.2

3.4

3.6 (a) (b)

No blocking

Refractive index n

Vertical position (µm)

Blocking (V2)

∆neff,0 = -1.85×10-3

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Vertical position (µm)

0.0

0.2

0.4

0.6

0.8

1.0

Normalized intensity

Figure 4.9: Refractive index and normalized optical intensity of the fundamental vertical mode

as functions of vertical position along the layer structure of an eSAS-V2 BAL in: (a) the central

aperture (no blocking), and (b) the outer blocking region, with the blue arrow indicating the

position of the blocking structure. The dashed lines indicate the effective refractive index of the

mode (neff,0) in each case, and the difference (∆neff,0) is given in the legend (adapted from [52]).

stronger anti-guiding. Analog to Fig. 4.4 for eSAS-V1, Figure 4.9 shows the refractive index

and fundamental mode intensity profiles for the eSAS-V2 configuration, clearly demonstrating

the origin of the index anti-guiding. The blocking structure layers (GaAs and InGaP) are

shown to have significantly higher refractive indices than the surrounding p-Al

0.8

GaAs cladding,

and due to their proximity to the active zone, they spatially overlap with the mode profile,

thus affecting its intensity distribution and increasing neff,0 in the outer regions.

To sum up, in comparison to eSAS-V1, the proposed eSAS-V2 p-i-n-i-p configuration

strongly reduces

dres

∼

250

, corresponding to stronger reduction of current spreading.

Strong current blocking in the outer regions is maintained with an estimated

Uon

of 6

0 V,

which is very similar to the eSAS-V1 estimate (6

1 V, see Fig. 4.2). Thin undoped layers are

added to the eSAS-V2 blocking structure to avoid early breakdown via band-to-band tunneling

and ensure effective current blocking. The blocking structure thickness is thus increased, but

4. Enhanced Self-Aligned Lateral Structure (eSAS)

it remains relatively thin (

dblock

= 100

). Significant lateral index anti-guiding is induced

in eSAS-V2 (∆

neff

−

−3

), but as previously mentioned, thermal lensing induces

index guiding with a similar magnitude under CW operation close to the operating point

(

∼

9–2

−3

, varying along

[68]), and is therefore expected to counteract the anti-guiding

effect of the blocking structure and minimize the beam quality degradation.

4.1.4 Estimated performance benefits

For the proposed eSAS-V1 and eSAS-V2 configurations, the next step is estimating the resulting

reduction in current spreading and LCA, and how effective this can be for improving BAL

performance. To this end, two simulations are carried out.

In the first simulation (following [52,83]), the simple analytical model from [104,105] is

used to approximate the lateral current density profile within the active zone, making the

assumptions that

dres << W

and the active zone is very thin (both valid here). For simplicity,

it also assumes a constant current density under the central stripe, such that the total current

can be calculated as

Itot

+ 2

·Io

, with

being the constant central current and

the

spreading current outside the stripe on each side. For a GaAs-based BAL,

is calculated as

Io= 2√︄kBT

q·L

W·Ic

Rsh,x

,(4.3)

where

is the Boltzmann constant,

is the temperature, and

Rsh,x

is the composite sheet

resistance (in the lateral direction

) of all the p-side layers where current is not laterally

confined, calculated as

Rsh,x

=∑︂

j(︄dj

ρj)︄,(4.4)

and

ρj

being the layer thickness and resistivity, respectively. The lateral current density

profile J(x)is then calculated as

J(x) =











WL ,|x| ≤ W/2

loL(︂1 + |x|−W/2

lo)︂2,|x|> W/2,

(4.5)

where lois a characteristic length equal to 4kBT L/ (qIoRsh,x).

This model is used here to simulate current spreading in BALs with different lateral

configurations at lasing threshold (

= 25

°C

). To this end, the constant current density under

the stripe is set to the threshold current density (

Jth

), which is calculated following [8,31] as

Jth =Ith

WL =qdAZ (︂ANth +BN2

th +CN3

th)︂,(4.6)

where

dAZ

is the active zone thickness,

Nth

is the threshold carrier density in the active zone,

and

are coefficients representing the non-stimulated carrier loss mechanisms:

Shockley-Read-Hall, spontaneous and Auger recombination, respectively. This calculation

assumes no stimulated emission (valid at threshold), and excludes the additional loss mechanism

4.1 Device design and simulation results

-100 -50 0 50 100

100

120

Current density J (A/cm2)

Lateral position (µm)

GG Ref.

eSAS-V1

eSAS-V2

Ideal injection

(a)

GG Ref. eSAS-V1 eSAS-V2 Ideal injection

400

450

500

550

600

650

Threshold current Ith (mA)

(b)

Figure 4.10: Simulation results (based on analytical current spreading model [104,105]) of BALs

with

= 90

µm

= 4

, and different lateral configurations (gain-guided reference, eSAS-V1,

eSAS-V2, ideal injection), compared in terms of: (a) current density as a function of lateral position

within the active zone at lasing threshold, and (b) the corresponding threshold current

Ith

(taken

from [52]).

DNx

(with

and

as empirical fit parameters), proposed in [8,31] to account for the excessive

carrier loss that causes a deviation between theoretical and experimental threshold current

values at temperatures beyond

∼

°C

(insignificant effect at 25

°C

and

Nth

are

taken from [8,31], where

Nth

is estimated for a similar ETAS vertical structure to the one

used here (Γ

≈

= 940

) using “kp8” (see section 2.1). This results in a

Jth

of about

120.7 A/cm2.

Figure 4.10(a) shows the resulting lateral current density profiles for BALs (

= 90

µm

= 4

) of the following variants: GG reference with no current confinement, eSAS-V1

with

dres ≈

850

, eSAS-V2 with

dres ≈

250

, and the ideal injection case with no current

spreading (i.e.

Rsh,x

∞

= 0). As mentioned in subsection 4.1.2, eSAS-V1 confines current

through the top half of the p-side, corresponding to higher

Rsh,x

compared to the GG reference,

which is demonstrated in the figure by a significant reduction of current spreading. Similarly,

eSAS-V2 is shown to further reduce current spreading, approaching the ideal injection profile.

In this simulation, the calculated

Itot

value in each case corresponds to the threshold current

Ith

, i.e. the total current needed to reach

Jth

under the stripe. These values are plotted in

Fig. 4.10(b), demonstrating the strong

Ith

reduction that can be expected by minimizing

current spreading. Compared to the ideal injection case with

Ith

= 434

, the model

estimates 630

for the GG reference (

∼

45% higher), 502

for eSAS-V1 (

∼

5% higher)

and 463

for eSAS-V2 (

∼

5% higher). It follows that eSAS-V1 and eSAS-V2 reduce the

loss of spreading current outside the stripe by about 65

5% and 85

5%, respectively, relative to

the GG reference.

The second simulation (following [83]) uses TeSCA’s two-dimensional self-consistent

numerical model, which was introduced in section 2.1. For each lateral design variant at a

given bias voltage, the lateral current density profile can be accurately calculated using this

model, in addition to the corresponding total current and

Popt

. The PUI characteristics are

thus obtained, providing an estimate of the performance enhancement expected from the eSAS

4. Enhanced Self-Aligned Lateral Structure (eSAS)

0 5 10 15 20 25

Voltage = 1.7 V

Current density (kA/cm2)

Lateral position (µm)

GG Ref.

eSAS-V1

eSAS-V2

0.0

0.2

0.4

0.6

0.8

1.0

Normalized optical intensity

(a)

012345

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

W = 20 µm

Voltage U (V)

Current I (A)

GG Ref.

eSAS-V1

eSAS-V2

Optical power Popt (W)

100

Conversion efficiency ηE (%)

(b)

Figure 4.11: TeSCA simulation results of narrow BALs with

= 20

µm

and different lateral

configurations (gain-guided reference, eSAS-V1, eSAS-V2), simplified by assuming longitudinal

homogeneity and a single index-guided lateral mode, compared in terms of: (a) current density and

optical intensity as functions of lateral position (in one half of symmetric BALs) within the active

zone at a high bias voltage (

= 1

7 V), and (b) voltage, optical power and conversion efficiency as

functions of current for L= 4 mm,Rf= 1% and Rr= 95% (adapted from [83]).

approach. The simulation is carried out on a simplified device model, adapted to TeSCA’s

limitations [106], which limits it to one half of a symmetric narrow BAL with

= 20

µm

(

= 4

= 1%,

= 95%), and assumes a single strongly-index-guided lateral mode

rather than typical multi-mode BAL behavior, thereby excluding carrier-density-dependent

lateral waveguiding effects. Figure 4.11(a) shows the simulated lateral current density profiles

for the GG reference, eSAS-V1 and eSAS-V2 lateral designs at a relatively high bias voltage of

7 V, along with the intensity profile of the single lateral mode, which is roughly identical

in all 3 cases. Strong reduction of current spreading at high bias is observed in both eSAS

variants relative to the GG reference, with stronger reduction demonstrated by eSAS-V2,

thereby following the same trend as the analytical model at threshold (Fig. 4.10(a)). The

simulated PUI characteristics are shown in Fig. 4.11(b). It is observed from the P-I curves

that the eSAS variants are estimated to have substantially higher

and lower

Ith

as a result

of reduced current spreading, which is in agreement with the literature (see subsection 3.2.2).

On the other hand, current confinement to a smaller area is expected to increase

, as shown

by the U-I curves. Nonetheless, in terms of

ηE

, the

Ith

and

enhancement are expected

to outweigh the

increase, with the overall outcome being a significant

ηE

increase in the

eSAS variants relative to the GG reference, with greater benefit estimated from eSAS-V2. As

previously mentioned, this simulation is carried out on a narrow-stripe BAL with a single

index-guided lateral mode and assumes longitudinal homogeneity, which means that it excludes

many lateral and longitudinal effects that significantly affect the performance of practical BALs,

and that the observed differences in the PUI characteristics are exaggerated. It shall therefore

be considered a sensitive test, whose results are beneficial for qualitatively determining the

expected performance trends, rather than accurately predicting the experimental results of

realized BALs.

4.2 eSAS first variant (V1): realization and quality control

n-buffer (GaAs) &

n-substrate (GaAs)

n-cladding (AlGaAs)

n-waveguide (AlGaAs)

p-waveguide (AlGaAs)

active zone

p+-contact (GaAs)

p-sub-contact (GaAs)

n-current block

p-cladding (Al0.8GaAs)

p-sub-contact

p-cladding

p-sub-contact

Figure 4.12: SEM images of the stripe edges of representative eSAS-V1 BALs, with highlighted

areas indicated relative to their position on a schematic diagram (adapted from [83]). The left

image is produced using a back-scattered electron (BSE) detector, while the right image is produced

using a secondary electron (SE) detector.

4.2 eSAS first variant (V1): realization and quality control

This section presents the realization of the eSAS-V1 lateral structure, and the various

tests carried out to ensure its correct implementation to match the proposed design (see

subsection 4.1.2), in terms of the epitaxial growth and wafer processing.

The process of realizing eSAS-V1 BALs (Fig. 4.3) goes as follows: in a first growth step,

the ETAS epitaxial structure is grown all the way up to the n-doped current-blocking layers

(GaAs on top of InGaP), with additional sacrificial layers on top. As previously mentioned,

the blocking layers are located within the p-GaAs sub-contact layer, at

dres ≈

850

from

the active zone. The wafers are then taken out of the MOVPE reactor to carry out the

lateral structuring of the blocking layers and create a central current aperture. First, using

photolithography and wet chemical etching, the n-GaAs layer is selectively etched in the center,

with the underlying n-InGaP layer acting as an etch-stop for the GaAs etching solution. Then,

the n-InGaP is also etched in the center, with the structured n-GaAs layer acting as an etching

mask and the underlying p-GaAs acting as an etch-stop for the InGaP etching solution. The

wafers are then placed back in the reactor for the second growth step, in which the remaining

p-side layers are regrown over the structured surface.

To verify that the eSAS-V1 design has been correctly realized, scanning electron microscopy

(SEM) imaging is carried out at the stripe edges of representative eSAS-V1 BALs, with two

examples shown in Fig. 4.12. In the left image, produced using a back-scattered electron (BSE)

detector, the darker-colored layer corresponds to the p-Al

0.8

GaAs cladding. Directly above it,

the interface between the central aperture and outer blocking region is clearly observed, with

the blocking layers appearing as a dark-colored line within the p-GaAs sub-contact layer. The

active zone is also observed as a lighter-colored line within the waveguide layers below the

cladding. The right image, produced using a secondary electron (SE) detector, gives a closer

view of the interface and the blocking layers. These SEM images demonstrate the successful

realization of the eSAS-V1 design, with no crystal defects observed around the stripe edges

or at the regrowth interface along the entire width of the stripe. Further SEM images have

also demonstrated high surface quality, with a high degree of surface flatness after regrowth

(analog to Fig. 4.14) and no surface defects observed at the stripe edges.

The next quality test of the eSAS-V1 realization is testing the current-blocking capability

of the blocking structure and comparing it to the simulated TeSCA estimate (Fig. 4.2). To this

4. Enhanced Self-Aligned Lateral Structure (eSAS)

01234

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

Current density J (A/cm2)

Applied voltage U (V)

Ref.

V1 (SP)

V1 (FP1)

V1 (FP2)

(a)

0123456789

10-3

10-2

10-1

100

101

102

103

Current density J (A/cm2)

Applied voltage U (V)

FP1

FP2

TeSCA

(b)

Figure 4.13: Current density as a function of applied voltage for: (a) measurements V1 p-n-

p current-blocking test devices from 3 successive realizations (SP: short-loop process, FP: full

process) compared to a non-blocking reference BAL with its threshold current density (

Jth

) and

corresponding bias voltage (

Uth

) indicated, and (b) comparison of V1 p-n-p blocking measurements

(from (a)) to the corresponding TeSCA simulation (from Fig. 4.2).

end, blocking test devices have been realized using two different methods. In the first method,

the epitaxial structure is grown in one step, including the V1 p-n-p blocking structure, and

processed into devices with standard dimensions using a simplified short-loop wafer process. In

the second method, blocking test devices are processed alongside eSAS-V1 BALs on the same

wafers, which undergo two-step epitaxial growth followed by a full wafer process. The test

devices are excluded via photolithography from the intermediate selective etching between the

two growth steps, thus leaving the blocking structure intact. In both cases, with no current

apertures etched, it is clear that these test devices cannot be operated as lasers, but their

I-U characteristics can be measured to evaluate the current-blocking capability. Two probe

needles are used for the measurement; one connected to a source-measure unit (SMU) which

simultaneously applies voltage and measures current, and the other connected to a digital

multimeter to form a four-point probe and provide an accurate measurement of the voltage

across the device.

Within the scope of this work, multiple processes have been carried out to develop and

optimize the epitaxial growth procedures and processing technology for the implementation of

the novel eSAS structure. Within these processes, blocking test devices with the V1 p-n-p

design have been realized three times: first in a short-loop wafer process (SP) as an initial

proof of concept, then in two subsequent full wafer processes (FP). As shown in Fig. 4.13,

with no changes to the blocking structure design, a gradual enhancement of current blocking

could be observed in each successive realization, simply by optimizing the growth procedure.

For example, in one of the earlier processes, secondary ion mass spectrometry (SIMS) was

used to analyze the material composition along the layer structure, and it was found that the

incorporated

ND,block

(blocking layer n-doping) is significantly lower than the design value,

which explains the weakened blocking (see Fig. 4.2(b)). The low

ND,block

could then be traced

back to a delay in dopant introduction into the MOVPE reactor, which had a pronounced

4.3 eSAS second variant (V2): realization and quality control

effect due to the small

dblock

. Upon fixing this issue, stronger current blocking was observed

in subsequent processes.

Figure 4.13(a) shows the measured J-U characteristics of the three V1 p-n-p blocking test

devices as well as a reference non-blocking BAL, with all devices having the same dimensions

(

= 90

µm

= 2

) with the exception of the SP device (

= 100

µm

= 1

). Of

highest importance to the eSAS implementation is the current-blocking capability within the

typical operating voltage range of GaAs-based BALs, which is quantified here by comparing

at the threshold bias voltage (

Uth ≈

36 V) corresponding to

Jth ≈

120

7 A

/cm2

in the

reference BAL (see subsection 4.1.4). At

Uth

, the measured

in the SP test device (first

realization) was 4 orders of magnitude lower than

Jth

, which was improved to 7 in the FP1

device, and further in the FP2 device to 8–9 orders of magnitude. In all three test devices,

it is thus clear that current blocking is sufficiently strong within the BAL operating voltage

range, and is even maintained in some cases up to much higher voltages. For example, in the

most recent realization (FP2), the measured

= 4

2 V is

∼

2 A

/cm2

, which is still only

1% of

Jth

. In Fig. 4.13(b), the measurement results of the V1 p-n-p blocking test devices are

compared to the corresponding TeSCA simulation (from Fig. 4.2). It is observed that despite

the gradual improvement, current blocking in the realized structures is still significantly weaker

than the simulation estimates. At

= 10

−3

/cm2

, the FP2 device exhibits

Uon

= 3

2 V, which

is high relative to BALs, but still much lower than expected from simulation (6

1 V). This can

either be explained by unidentified issues with the growth (similar to the aforementioned low

ND,block

) or alternatively by limitations of the TeSCA simulation model (e.g. not including

band-to-band tunneling, as discussed in subsection 4.1.3), but since the measured blocking

capability is sufficiently strong for the eSAS implementation, this deviation is not investigated

further. Overall, this quality test showed the successful realization of V1 blocking structures

that can fulfill their purpose, namely strong current blocking within and beyond the BAL

operating voltage range, thus enabling the implementation of BALs with the eSAS-V1 lateral

structure.

4.3

eSAS second variant (V2): realization and quality control

Analog to the previous section, this section presents the realization of the eSAS-V2 lateral

structure and the various quality control tests, carried out to ensure proper implementation of

the design proposed in subsection 4.1.3.

The process of realizing eSAS-V2 BALs (Fig. 4.8) goes as follows: the epitaxial structure

is grown in a first growth step up to the current-blocking structure, with additional sacrificial

layers on top. As previously mentioned, the blocking structure is located within the p-Al

0.8

GaAs

cladding layer at

dres ≈

250

, and is composed of a p-i-n-i-p layer sequence with undoped

and n-doped blocking layers on top of a thin p-doped GaAs layer. The wafers are then taken

out of the MOVPE reactor (i.e. ex situ), where the sacrificial and blocking (undoped and

n-doped) layers are laterally structured using photolithography and selective wet chemical

etching to create a central current aperture. At this point, the p-GaAs layer is exposed in the

center, while the outer regions remain unchanged with the sacrificial layers on top. The wafers

are then placed back into the reactor, where in situ etching with CBr

(non-selective) is used

4. Enhanced Self-Aligned Lateral Structure (eSAS)

n-buffer (GaAs) &

n-substrate (GaAs)

n-cladding (AlGaAs)

n-waveguide (AlGaAs)

p-waveguide (AlGaAs)

active zone

p+-contact (GaAs)

p-sub-contact (GaAs)

p-cladding (Al0.8GaAs)

i-n-i current block

p-cladding

Figure 4.14: SEM images of the stripe edges of representative eSAS-V2 BALs, with highlighted

areas indicated relative to their position on a schematic diagram. Both images are produced using

a secondary electron (SE) detector.

to remove the p-GaAs layer in-stripe, thus exposing the underlying p-Al

0.8

GaAs cladding, as

well as removing the sacrificial layers outside the stripe to expose the blocking layers [98]. It is

clear that this in situ etching step increases the process complexity of eSAS-V2 relative to

eSAS-V1 and established SAS realizations, but as explained in subsection 4.1.3, it is necessary

to prevent the exposure of Al

0.8

GaAs to air outside the reactor. Otherwise, Al would rapidly

oxidize, forming electrically-insulating aluminium oxide (Al

) that could drastically increase

and degrade BAL performance. Upon completion of the in situ etching step, the structure

is finalized with a second growth step, in which the remaining p-side layers are regrown over

the structured surface.

After the process of realizing eSAS-V2 BALs is complete, SEM is used to verify the correct

implementation of the design. Figure 4.14 shows two SEM images produced using a secondary

electron (SE) detector, highlighting the interface between the central current aperture and outer

blocking region at stripe edges of representative eSAS-V2 BALs. In both images, the structured

blocking layers appear as a lighter-colored structure near the bottom of the p-cladding, while

the active zone appears as a thin lighter-colored line within the waveguide layers below the

p-cladding. It is clearly observed that the blocking layers are much closer to the active zone in

eSAS-V2 in comparison to eSAS-V1 (c.f. Fig. 4.12). SEM imaging could thus demonstrate the

first successful realization of the eSAS-V2 design, with increased process complexity enabling

the structured current block to be located within the p-Al

0.8

GaAs cladding. To the author’s

knowledge, this is the first reported realization that involves etching and regrowth within a

material with such high Al content. Moreover, the images demonstrate that a high degree of

surface flatness is obtained after regrowth, despite the increased

dblock

relative to eSAS-V1.

However, various defects and morphological features are observed around the aperture edges,

which appear to be connected to the inclined sidewall of the structured blocking layers. A

further test is subsequently carried out to study these non-idealities in more detail, as described

below.

In this test, transmission electron microscopy (TEM) is used to analyze the structural

quality of eSAS-V2 BALs and determine the origin of the aforementioned features and defects.

Quoting the author’s work [52], “Fig. 4.15 shows scanning TEM (STEM) images of the edge

of a representative central current aperture. In Fig. 4.15(a), the high-angle annular dark-field

(HAADF) imaging method is used, which exhibits a contrast strongly dependent on the mean

atomic number (Z-contrast) and the local thickness of the TEM specimen, whereas Fig. 4.15(b)

uses the annular dark-field (ADF) method, which predominantly exhibits strain contrast,

4.3 eSAS second variant (V2): realization and quality control

p-GaAs

p-Al0.8Ga0.2As

waveguide

p-GaAs

p-Al0.8Ga0.2As

waveguide

Figure 4.15: STEM images showing typical structural features resulting from epitaxial regrowth

over the edge of an eSAS-V2 BAL aperture, using the (a) HAADF and (b) ADF imaging methods.

The imaged area matches the SEM image in Fig. 4.14(left) (taken from [52]).

allowing the analysis of crystal defect distribution within the heterostructure. Upon epitaxial

regrowth over the laterally structured blocking layers, the inclined sidewalls of the aperture

experience a different growth rate compared to planar parts of the surface. This leads to

the formation of non-planar growth fronts, which are clearly visible in Fig. 4.15(a). After

regrowth of the p-Al

0.8

GaAs cladding, the local height difference at the aperture edge is larger

than the total thickness of the blocking layers, due to the different growth rates, but the

subsequent regrowth of the p-GaAs sub-contact and contact layers significantly flattens the

surface. Depending on the applied growth parameters, 3-dimensional AlGaAs regrowth can

lead to self-organization of aluminium within the layers, resulting in Al-rich and Al-poor

regions [107]. To determine if this effect occurs here, we use HAADF STEM imaging in

combination with energy-dispersive X-ray spectroscopy (EDXS). Using these techniques, no

change in Al content is observed above the aperture edges, indicating an inhomogeneity lower

than 1 atomic percent.”

“However, as shown in Figs. 4.15(b) and 4.16, regrowth over the aperture edges results in a

large number of crystal defects at the inclined sidewalls, such as stacking faults and threading

dislocations. On the other hand, no defects or non-idealities are observed at the regrowth

interface along the entire current aperture, and neither above nor below the planar parts

of the blocking layers. The defects are thus limited to the vicinity of the inclined sidewalls,

constituting

1% of the aperture width. High-resolution TEM (HRTEM) imaging is used to

take a closer look at the aperture edge in Fig. 4.16(a) and reveal the origin of the observed

defects. Whereas a perfect AlGaAs crystal structure grows above the planar surface of the

blocking layers, lateral growth takes place over the inclined sidewall. This lateral growth

in free space without a lattice-matched buffer at the bottom results in the formation of a

large number of stacking faults and twins, as shown in Figs. 4.16(c) and (d). Similar defect

formation takes place at the bottom of the aperture edge (Fig. 4.16(b)), where the material

growing over the bottom of the aperture coalesces with the material nucleating on the sidewall.

The dark regions frequently observed at the inclined sidewalls (Fig. 4.16(a)) are attributed

to the formation of voids containing amorphous material, as shown in Fig. 4.16(d). The

void formation was confirmed using EDXS, which could not precisely identify the material

composition, but detected low-intensity oxygen peaks. One possible interpretation of the EDXS

4. Enhanced Self-Aligned Lateral Structure (eSAS)

Figure 4.16: (a) HAADF STEM image of the edge of an eSAS-V2 BAL aperture, (b), (c) and

(d) HRTEM images of specific areas indicated on (a), demonstrating the formation of stacking

faults (SFs), twins and voids as a result of the epitaxial regrowth of Al0.8GaAs over the aperture

edge (taken from [52]).

analysis is that the amorphous material in the voids is Al

, which has significantly lower

refractive index (

n≈

7) than the surrounding layers. To estimate the potential influence

of the voids on lateral waveguiding, we repeat the QIP2 simulation (see subsection 4.1.3),

modelling the void as a 15

layer replacing part of the thicker GaAs blocking layer

in the outer blocking region. With these assumptions, ∆

neff,0

is reduced from

−

−3

−

−3

, indicating that the voids can potentially induce index guiding, but the

anti-guiding of the current-blocking layers would likely remain the dominant waveguiding

mechanism. The defects at the aperture edges (stacking faults, twins and voids) have had to

date no observed negative impact on device performance, as discussed in section 4.4. To limit

or eliminate defects in future realizations, regrowth parameters have to be optimized in order

to control growth kinetics and thus lateral and vertical growth rates.”

It was previously mentioned that the added in situ etching step is necessary for the

realization of eSAS-V2 BALs, in order to prevent the exposure of Al

0.8

GaAs to air and the

subsequent Al oxidation into electrically-insulating Al

. However, it was also mentioned in

relation to the TEM study that low-intensity oxygen peaks were detected using EDXS within

the voids formed at the edges of the current aperture, which suggests that the amorphous

material inside the voids can possibly be Al

. It is therefore the aim of the next quality

control test to determine the effectiveness of the eSAS-V2 process (with the in situ etching step)

in preventing Al oxidation within the p-Al

0.8

GaAs cladding, specifically at the etch-regrowth

interface along the aperture.

4.3 eSAS second variant (V2): realization and quality control

2.5 3.0 3.5 4.0 4.5 5.0

1015

1016

1017

Oxygen concentration (cm-3)

Vertical position (µm)

100

101

102

103

104

105

Aluminium concentration (counts/s)

Figure 4.17: Oxygen and aluminium concentrations (measured using SIMS) as functions of

vertical position along an eSAS-V2 test device that undergoes complete removal of the blocking

structure between the two growth steps, with the etch-regrowth interface indicated by a dashed

line (taken from [52]).

To this end, test devices have been realized using a simplified process, in which the blocking

layers are completely removed after the first growth step (i.e. ex situ etching with no prior

photolithography), rather than being laterally structured. After the subsequent in situ etching

and second growth steps, the wafers are processed into devices with standard dimensions using

a simplified short-loop wafer process. Quoting the author’s work [52], “oxygen content along

the vertical structure is then measured using SIMS, as shown in Fig. 4.17, with the measured

Al content also plotted for orientation. An oxygen peak is observed at the etch-regrowth

interface, but with very low concentration (

16 cm−3

). This result demonstrates that

using the eSAS-V2 process, the p-i-n-i-p blocking structure can be successfully integrated

within the p-Al

0.8

GaAs cladding in close proximity to the active zone, while minimizing Al

oxidation and the subsequent performance deterioration.”

The final eSAS-V2 quality control study focuses on the current-blocking capability of the

blocking structure, analog to the eSAS-V1 blocking study presented in section 4.2, using the

same methods to realize test devices as well as the same measurement configuration with the

four-point probe. Blocking test devices with the V2 p-i-n-i-p design have been realized twice:

first in a short-loop wafer process (SP) with one-step epitaxial growth, and then alongside

eSAS-V2 BALs in a full wafer process (FP) with two-step epitaxial growth.

Figure 4.18(a) shows the measured J-U characteristics of V2 p-i-n-i-p blocking test devices

from the 2 successive realizations (SP and FP), and compares them to a V1 p-n-p test device

from the same FP (corresponding to FP2 in Fig. 4.13) as well as a reference non-blocking

BAL. Once again, all the measured devices have the same dimensions (

= 90

µm

= 2

)

with the exception of the SP device (

= 100

µm

= 1

). Current-blocking capability is

evaluated within the typical operating voltage range of GaAs-based BALs by comparing

allowed by the blocking test devices at

Uth ≈

36 V, corresponding to

Jth ≈

120

7 A

/cm2

the reference BAL (see subsection 4.1.4). At

Uth

, both V2 test devices exhibit very strong

current blocking, with

being 8–9 orders of magnitude lower than

Jth

. Comparing them to

each other, it is observed that the V2 FP device is slightly better at lower voltages, while the

V2 SP device maintains stronger blocking at higher voltage levels. For example, at

= 4

2 V,

4. Enhanced Self-Aligned Lateral Structure (eSAS)

01234

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

Current density J (A/cm2)

Applied voltage U (V)

Ref.

V1 (FP)

V2 (SP)

V2 (FP)

(a)

012345678

10-3

10-2

10-1

100

101

102

103

Current density J (A/cm2)

Applied voltage U (V)

TeSCA

(b)

Figure 4.18: Current density as a function of applied voltage for: (a) measurements of V2

p-i-n-i-p current-blocking test devices from 2 successive realizations (SP: short-loop process, FP:

full process) compared to the best realization of V1 p-n-p blocking test devices (from Fig. 4.13)

and a non-blocking reference BAL with its threshold current density (

Jth

) and corresponding bias

voltage (

Uth

) indicated, and (b) comparison of V2 p-i-n-i-p blocking measurements (from (a)) to

the corresponding TeSCA simulation (from Fig. 4.7(b)).

the measured

∼

−3

/cm2

in the SP device (0

001% of

Jth

) and

∼

06 A

/cm2

the FP device, which is still only 0

05% of

Jth

. These differences between the two devices are

nonetheless much smaller than the contrast between the different realizations in the earlier

V1 test (Fig. 4.13), where current blocking was significantly improved with each successive

realization by optimizing the growth procedure. Conversely, the comparable blocking in the

V2 test devices is consistent with an optimized and reproducible growth process. Comparing

the V2 and V1 test devices from the same FP, it is clear that while strong current blocking is

obtained by both blocking structure variants, the V2 p-i-n-i-p variant exhibits more effective

blocking than its V1 p-n-p counterpart over the whole applied voltage range. Quoting the

author’s work [52], “it’s important to note that the thin undoped layers add to the total

thickness of the p-i-n-i-p structure, which inherently improves current blocking, but this effect

is counteracted by a significant reduction in the doping concentration of the n-doped layers.

In addition, the differences in the composition and doping concentration of the surrounding

p-doped layers in each case also have an inherent impact on the current-blocking capability.

Although the comparison is non-ideal, this result is nonetheless consistent with the expectation

that p-i-n-i-p structures enhance current blocking relative to p-n-p structures by reducing the

probability of band-to-band tunneling, as discussed in subsection 4.1.3.”

In Fig. 4.18(b), the V2 p-i-n-i-p blocking test devices are compared to the corresponding

TeSCA simulation (from Fig. 4.7(b)). Similar to the earlier V1 blocking study, it is observed

that while effective current blocking is exhibited by the V2 test devices, it is still significantly

weaker than expected from simulation, either due to unidentified issues with the growth or

limitations of the TeSCA simulation model. At

= 10

−3

/cm2

, the SP and FP devices

exhibit

Uon

values of 4.2 and 3

6 V respectively, while the TeSCA simulation estimates 6

0 V.

Nonetheless, it has been demonstrated by this quality test that realized V2 p-i-n-i-p blocking

structures exhibit strong current blocking within and beyond the BAL operating voltage range,

4.4 Device characterization and measurement results

thus fulfilling their purpose and enabling the implementation of BALs with the eSAS-V2

lateral structure.

4.4 Device characterization and measurement results

The previous sections presented the design, realization and quality control of BALs with the

eSAS lateral structure variants V1 and V2, with their final configurations shown in Figs. 4.3

and 4.8, respectively. On each processed epitaxial wafer, GG reference BALs are realized

alongside eSAS BALs to enable a fair performance comparison and accurately determine the

benefits and drawbacks of the eSAS as a lateral structuring approach, independent of the

performance reproducibility of the vertical structure over different growth processes. In these

GG reference BALs, the current-blocking structure is completely etched between the two

growth steps, such that after epitaxial regrowth, they are nominally identical to conventional

BALs with the ETAS vertical structure grown in one step. Unlike eSAS BALs, where

corresponds to the width of the etched aperture through the blocking structure,

in GG

reference BALs is defined using selective shallow ion implantation of the p

-contact layer,

with the final configuration resembling Fig. 3.2(a).

The next step is characterization of the realized BALs with the three lateral design variants

(GG reference, eSAS-V1, eSAS-V2) in order to compare their performance. To this end,

BAL single emitters (SEs) are processed (by cleaving the epitaxial wafers followed by facet

passivation and coating) then mounted in a configuration that enables effective heat extraction

and temperature regulation, as described in detail in section 2.2. The SEs are all processed

to have

= 4

= 1% and

= 98%, with varying

= 20, 50, 90 and 186

µm

After mounting, each SE is characterized under CW operation at 25

°C

by measuring its PUI

and spectral characteristics, beam quality, and polarization purity, using the measurement

techniques described in section 2.3. A large number of SEs are characterized and their

measurement results are presented in this section, along with detailed analysis and comparison

of the performance of the three lateral design variants. Finally, the best-performing eSAS

BALs are benchmarked against state-of-the-art devices, and the findings are discussed and

summarized to provide an outlook for the eSAS as the lateral structuring technique of choice

in future realizations.

Power-voltage-current (PUI) and spectral characterization

First, the PUI and spectral characteristics of SEs with

= 90

µm

are presented, which

are measured up to

= 11 A, with

Popt

= 10 W designated as a relevant operating point,

based on device dimensions, for comparison to the literature. Figure 4.19(a) shows the PUI

characteristics of a representative 90

µm

SE of each design variant, and their extracted electro-

optical performance metrics are compared. In terms of

Ith

, it is observed that eSAS-V2 has

the lowest value (427

), followed by eSAS-V1 (489

), with the GG reference having the

highest value (598

). The three SEs are found to have very similar slopes (

1and

2) of

the P-I curve, as well as almost identical U-I characteristics, corresponding to roughly constant

. Both eSAS variants show a clear advantage over the GG reference in terms of

ηE,peak

with eSAS-V1 achieving the highest value (68

7%), followed by eSAS-V2 (67

7%), and finally

4. Enhanced Self-Aligned Lateral Structure (eSAS)

0 1 2 3 4 5 6 7 8 9 10 11

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Voltage U (V)

Current I (A)

GG Ref.

eSAS-V1

eSAS-V2

Optical power Popt (W)

Conversion efficiency ηE (%)

(a)

0 1 2 3 4 5 6 7

920

925

930

935

940

GG Ref.

eSAS

Centroid wavelength λc (nm)

Dissipated power Pdiss (W)

V1 (FP1)

V1 (FP2)

V2 (FP2)

(b)

Figure 4.19: Measurement results (CW, 25

°C

) of representative BAL SEs with

= 90

µm

and

= 4

, compared in terms of: (a) voltage, optical power and conversion efficiency as functions

of current for different lateral configurations: gain-guided reference, eSAS-V1 and eSAS-V2 (taken

from [52]), and (b) centroid wavelength as a function of dissipated power in reference and eSAS

SEs realized in different growth runs (V1 versus V2) and wafer processes (FP1 versus FP2).

the GG reference (66

5%). However, at the operating point (10 W), the three SEs are found to

have very similar ηEvalues in the 64.5–65.0% range [52].

For each 90

µm

SE, the measured spectrum at each current level is used to extract the

centroid wavelength (

λc

), which is then plotted as a function of

Pdiss

and used to calculate

Rth

following standard practice (see section 2.3). The

λc

Pdiss

curves of representative SEs

from different full process (FP) realizations are shown in Fig. 4.19(b). Significant

λc

shifts are

observed between different FPs (8–9

) and even between different growth runs (V1 versus

V2) from the same FP (1.5–2

). These shifts are likely caused by small variations in the

growth of the active zone layers, which are not expected to affect peak device performance

and are therefore not further investigated here. On the other hand, the slope ∆

λc/

∆

Pdiss

found to be very similar for all the representative SEs, corresponding to consistent

Rth

values

in the 2.06–2

31 K

Wrange. Another observation, that is most relevant for the purposes of

this study, is that GG reference and eSAS SEs from the same wafers exhibit very similar

λc

across the whole current range, which indicates that the eSAS lateral structure has no effect

on the spectral characteristics or Rth.

To obtain reliable trends and confirm the prior observations, the performance metrics of a

large number of 90

µm

SEs (

≥

11 of each design variant) are extracted and averaged, with

Table 4.2: Averaged performance metrics of

≥

11 SEs (

= 90

µm

= 4

) of each lateral

configuration (gain-guided reference, eSAS-V1, eSAS-V2), extracted from their measured PUI and

spectral characteristics (CW, 25 °C).

Lat. design Rth Ith S1S2RsηE,peak ηE,10W

(K/W) (mA) (W/A) (W/A) (mΩ) (%) (%)

GG Ref. 2.23 592 1.10 1.00 19.8 66.5 64.4

eSAS-V1 2.22 487 1.10 0.98 20.5 68.0 64.5

eSAS-V2 2.23 428 1.07 1.01 20.0 67.3 64.4

4.4 Device characterization and measurement results

the resulting mean values presented in table 4.2 for a detailed analysis. The average

Rth

found to be almost identical in all variants, thus confirming that it is unaffected by the eSAS.

Relative to the GG reference,

Ith

is reduced by 18% in eSAS-V1 and 28% in eSAS-V2, which

clearly demonstrates the effective reduction of lateral current spreading (see subsection 3.2.2).

On average, eSAS-V1 shows slightly reduced

2while eSAS-V2 shows slightly reduced

with the differences lying marginally outside the

5% standard error margin reported in [10].

Beyond these small differences, the slope of the P-I curve is found to be broadly consistent

in all variants and thus not significantly affected by the eSAS.

is found to be slightly

higher on average in eSAS variants (3

5% in eSAS-V1, 1% in eSAS-V2), which differs from

the prior observation based on individual representative SEs. However, the negative effects

of this marginal

increase, i.e. increased

and consequently reduced

ηE

, are found to be

very small and almost insignificant. The averaged metrics confirm the

ηE,peak

advantage of the

eSAS variants compared to the GG reference, which mostly results from the strongly reduced

Ith

, with the changes to

and

being relatively small. Nonetheless, despite the lower

Ith

eSAS-V2, its

ηE,peak

benefit is observed to be smaller than eSAS-V1 (0.8 versus 1.5 percentage

points), which is due to the slightly lower

1in eSAS-V2. Finally, in agreement with the prior

observation, the average ηEat 10 W is found to be almost identical in all three variants.

Comparing the measured PUI performance trends to the ones estimated from the simulation

(Fig. 4.11(b)), an agreement is found in terms of

Ith

, with significant reduction exhibited by

the eSAS variants that is proportional to the reduction of current spreading. The estimated

increase in eSAS due to stronger current confinement is also validated by the measurements, but

is found to be much less significant in the realized 90

µm

SEs than estimated from simulation,

therefore having very little impact on BAL performance. As discussed in subsection 4.1.4, the

larger estimated

difference is due to the TeSCA simulation being a qualitative sensitive test,

involving 20

µm

BALs with a single lateral mode and excluding many lateral and longitudinal

mechanisms, which can lead to exaggerated performance differences. The measured trends,

however, show eSAS-V2 having lower

than eSAS-V1, which is not estimated by simulation

and inconsistent with the stronger current confinement in eSAS-V2. This discrepancy is

attributed to growth- or process-related variations between different wafers, similar to the

unintended

λc

shifts in Fig. 4.19(b). While the measured

Ith

and

trends match the

simulation estimates, the measured

1and

2are broadly consistent in all variants, and thus

do not exhibit the slope enhancement associated with reduced current spreading, as estimated

not only by the simulation (exaggerated due to single- rather than multi-mode guiding), but

in the literature as well [72]. Quoting the author’s work [52], “one possible explanation is LCA

occurring not at the stripe edges, but rather within the stripe at the front facet, which can be

explained by lateral spatial hole burning and thermal lensing in the presence of longitudinal

temperature variation. This can result in non-ideal overlap between the lateral carrier and

optical profiles and therefore lower gain [69,81].” This slope-limiting mechanism is described in

more detail in subsection 3.2.2. With the simulated and measured

trends not in agreement,

it follows that the

ηE

trends also do not match. While the simulation estimates higher

ηE

the eSAS variants over the whole current range as a result of their higher S, measured eSAS

SEs only exhibit higher

ηE,peak

at relatively low current levels, which, as previously mentioned,

is largely due to the Ith reduction.

4. Enhanced Self-Aligned Lateral Structure (eSAS)

0 20 40 60 80 100 120 140 160 180 200

100

200

300

400

500

600

700

800

900

1000

1100

GG Ref.

eSAS-V1

eSAS-V2

Threshold current Ith (mA)

Stripe width W (µm)

(a)

186

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

1.12

1.14

GG Ref. (S1)

Stripe width W (µm)

Slope S1 (W/A)

±1.5%

std.

error

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

1.12

1.14

GG Ref. (S2)

Slope S2 (W/A)

eSAS-V1 (S1)

eSAS-V1 (S2)

eSAS-V2 (S1)

eSAS-V2 (S2)

(b)

Figure 4.20: Performance metrics extracted from PUI measurements (CW, 25

°C

) of

≥

13 SEs

(

= 4

, varying

) of each lateral configuration (gain-guided reference, eSAS-V1, eSAS-V2):

(a) threshold current

Ith

as a function of

, with linear fits extrapolated to intercept with the

y-axis (

= 0), and (b) slopes

1and

2for SEs with

= 50, 90 and 186

µm

, measured up to 7,

11 and 15 A, respectively (taken from [52]).

Since the previous analysis focused exclusively on SEs with

= 90

µm

, the next step

is determining whether the observed performance trends are consistent for different stripe

widths. To this end, the PUI metrics of

≥

13 SEs of each variant with varying

(20, 50, 90

and 186

µm

) are extracted and analyzed. In Fig. 4.20(a),

Ith

is plotted as a function of

for each variant, demonstrating a very consistent trend of

Ith

reduction over the whole

range. As described in subsection 3.2.2, these plots can be used to estimate the current loss at

threshold due to lateral current spreading, based on the empirical method from [74]. Linear

fits of the

Ith

values for each variant are extrapolated to intercept with the y-axis (

= 0)

at the intercept point

Ith,0

, which represents an empirical estimate of the spreading current

lost at threshold. Using this method,

Ith,0

values of 218, 94 and 24

are obtained for the

GG reference, eSAS-V1 and eSAS-V2 variants, respectively. Relative to the reference, the

corresponding current loss reduction is thus 57% in eSAS-V1 and 89% in eSAS-V2, which

are notably similar to the simulation estimates using the analytical current spreading model

(Fig. 4.10), which are 65.5% and 85.5% respectively [52].

Similarly, Fig. 4.20(b) shows the extracted slope values

1and

2of the SEs with varying

of each variant. The analysis includes SEs with

= 50, 90 and 186

µm

, measured up to

7, 11 and 15 A, respectively, with

1and

2calculated as described in section 2.3. Unlike

their broader counterparts, the measured P-I characteristics of 20

µm

SEs are not typically

linear beyond

Ith

, but rather tend to exhibit kinks at unpredictable current levels, which

are consistent with mode hops or otherwise unstable operation [83]. Consequently,

1and

2cannot be reliably extracted and compared for the 20

µm

SEs in this work, and are thus

excluded from this analysis. In agreement with table 4.2, the figure shows the differences in

and

2between variants at

= 90

µm

lying within or marginally outside the

5% standard

error margin [10]. A dependence on

is demonstrated, with slope differences between variants

found to be smaller in 186

µm

SEs (all within

5% error margin) and larger in 50

µm

SEs.

More specifically,

1and

2of 50

µm

eSAS-V2 SEs are found to be

∼

7% lower than their

GG reference counterparts. This could be explained by worse overlap between carrier and

4.4 Device characterization and measurement results

0 5 10 15 20 25 30

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Voltage U (V)

Current I (A)

90 µm

186 µm

Optical power Popt (W)

Conversion efficiency ηE (%)

Figure 4.21: Measured voltage, optical power and conversion efficiency as functions of current

(CW, 25

°C

) for two exemplary eSAS-V2 SEs with

= 90 and 186

µm

, respectively, and

= 4

measured up to high current levels corresponding to Popt,max (taken from [52]).

optical profiles (see above) or alternatively by the defects at aperture edges having a more

pronounced effect in narrower BALs (see section 4.3), but this is not explored in further detail

here. In any case, this analysis confirms that the estimated slope enhancement could not be

demonstrated in eSAS realizations to date, despite the suppression of current spreading losses

by up to 89% [52]. Overall, the observed trends in Fig. 4.20 show that the findings obtained

from 90 µmSEs (table 4.2) are generally valid for all stripe widths.

In all characterization results presented up to this point, SEs were measured up to

moderate current levels relative to their dimensions, with the purpose of extracting reproducible

performance metrics that enable a reliable comparison of the three lateral design variants.

The next step is measuring SEs up to high current levels, to study their power saturation

and thermal roll-over behavior (see section 3.2). Among a large number of measured 90 and

186

µm

SEs of different variants, the highest

Popt,max

values were achieved by eSAS-V2 devices.

Figure 4.21 shows the PUI characteristics of the best-performing eSAS-V2 SE of each of

the two stripe widths, and a selection of extracted key performance metrics is presented in

table 4.3. Quoting the author’s work [52], it is observed that “the 90

µm

SE does not fail up to

a current of 23.6 A, corresponding to Popt,max = 20.9 W, with ηE= 51.5% at 20 W. Similarly,

the 186

µm

SE does not fail up to a current of 28

4 A, corresponding to

Popt,max

= 27

2 W, with

ηE

= 69

0% at its peak, 65

8% at 20 W, and 61

6% at 25 W. These results clearly demonstrate

the benefits of the ETAS vertical structure used in this realization, which enables high

ηE

at high

Popt

(see subsection 4.1.1). The high

Popt

levels obtained by the SEs also show that

despite the defects observed using TEM (see section 4.3), the eSAS-V2 configuration does not

cause early power saturation or failure.”

The PUI performance of eSAS SEs is then benchmarked against state-of-the-art BAL SEs

which have recently been reported in the literature (as summarized in section 3.1), limiting

the comparison to SEs with

= 4

, mounted p-side down on passively-cooled heat sinks.

As a first step, they are compared to best-performing baseline SEs from the FBH, fabricated

using one-step epitaxial growth and standard processing techniques, and having comparable

dimensions, facet reflectivities and mounting configurations. For example, the 90

µm

eSAS

and reference SEs realized in this work (using two-step growth), with their results shown in

4. Enhanced Self-Aligned Lateral Structure (eSAS)

tables 4.2 and 4.3, can be compared to the baseline 100

µm

SE in Fig. 3.1(b) [8,31]. This

baseline device uses a similar ETAS vertical design to the one used here, with nearly identical

and Γ. However, its

is lower by 3–4

mΩ

, which is due in part to its larger

but also to

differences in the epitaxial structure. In terms of

Ith

, two-step reference SEs exhibit somewhat

higher

Ith

than the baseline, which is also likely connected to epitaxial structure differences

in addition to the different measurement conditions (CW versus pulsed). Nonetheless, eSAS

SEs (especially eSAS-V2) still show a strong

Ith

reduction relative to the baseline, resulting

from the strongly reduced current spreading. The reported

of the baseline SE was also

obtained using a pulsed measurement, which makes it comparable to

1under CW operation

(i.e. at low current and heat levels). The measured

1values of eSAS and reference SEs are

found to be almost identical to the

value of the baseline SE, indicating that no additional

losses are introduced by the two-step epitaxial growth process. In terms of

ηE,peak

under CW

operation, two-step reference SEs exhibit values lower than the baseline by

∼

5percentage

points, which is a direct result of their higher

. Despite having the same significant

disadvantage, eSAS SEs exhibit

ηE,peak

values more comparable to the baseline as a result of

their lower

Ith

, with the best-performing eSAS-V1 SEs even surpassing the baseline (68

versus 68%). Out of all the different SEs with

= 90–100

µm

and varying epitaxial structures

which have been realized to date at the FBH, the highest

Popt,max

level under CW operation

has been achieved by the eSAS-V2 BAL SE in Fig. 4.21 (20

9 W). In another example [62],

the

ηE.peak

of baseline 186

µm

SEs showed a strong dependence on the combination of

and

the Γof the ETAS vertical design, with the highest value (71%) achieved by the SE variant

with Γ

≈

5% and

= 3%. However, the variant with Γ

≈

1% and

= 1%, which is most

comparable to the SEs realized in this work, exhibited

ηE,peak

= 64%. The 186

µm

eSAS SE in

Fig. 4.21 achieves a significantly higher

ηE,peak

of 69%, as well as the highest

Popt,max

under

CW operation reported from a 186 µmSE realized at the FBH (27.2 W).

Benchmarking against the best recent results from other research groups can be challenging

due to several factors. These include differences in mounting and cooling configurations and

vertical structures, as well as measurement setup variations, e.g. the commercial power detectors

used by most groups are typically calibrated to within

3–5% of national standards, meaning

that comparisons of absolute

Popt

and

ηE

values obtained using different detectors can be

misleading [10]. Nonetheless, it is observed that while the metrics presented here are not as high

as some record metrics reported in the literature, the performance is still broadly comparable.

For example, the 940

BAL SEs with

= 90

µm

from JENOPTIK achieved

ηE,peak

= 70%

and

ηE

= 64% at 12 W [54]. The 90

µm

eSAS-V2 SE metrics presented here are slightly lower

but still comparable to these results, with

ηE,peak

= 67

5% (up to 68

7% in eSAS-V1; see

Table 4.3: Key performance metrics extracted from the measured PUI characteristics in Fig. 4.21,

corresponding to two exemplary eSAS-V2 SEs with

= 90 and 186

µm

, respectively, and

L= 4 mm, measured up to high current levels corresponding to Popt,max (CW, 25 °C).

W Popt,max ηE,peak ηE,12W ηE,13W ηE,17W ηE,20W ηE,25W ηE,27W

(µm) (W) (%) (%) (%) (%) (%) (%) (%)

90 20.9 67.5 62.9 61.9 56.5 51.5 – –

186 27.2 69.0 68.9 68.7 67.3 65.8 61.6 59.4

4.4 Device characterization and measurement results

Fig. 4.19(a)) and

ηE

= 62

9% at 12 W. In another example, in two realizations of 915

BALs

by Optoenergy, SEs with

= 100

µm

showed

Popt,max

levels of 24 and 22

5 W, respectively,

and at 13 W, had

ηE

values of over 60% and

∼

62%, respectively [55,57]. These metrics are

comparable to the 90

µm

eSAS SE results, namely

Popt,max ≈

9 W and

ηE

= 61

9% at 13 W.

In the aforementioned 915

BAL realizations by Optoenergy,

ηE,peak

= 68% was achieved by

SEs with varying stripe widths. Moreover, a 150

µm

SE maintained

ηE

= 65% up to 17 W, a

220

µm

SE maintained 60% up to 27 W, and a 180

µm

SE achieved

Popt,max ≈

28 W [57]. These

results are very similar to the 186

µm

eSAS SE metrics presented here, namely

ηE,peak

= 69%,

ηE

= 67

3% and 59

4% at 17 W and 27 W, respectively, and

Popt,max ≈

2 W. Optimized layer

structures at

= 955

(by Jenoptik [26]) and

∼

975

(by Optoenergy [58,59] and IPG

Photonics [60]) have enabled BAL SEs with

= 90–220

µm

to exhibit record

ηE,peak

values in

the 73–74% range. This corresponds to an advantage of 4–5 percentage points over the 940

eSAS SEs in this work, which can partially be explained by the aforementioned differences

in mounting configurations and measurement setups. Nonetheless, this

ηE

advantage is not

shown to enable higher

Popt

levels, with exemplary eSAS SEs exhibiting very similar

Popt,max

values. To sum up, it is shown that state-of-the-art electro-optic performance is successfully

demonstrated by eSAS BALs.

Characterization of beam quality and polarization purity

Proceeding to beam quality characterization, a comprehensive experimental study of 90

µm

SEs is first presented, which is mostly quoted from the author’s recent work [52]. “Figure 4.22

shows the near- and far-field intensity profiles and the corresponding beam parameters

W95%

and

θ95%

for an exemplary SE of each lateral design variant with

= 90

µm

at different

operating points (

Popt

= 2

5, 5, 7.5 and 10 W). Significant narrowing of the near field is

observed in both eSAS variants compared to the GG reference over the whole

Popt

range, due

to the reduced LCA. The eSAS-V1 SE follows roughly the same trend as the GG reference,

with a wide

W95%

at lower

Popt

levels that is strongly narrowed at the highest operating point

due to thermal lensing. Conversely, the eSAS-V2 SE exhibits a different tendency, with a

constant, narrow

W95%

over the whole

Popt

range, which is consistent with the presence of

index guiding [24]. In addition, the near-field profiles of the eSAS-V2 SE show weaker lateral

intensity modulation (i.e. less pronounced peaks) compared to the other variants, which is also

consistent with index guiding [108]. The obtained

W95%

values at

Popt

= 10 W correspond to

a narrowing of 15.4% for V2 and 13.2% for V1 relative to the reference.”

“In terms of far field, the reference and V1 SEs have similar

θ95%

values and no obvious trend

in the profiles over the whole

Popt

range, which is in agreement with previous results [83,93].

On the other hand, the V2 SE has a significantly wider

θ95%

at all

Popt

levels, which can

also be explained by index guiding. Overall, at

Popt

= 10 W, the eSAS-V2 SE has

BPPlat

mm·mrad

, compared to 3

mm·mrad

for the eSAS-V1 SE and 3

mm·mrad

for the

reference. These correspond to

Blat

values of 3.03, 3.27 and 2

88 W

(

mm·mrad

), respectively.

Both eSAS variants have thus demonstrated improved beam quality compared to the reference,

but despite stronger suppression of LCA at stripe edges, the improvement shown by the V2

variant (5

2%) is not as large as that shown by the V1 variant (13

5%), likely due to index

guiding.”

4. Enhanced Self-Aligned Lateral Structure (eSAS)

-100 -80 -60 -40 -20 0 20 40 60 80

100

-80 -60 -40 -20 0 20 40 60 80 -80 -60 -40 -20 0 20 40 60 80 100

-8 -6 -4 -2 0 2 4 6

-6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 6 8

Popt (W)

2.5

5.0

7.5

10.0

Intensity (a.u.)

Near-field position (µm)

W95% (µm)

112.29

119.92

120.02

96.14

Near-field position (µm)

W95% (µm)

96.99

109.62

111.15

83.47

Near-field position (µm)

W95% (µm)

81.08

81.56

87.02

81.33

eSAS-V2

GG Ref. eSAS-V1

Popt (W)

2.5

5.0

7.5

10.0

Intensity (a.u.)

Far-field angle (°)



95% (°)

5.20

6.29

7.00

8.28

Far-field angle (°)



95% (°)

4.98

5.71

6.52

8.39

Far-field angle (°)



95% (°)

6.39

7.71

8.68

9.31

Figure 4.22: Measured optical intensity at varying

Popt

levels (CW, 25

°C

) as a function of

near-field position (top) and far-field angle (bottom) for representative BAL SEs with

= 90

µm

= 4

and different lateral configurations (gain-guided reference, eSAS-V1, eSAS-V2). The

corresponding beam parameters W95% and θ95% are indicated in the legends (taken from [52]).

“To obtain reliable trends, near-field and far-field profiles are measured for a large number

of SEs (

≥

7of each variant) with

= 90

µm

at the 4 operating points mentioned above, and

are used to extract

W95%

and

θ95%

and subsequently calculate

BPPlat

. As shown in Fig. 4.23,

these parameters are then plotted as functions of ∆

TAZ

” (see section 2.3). “In terms of the

near field (Fig. 4.23(a)), the observed trends confirm the findings from the individual SE results

(see above). We additionally note that in V2 SEs, as well as in V1 SEs at the highest operating

point (

Popt

= 10 W,∆

TAZ

= 12

1 K),

W95%

is significantly smaller than

= 90

µm

. This is

consistent with strong longitudinal-lateral temperature variation [69], but it is unclear why this

would occur at low ∆

TAZ

levels in V2 SEs, so this remains a topic for further investigation. The

near-field behavior observed in eSAS-V2 SEs, namely narrow and roughly constant

W95%

with

increasing

Popt

and heat levels, can be exploited using SEs with large stripe widths for efficient

coupling into optical fibers. The far-field trends (Fig. 4.23(b)) are also in agreement with the

individual SE findings (see above). However, we observe that while

θ95%

is generally wider in

V2 SEs, it becomes more comparable to V1 and reference values at the highest operating point.

This may be evidence that as thermal lensing becomes stronger, it counteracts the built-in

index anti-guiding as estimated in subsection 4.1.3, resulting in improved beam quality, but

further studies are also necessary to confirm this.”

“The resulting

BPPlat

values, plotted in Fig. 4.23(c), directly demonstrate the improvement

in beam quality by using eSAS. We observe that V1 SEs tend to have the lowest (best) values

over the whole ∆

TAZ

range. V2 SEs also tend to exhibit lower values than GG reference

SEs, especially at higher operating points, despite their wider

θ95%

. Following [39,51], we

obtain further insight on the beam quality enhancement by applying linear fits to the

BPPlat

values and using the simple empirical model

BPPlat

BPP0

Sth ·

∆

TAZ

” (see section 2.3).

4.4 Device characterization and measurement results

0 2 4 6 8 10 12 14 16

100

105

110

115

120

125

130

GG Ref.

eSAS-V1

eSAS-V2

Lateral near-field width W95% (µm)

Active zone temperature increase ∆TAZ (K)

(a)

0 2 4 6 8 10 12 14 16

(b)

GG Ref.

eSAS-V1

eSAS-V2

Lateral far-field angle



95% (°)

Active zone temperature increase ∆TAZ (K)

0 2 4 6 8 10 12 14 16

(c)

GG Ref.

eSAS-V1

eSAS-V2

Lat. beam param. product BPPlat (mm·mrad)

Active zone temperature increase ∆TAZ (K)

Figure 4.23: Performance metrics extracted from measured near- and far-field beam profiles

(CW, 25

°C

) of

≥

7SEs of each lateral configuration (gain-guided reference, eSAS-V1, eSAS-V2):

(a)

W95%

, (b)

θ95%

, and (c)

BPPlat

as functions of ∆

TAZ

Pdiss ·Rth

. The SEs all have the same

dimensions (

= 90

µm

= 4

) and their beam profiles are measured at the same

Popt

levels:

2.5, 5, 7.5 and 10 W (taken from [52]).

“We observe that while

BPP0

is consistent in all three variants (2

mm·mrad

Sth

reduced from 0

149

mm·mrad/

Kfor the reference design to 0.124 for eSAS-V2 (17% reduction)

and 0.108 for eSAS-V1 (28% reduction). The

Sth

reduction results from the suppression

of LCA, which is not directly a thermal mechanism, but is nonetheless dependent on bias

current through the increasing carrier density at the stripe edges, which allows higher order

modes to reach threshold and be guided by the existing thermal lens [39,51,71]. This result is

consistent with [51], where a comparable

Sth

reduction was shown using deep ion implantation

through the active zone, at the cost of significantly reduced

Popt

and

ηE

. Using eSAS, we have

demonstrated here a significant reduction of Sth and BPPlat with no efficiency penalty.”

In the previous study, beam quality measurements of a large number of SEs were analyzed

to compare different lateral designs, with all SEs having a constant stripe width (

= 90

µm

This follow-up study focuses on beam quality variation with varying

. Since

Popt

scales

with

, comparisons at constant

Popt

levels would be non-ideal. Instead, following [106],

Popt

levels of SEs with different

are normalized by calculating the optical power density at the

4. Enhanced Self-Aligned Lateral Structure (eSAS)

0 2 4 6 8 10 12 14

Lateral brightness Blat (W/(mm·mrad))

Optical power density at front facet PDf (MW/cm2)

50 µm

90 µm

186 µm

Figure 4.24: Lateral brightness

Blat

Popt/BPPlat

), extracted from measured near- and far-field

beam profiles (CW, 25

°C

), as a function of optical power density at the front facet for three

representative eSAS-V1 SEs from the same wafer with W= 50, 90 and 186 µm, respectively, and

L= 4 mm.

front facet (PDf) as

PDf=Popt

Weff,x·Weff,y

=Popt ·[︄(∫︁Ix(x)dx)2

∫︁(Ix(x))2dx ·(∫︁Iy(y)dy)2

∫︁(Iy(y))2dy]︄−1

,(4.7)

where

(

)and

(

)are the near-field intensity profiles along the lateral and vertical axes,

respectively, and

Weff,x

and

Weff,y

are the corresponding effective beam widths. Figure 4.24

shows

Blat

as a function of

PDf

for three eSAS-V1 SEs from the same wafer, with

= 50, 90

and 186

µm

, respectively. For each SE, beam quality is measured at 9–10 different

Popt

levels,

aiming to identify the operating point with the highest

Blat

. It is found that higher peak

brightness is achieved by SEs with narrower

. More specifically, the 50

µm

SE exhibits the

highest

Blat

, namely 3

43 W

(

mm·mrad

)at

Popt

= 5

2 W. In comparison, the 90 and 186

µm

SEs exhibit peak values of 3.26 and 2

65 W

(

mm·mrad

)at 8.5 and 20 W, respectively. It is

also observed that the three SEs follow a broadly similar trend with increasing power density,

where

Blat

initially increases up to a peak value, which is reached at roughly the same power

density (10.3±0.35 MW/cm2), then starts to decrease beyond that point.

The last characterization step is evaluating the

DoP

of each BAL SE (as presented in

section 2.3) to determine the impact of the eSAS approach on the polarization purity of the

BAL output. Figure 4.25 shows the

DoP

of three representative 90

µm

SEs of each lateral

design variant at different operating points (

Popt

= 2

5, 5, 7.5 and 10 W). It is observed that

all SEs exhibit very high

DoP

between 98

5% and 99

6%, corresponding to predominantly

TE-polarized emission (i.e. high polarization purity). These

DoP

values remain broadly

constant over the whole operation range, with no consistent trend or significant change shown

with increasing

Popt

and heat levels. In addition, no significant difference is observed between

the eSAS variants and the GG reference, demonstrating that

DoP

degradation (due to strain

build-up at mechanical edges upon soldering) is effectively avoided in the eSAS. As discussed

in section 4.1, this is achieved by minimizing the blocking structure thickness (

dblock ≤

100

)

and thus the step height at the surface, in addition to selecting an ETAS vertical structure

4.4 Device characterization and measurement results

2.5 5.0 7.5 10.0

97.5

98.0

98.5

99.0

99.5

100.0

Degree of polarization DoP (%)

Optical power Popt (W)

GG Ref.

eSAS-V1

eSAS-V2

Figure 4.25: Measured

DoP

Popt,TE/

(

Popt,TE

Popt,TM

)) as a function of

Popt

(CW, 25

°C

) for

3 representative BAL SEs of each lateral configuration (gain-guided reference, eSAS-V1, eSAS-V2),

all with W= 90 µmand L= 4 mm.

variant with a relatively thick p-side sub-contact layer that shields the active zone from

potential strain build-up at the surface.

Finally, SEs from this work with exemplary beam quality and polarization purity metrics

are benchmarked against state-of-the-art SEs from the literature with comparable dimensions

(see section 3.1), analog to the PUI metric benchmarking provided above. They are first

compared to baseline SEs from the FBH, fabricated using one-step epitaxial growth and

standard processing techniques [61]. These baseline SEs (

= 90

µm

= 4

) are highly

comparable to the epitaxially regrown reference SEs in this work, since they also have a

gain-guided (GG) lateral configuration and an ETAS vertical structure. However, they use a

different ETAS variant, designed for operation at 970

rather than 940

. At

Popt

= 10 W,

the baseline SEs achieved

Blat ≈

3 W

(

mm·mrad

), along with values of

BPP0

= 1

mm·mrad

and

Sth

= 0

mm·mrad/

Kupon applying the empirical

BPPlat

–∆

TAZ

fit. The 90

µm

reference SE from Fig. 4.22 achieved a similar

Blat

= 2

88 W

(

mm·mrad

)at 10 W, and

fitting the results of

≥

7reference SEs (Fig. 4.23(c)) resulted in

BPP0

= 2

mm·mrad

and

Sth

= 0

149

mm·mrad/

K. It is observed that while

Sth

is almost identical,

BPP0

is significantly

higher for the reference SEs from this work. The comparison is then extended to eSAS-V1

SEs, also having the same dimensions. The exemplary 90

µm

eSAS-V1 SE from Fig. 4.22

exhibited

Blat

= 3

27 W

(

mm·mrad

)at 10 W, and the empirical fit values in Fig. 4.23(c) were

BPP0

= 1

mm·mrad

and

Sth

= 0

108

mm·mrad/

K. The eSAS approach is thus shown

to successfully improve

Blat

relative to standard baseline FBH BALs, due to a significant

Sth

reduction which is attributed to LCA suppression. On the other hand, it is shown to

have almost no impact on

BPP0

, with the fitted values for eSAS-V1 as well as eSAS-V2

SEs being very similar to their GG reference counterparts, and hence significantly higher

than the baseline FBH SEs from [61]. Previous experiments conducted at the FBH have

studied the impact of certain mechanisms on

BPP0

, demonstrating for example that it is

significantly increased by lateral index guiding [24]. However, even in comparable GG SEs

with similar dimensions and mounting configurations, different FBH studies over many years

(including this work) have shown strong variance in the background

BPP0

level between 0.8

4. Enhanced Self-Aligned Lateral Structure (eSAS)

and

∼

mm·mrad

[39,51,53,61]. Examining the results of these studies,

BPP0

appears to

have a consistent negative correlation with

(within the studied range), being lowest at

970

and highest at 910

, which suggests a certain dependence on the epitaxial structure.

The impact of different epitaxial structures (with constant

) on

BPPlat

has been studied in

various works [39,53,61,109], showing a clear trend of

Sth

dependence on the vertical thermal

conductivity profile. However, a consistent

BPP0

trend could so far not be identified, with

earlier studies showing very weak dependence [39,53,109], while a more recent study found a

relatively large difference of

∼

mm·mrad

between different epitaxial structures [61]. The

specific factors regulating

BPP0

thus remain largely unclear, requiring a detailed study to

identify them, which is proposed here as a topic for future research to enable further beam

quality enhancement.

Proceeding to the best recent results from other research groups, it is mentioned in

section 3.1 that 940

BAL SEs from JENOPTIK (

= 90

µm

= 4

) exhibited

θ95%≈

at 8 W and 11

at 11

5 W [54], with similar results reported in [26]. Using the

corresponding PUI characteristics and

Rth

= 1

8 K

W, it can be roughly calculated that the

∆

TAZ

values corresponding to these operating points (8 W and 11

5 W) are around 6

5 K and

5 K, respectively. The reported results can then be compared to Fig. 4.23(b), showing

θ95%

of SEs realized in this work, having the same

and

as their JENOPTIK counterparts.

It is observed that at comparable ∆

TAZ

levels, eSAS-V1 and GG reference SEs from this work

have a significant advantage over the JENOPTIK SEs, exhibiting narrower

θ95%

by about 2

on average. In another example, 915

BAL SEs from Optoenergy (

= 100

µm

, varying

)

achieved

Blat

= 2

79 W

(

mm·mrad

)from a 4

variant and 3

48 W

(

mm·mrad

)from a 6

variant. As presented earlier, very similar values have been obtained from exemplary eSAS-V1

SEs with

= 4

and

= 50, 90 and 186

µm

, achieving maximum

Blat

values of 3.43, 3.27

and 2

65 W

(

mm·mrad

), respectively. In terms of polarization purity, 955

BAL SEs from

JENOPTIK (

= 90

µm

= 4

) exhibited

DoP

= 98

5% at 12

5 W (i.e.

DoP ∗

= 97%;

see section 1.1) [26]. Similarly, 915

BAL SEs from Optoenergy (

= 180

µm

= 4

)

exhibited

DoP

= 98

4% on average, with an exemplary device maintaining

DoP ≈

99% up to

18 W [25]. As presented in Fig. 4.25, the

DoP

metrics exhibited by the SEs in this work, both

with and without the eSAS lateral structure, are equally good (or slightly better), with an

average

DoP

value of

∼

99% and a maximum value exceeding 99

4% at 10 W, that remains

broadly constant with varying Popt levels.

4.5 Overview and outlook

This section provides a brief summary of the eSAS lateral-structuring technique and its two

variants realized in this work, and the key experimental findings from characterizing SSM-

mounted BAL SEs (eSAS versus GG reference). These findings are compared to expected

performance trends from simulation and the literature, with the aim of providing an outlook

for the eSAS approach and highlighting potential topics for future studies.

The eSAS lateral design is based on a two-step epitaxial growth process, in which n-doped

current-blocking layers (GaAs on top of InGaP) are integrated within the p-side of an ETAS

vertical structure and selectively etched in the center before epitaxial regrowth. Current

4.5 Overview and outlook

flow is thus confined to a central stripe and blocked in the outer regions, with the aim of

reducing lateral current spreading and LCA. In the first variant (eSAS-V1), the blocking layers

have a total thickness of 60

and are integrated within the p-GaAs sub-contact layer, at

dres ≈

850

from the active zone. In the second variant (eSAS-V2), the blocking layers are

located within the p-Al0.8GaAs cladding layer, closer to the active zone (dres ≈250 nm), and

the current block is modified by reducing

ND,block

and adding thin undoped layers, thereby

replacing the p-n-p layer sequence with p-i-n-i-p and increasing the total thickness to 100

aiming to reduce band-to-band tunneling probability and improve current blocking. Higher

process complexity is involved in realizing eSAS-V2, in the form of an additional in situ

etching step that is necessary to avoid the exposure of Al

0.8

GaAs to air and the subsequent

performance degradation caused by rapid Al oxidation. Using this modified process, the

eSAS-V2 is successfully realized for the first time, with very low oxygen incorporation at

the etch-regrowth interface (measured using SIMS), representing the first reported etching

and regrowth within a material with such high Al content (80%). Following this work, the

capability to integrate laterally-patterned buried structures in such close proximity to the

active zone can be a valuable tool for future studies by enabling the realization of novel

designs for further performance enhancement. In terms of current-blocking capability, the

measured

Uon

(at

= 10

−3

/cm2

) of the V1 p-n-p block variant is up to 3

2 V, while the

V2 p-i-n-i-p variant exhibits

Uon

up to 4

2 V, consistent with the estimated improvement.

Although these measured

Uon

values are lower than expected from TeSCA simulations, they

nonetheless correspond to strong current blocking within the BAL operating voltage range (

lower than Jth by 8–9 orders of magnitude at Uth) and up to much higher voltage levels.

As expected, strong

Ith

reduction is successfully demonstrated in both eSAS variants

relative to the GG reference, proportional to the reduced current spreading. The estimated

increase due to stronger current confinement is observed (on average) upon testing a large

number of SEs, but is found to be very small in practice, therefore having a very limited

impact on

ηE

. Similarly, the slope (

) values in eSAS SEs are found to be slightly lower

(on average), but broadly comparable to their reference counterparts. However, this means

that the estimated

enhancement due to reduced current spreading and LCA could not be

experimentally demonstrated, which had been expected based on [72,73] as well as the TeSCA

simulation (Fig. 4.11(b)). As previously discussed, this suggests that the limiting factor for

is not LCA at stripe edges due to current spreading, but rather LCA at the front facet within

the stripe (towards the edges), caused by lateral SHB and strong thermal lensing due to LTV.

Experimental studies of the lateral carrier distribution, e.g. as subsequently performed at the

FBH [81,110], are therefore well-motivated, and efforts to address this limiting mechanism by

minimizing LCA within the stripe are proposed as a promising approach to increase

, thus

enabling higher

ηE

and

Popt,max

. In terms of

ηE

, eSAS SEs exhibit a higher peak by up to 1.5

percentage points, reaching up to 69%, which is largely attributed to the reduced

Ith

. However,

as current increases, this advantage diminishes gradually due to the slightly lower

, resulting

in a roughly equal

ηE

∼

65% at the operating point. In terms of

Popt,max

, eSAS SEs with

= 4

and

= 90

µm

have achieved 20

9 W, while broader SEs with

= 186

µm

have

achieved 27.2 W.

4. Enhanced Self-Aligned Lateral Structure (eSAS)

The expected beam quality enhancement (

BPPlat

reduction) due to reduced LCA is also

successfully demonstrated in both eSAS variants. It is found, however, that the

BPPlat

reduction is mostly attributed to near-field narrowing (smaller

W95%

), while the far-field angle

(

θ95%

) remains roughly unchanged by the central current and carrier confinement, meaning

that the reduction of far-field blooming could not be experimentally demonstrated. This

could also be explained by the aforementioned LCA within the stripe being the limiting factor

and preventing

θ95%

reduction, further motivating future studies on that topic (see above).

Contrary to expectation, the

BPPlat

reduction in eSAS-V2 is found to be smaller than in

V1, mostly due to wider

θ95%

, especially at lower

Popt

levels. This finding, along with other

observed trends, are consistent with the deep blocking layers inducing lateral index guiding,

which limits beam quality. Further efforts on optimizing the constituent materials and

dres

the current block in relation to the active zone and vertical intensity profile can therefore be

beneficial, as well as studies of the interplay between built-in index guiding and thermal lensing

in terms of ∆

neff

. Analyzing beam quality in terms of the empirical

BPPlat

–∆

TAZ

linear fit

shows that the heat- and bias-dependent slope term (

Sth

) is reduced in both eSAS variants,

while the heat- and bias-independent intercept term (

BPP0

) remains roughly unchanged. As

previously discussed, it is known that

BPP0

can be affected by packaging- or process-induced

waveguiding (e.g. index-guiding trenches), but strong

BPP0

variation has also been observed

among BALs with similar processing and packaging, appearing to correlate with other factors,

e.g. the emission wavelength (

). Future studies to identify the factors regulating

BPP0

and

techniques to minimize it are thus proposed here as a promising approach to reduce the overall

BPPlat

. The highest lateral brightness recorded in this work is attributed to an eSAS-V1 SE

with

= 4

and

= 50

µm

, exhibiting

Blat

= 3

43 W

(

mm·mrad

)at

Popt

= 5

2 W, while

the best 90

µm

eSAS-V1 SE has achieved 3

27 W

(

mm·mrad

)at 10 W, corresponding to a

5% improvement over the best comparable reference SE. Finally, very high polarization

purity is exhibited by both eSAS variants as well as the GG reference, with

DoP

in the

5%–99

6% range (

∼

99% on average). This demonstrates that the eSAS designs successfully

avoid strain build-up near the active zone, by minimizing current-blocking layer thicknesses and

thus mechanical step height at the surface, while having a relatively thick p-side sub-contact

layer to shield the active zone.

As detailed in the previous section, the

Popt,max

levels achieved by exemplary eSAS BAL

SEs under CW operation are the highest among comparable devices realized to date at the

FBH. The peak performance exhibited by exemplary eSAS SEs, in terms of

Popt,max

Blat

and

DoP

, is on the same level as state-of-the-art values reported in the literature, while

ηE

(peaking at 69%) is lower than reported record values by a few percentage points, which can

(partially) be explained by differences in mounting configurations and measurement setups.

Chip-Internal Thermal Path Engineering:

Design and Outlook

In section 3.2, a review of the most important thermal and non-thermal mechanisms that limit

BAL performance is provided. This is followed in section 3.3 by a literature review of notable

lateral structuring techniques, which primarily aim to eliminate two non-thermal performance-

limiting mechanisms, namely lateral current spreading and lateral carrier accumulation (LCA).

Chapter 4 then presents a detailed and comprehensive study of one such lateral structuring

technique, namely the enhanced self-aligned structure (eSAS), starting with design development

and optimization, followed by design realization and quality control, and finally test device

characterization and performance analysis.

While the aforementioned eSAS study constitutes the main part of this dissertation, efforts

to devise and develop other lateral design approaches were also undertaken over the course

of this work, with the aim of addressing other performance-limiting mechanisms. One such

approach is laterally-structured heat-blocking layers for chip-internal thermal path engineering,

which aims to reduce thermal lensing. Despite its conceptual similarity to the SAS/eSAS

approach (based on laterally-structured current-blocking layers), they can be considered

independent designs and can even be complementary, as they tackle different performance-

limiting mechanisms. This proposed design has produced promising results in simulation, but

is yet to be optimized and realized in a full wafer process, in order to obtain and characterize

test devices and reliably determine if the estimated performance benefits are achieved in

practice. This chapter serves to describe this lateral design approach and present the findings

obtained so far, with the purpose of motivating further research efforts on it in the future.

5.1 Motivation and prior art

Thermal lensing is a dominant cause of lateral beam quality degradation (higher

BPPlat

) due

to far-field blooming (higher

θ95%

) in high-power BALs under CW operation, as discussed in

subsection 3.2.1. It refers to increasingly stronger lateral waveguiding between the central and

outer regions of the BAL with increasing bias current as a result of self-heating (increasing

5. Chip-Internal Thermal Path Engineering: Design and Outlook

∆

TAZ

) under the injection stripe, which gives rise to a lateral temperature gradient and a

subsequently higher effective refractive index variation (∆neff).

Various design approaches can be employed to minimize thermal lensing and its detrimental

effect on beam quality. One approach is minimizing ∆

TAZ

under the stripe by reducing

Rth

This can be achieved, for example, by increasing

, which has been shown to significantly reduce

θ95%

and

BPPlat

for a given

Popt

level. On the other hand, increasing

has some drawbacks,

including higher

Ith

, stronger longitudinal SHB, higher realization cost as well as increased

sensitivity to bulk defects [11,66]. Experimental studies at the FBH have also shown that

vertical (epitaxial layer) structure variation has a significant impact on the lateral temperature

gradient and its dependence on self-heating under the stripe [53,109]. This was reproduced

and investigated in further detail using the FEA software “Ansys Mechanical” (see section 2.1),

demonstrating that the observed variation in lateral heat spreading is caused by differences in

the vertical thermal conductivity (k) profiles of the epitaxial layer structures [39,111].

It has also been shown in the literature that thermal lensing can be minimized using lateral

design approaches, with no changes to the device dimensions or layer structure. One approach

is laterally structuring the p-side metallization, with metal layers replaced outside the stripe by

low-

materials (e.g. air or other insulators), with the aim of limiting heat dissipation outside

the stripe and confining heat flow to a central thermal path [11,66,112]. This has the benefit

of flattening the lateral temperature profile within the active zone, resulting in reduced ∆

neff

and thus lower

θ95%

and

BPPlat

. On the other hand, it has the drawback of increasing the

overall

Rth

and ∆

TAZ

, leading to lower

and thus lower

Popt

and

ηE

at a given bias current.

Nonetheless, this approach has been demonstrated to significantly enhance lateral brightness

(Blat) at a given Popt level.

However, experimental studies based on thermal camera imaging of standard BALs have

shown evidence of a substantial thermal barrier at the p-side semiconductor–metal interface

which limits heat transfer out of the semiconductor device, thus limiting the expected impact

of design changes outside it [38,113]. It follows that lateral structuring of semiconductor

layers within the device and replacing them outside the stripe with heat-blocking layers made

of lower-

materials, with the aim of engineering an internal thermal path, is a promising

alternative which can enable more significant beam quality enhancement [114].

5.2 Thermal simulation model

This approach is investigated here by performing thermal simulations using Ansys, following

the techniques described in [38,39] and summarized in section 2.1. As an initial state for

the simulation, the generated heat under given operating conditions, which is calculated as

Pdiss

I·U−Popt

(see section 2.3), is appropriately distributed along the vertical layer structure,

including the epitaxial layers as well as the metallization and submount. Following [24,38],

it is assumed that three heating mechanisms contribute exclusively to

Pdiss

, namely Joule

heating (

PJoule

RsI2

), non-radiative recombination within the active zone (

Prec

U0Ith

and optical absorption (

Pabs

Pdiss −PJoule −Prec

). Within each layer, the area under the

stripe is modeled as a uniform heat source, with its thermal power density (

qth,j

) defined as

5.2 Thermal simulation model

0 50 100 150 200 250

Temperature (°C)

Vertical position (µm)

Thermal camera

Ansys

Ansys (+ barrier)

(a)

-250 -200 -150 -100 -50 0 50 100 150 200 250

Temperature (°C)

Lateral position (µm)

Thermal camera

Ansys

Ansys (+ barrier)

(b)

Figure 5.1: Comparison of experimental (thermal imaging) results of a p-down-mounted BAL

chip (

= 90

µm

, CW,

Popt

= 10 W) taken from [38], to Ansys thermal simulation results, with

and without an added thermal barrier layer at the p-side semiconductor–metal interface, in terms of:

(a) Temperature as a function of vertical position along the chip, with a dotted green line indicating

the thermal barrier, and (b) temperature as a function of lateral position in the plane of the active

zone, with magenta lines indicating the quadratic fit curves applied within

. The simulated

profiles are spatially averaged over ±5µmto match the limited thermal camera resolution.

the sum of contributions of these heating mechanisms, i.e.

qth,j =qJoule,j +qrec,j +qabs,j.(5.1)

For each layer, these contributions are calculated as follows:

qJoule,j =PJoule

WL ·ρj

∑︁j(djρj)(5.2)

qrec,j =









Prec

WL ·dAZ

(within AZ)

0(outside AZ)

(5.3)

qabs,j =Pabs

WL ·dj·Γjαj

∑︁j(Γjαj),(5.4)

where

ρj

,Γ

and

αj

correspond to layer thickness, resistivity, optical confinement factor

and optical absorption coefficient, respectively, and

dAZ

is the active zone thickness. The

assumption that heat generation is uniform under the stripe and limited to its width (

) is

made for simplicity, and excludes the influence of mechanisms such as lateral current spreading

and carrier diffusion as well as the non-uniformity of lateral optical intensity profiles. To finalize

the simulation model, a constant

THS

of 25

°C

is assumed at the bottom of the submount, and

a convective heat transfer coefficient of 5 W

2·

K) is assumed at the external surfaces of the

mounted chip which are in contact with static air [38].

5. Chip-Internal Thermal Path Engineering: Design and Outlook

Before introducing lateral design changes, it is important to calibrate this simulation

model and ensure that it is capable of reproducing measured temperature profiles (obtained

from thermal camera images) with reasonable accuracy. To this end, measured vertical and

lateral temperature profiles (taken from [38]) are plotted in Fig. 5.1, which are obtained

by imaging mid-infrared (MIR) thermal radiation from the front facet of a representative

p-down mounted BAL chip with

= 90

µm

under CW operation at

Popt

= 10 W. Ansys

thermal simulations are then carried out for an equivalent BAL chip with the same epitaxial

structure, mounting configuration, and operating conditions, and the resulting vertical and

lateral profiles are compared to their measured counterparts. It is important to note that the

long wavelength of the MIR radiation limits the spatial resolution of the thermal camera to

8–10 µm[38,109], meaning that for a valid comparison, simulated profiles should be spatially

averaged accordingly. Following [38], simulated lateral profiles are thus averaged over a

µm

vertical range around the AZ, while vertical profiles are smoothed using a moving average.

In Fig. 5.1(a), the measured vertical profile shows a large temperature step at the p-side

semiconductor–metal interface, corresponding to the aforementioned thermal barrier, with a

thermal boundary (Kapitza) resistance of about 7

−6

2·

W, equivalent to a thermal

boundary conductance of 0

MW/

2·

K). It is found that to reproduce this temperature

step in Ansys, the thermal barrier has to be included in the device model by adding a layer

with high thermal resistance (

∼

85 K

W) at the p-side semiconductor–metal interface. As

shown in Fig. 5.1(b), the added thermal barrier layer also results in a good agreement between

the measured and simulated lateral profiles in terms of the maximum temperature at the stripe

center (

Tmax

), but the measured profile is significantly broader. This broadening is explained

by the propagation of the MIR thermal radiation within the device, and is thus an artifact of

the imaging technique which is not accounted for in the simulation [109]. Upon adding the

thermal barrier layer to the simulation, the calculated

Rth

value (as defined in section 2.3,

with

TAZ

Tmax

) of the mounted BAL chip increases from 1.65 to 2

5 K

W, thus matching

the value obtained from experiment [38,113].

5.3 Thermal simulation results and analysis

Using the calibrated Ansys model, the proposed lateral design approach with heat-blocking

layers outside the stripe can then be simulated, in order to estimate its impact on thermal lensing

and beam quality. To quantify thermal lens curvature in the simulated lateral profiles within

the active zone, a quadratic fit function (

(

) =

B2x2

B1x

) is applied within

µm

from the stripe center, i.e. within the stripe with

= 90

µm

as indicated in Fig. 5.1(b). The

magnitude of the quadratic fit parameter (

|B2|

), referred to as the bowing factor, is subsequently

used as a measure of thermal lens curvature. This is almost identical to the method used in

earlier FBH studies [38,39,109], with the only difference being that

calculation is limited

instead of extending beyond it. This is necessary for investigating this design, whose

primary objective is confining heat under the stripe and minimizing its flow and dissipation in

the outer regions. Many variants of the proposed lateral design are simulated, in which various

low-

materials replace either the p-side contact layer only, or the p-side contact and cladding

layers, as shown in Fig. 5.2. In the used vertical structure, the p-GaAs contact layer has a

5.3 Thermal simulation results and analysis

n-substrate (GaAs)

n-cladding (AlGaAs)

n-waveguide (AlGaAs)

p-waveguide (AlGaAs)

active zone

p-cladding (AlGaAs)

p-contact (GaAs)

p-side metallization

solder (AuSn)

submount (CuW)

n-side metallization

thermal barrier

heat block (low k)

Figure 5.2: Schematic transverse cross section of a p-down-mounted BAL chip with heat-blocking

layers replacing the p-side contact and cladding layers outside the central stripe. The stripe width

(

), emitted optical beam, heat flow paths, and thermal barrier location are indicated on the

diagram (adapted from [114]).

thickness of 1

µm

with

= 45 W

K), while the p-cladding consists of multiple Al

1−x

layers with a total thickness of 660

and an average

of 18 W

K), meaning that their

combined average

∼

3 W

K) [40]. The following low-

materials are used to replace

them in the outer regions and act as heat-blocking layers:

–In0.48Ga0.52P: lattice-matched to GaAs, k= 5.16 W/(m·K) [40]

–

Superlattice (SL) of thin alternating In

0.48

0.52

P and In

0.34

0.66

0.3

0.7

layers

(5.16 and 4.31 W/(m·K), respectively): both lattice-matched to GaAs [40], kestimated

as half the expected average bulk value due to phonon scattering at the numerous SL

interfaces [115], i.e. estimated k= 2.37 W/(m·K)

–Air:k= 0.026 W/(m·K) [116]

The resulting lateral temperature profiles are shown in Fig. 5.3(a) for the case of laterally-

structured p-contact and cladding layers, demonstrating the reduction in thermal lens curvature

within the stripe with decreasing

of the heat-blocking material, which replaces the reference

GaAs and AlGaAs in the outer regions. The corresponding

|B2|

values are plotted in Fig. 5.3(b),

showing a reduction of 13% using InGaP, 17% using an InGaP/InGaAsP superlattice, and 73%

using air. The figure also includes the |B2|values for the structured p-contact case (i.e. with

p-AlGaAs cladding layers unchanged), which follows the same trend but has a smaller impact

|B2|

, with reductions of 10%,13% and 65%, respectively. Despite being less effective, the

latter variant with the structured p-contact could be preferable in practice, in order to avoid

the increased process complexity associated with laterally structuring an AlGaAs layer, as

well as the possibility of inducing undesired lateral index guiding (see chapter 4).

As previously mentioned, the reduction of thermal lens curvature (i.e.

|B2|

reduction)

is associated with reduced beam quality degradation (i.e. lower

BPPlat

) [11,53,66,109]. It

can thus be estimated from these simulation results that the approach proposed here could

effectively enhance beam quality. However, like other lateral design approaches (see section 3.3),

5. Chip-Internal Thermal Path Engineering: Design and Outlook

-40 -30 -20 -10 0 10 20 30 40

-6

-5

-4

-3

-2

-1

∆Tlat = T - Tmax (K)

Lateral position (µm)

GaAs + AlGaAs (Ref.)

InGaP

InGaP/InGaAsP SL

Air

Material

(p-contact + p-cladding)

(a)

0.01 0.1 1 10 100

100

Air

InGaP

Normalized |B2| (%)

Thermal conductivity k (W/(m·K))

Epitaxial layers

p-contact

p-contact + p-cladding

Ref.

(b)

Figure 5.3: Ansys simulation results (

THS

= 25

°C

) of BALs (

= 90

µm

, CW,

Popt

= 10 W) with

laterally-structured heat-blocking layers (outside the stripe) made of varying materials, compared

to reference BALs in terms of: (a) Temperature difference ∆

Tlat

(relative to the central maximum

Tmax

) as a function of lateral position within the active zone for the case of structured p-contact

and cladding layers, and (b) bowing factor

|B2|

(normalized to reference) as a function of thermal

conductivity kof the heat-blocking layers replacing p-side epitaxial layers outside the stripe.

it also has various drawbacks and implementation challenges. For example, Fig. 5.3 shows that

using air as the heat-blocking material outside the stripe, corresponding to etching a broad-area

mesa, is most effective in reducing

|B2|

(65%–73%) due to the large

contrast. However, even

if strong lateral index guiding is avoided, the structured BAL surface with large step height is

likely to accumulate external strain at mechanical edges during processing or mounting, leading

to significant degradation of polarization purity [24,25] (see sections 3.2 and 3.3). Moreover,

the large

contrast is accompanied by a

Rth

increase from 2.5 to

∼

5 K

W, but as discussed

above for the chip-external approach, the

BPPlat

benefit from flattening the thermal lens is

estimated to be larger than the

Popt

penalty due to the

Rth

increase, thereby resulting in

enhanced Blat at a given Popt level.

In the alternative case of using two-step epitaxial growth to replace the epitaxial layers out-

side the stripe with low-

lattice-matched materials (e.g. In

0.48

0.52

P or In

0.34

0.66

0.3

0.7

additional processing steps would be necessary to selectively remove the unwanted regrown

material and flatten the BAL surface. Along with the estimated beam quality benefit, this

increase in process complexity must also be taken into consideration. To maximize the

beam quality benefit, it is clear that a lateral

contrast as large as possible is desirable.

To the author’s knowledge, the

values of the materials used here (e.g. 4

31 W

K) for

0.34

0.66

0.3

0.7

) are among the lowest for ternary and quaternary semiconductors that

are lattice-matched to GaAs [40]. While these

values are an order of magnitude lower than

GaAs, they are over two orders of magnitude higher than air, resulting in their smaller impact

|B2|

(10%–14% reduction). As mentioned above, a superlattice of thin alternating materials

is estimated to have a reduced

of roughly half the average bulk value of the materials,

as a result of phonon scattering at the interfaces [115]. Ansys results show that using an

InGaP/InGaAsP superlattice would further reduce

|B2|

, but not by more than 3–4 percentage

points, since the

of the resulting superlattice is still on the same order of magnitude as its

5.3 Thermal simulation results and analysis

constituent materials. Although using InGaP and/or InGaAsP does not reduce

|B2|

as much

as using air, the moderate

contrast has the benefit of maintaining low

Rth

, with a negligible

increase ≤0.05 K/Wrelative to a reference BAL, which corresponds to an estimated BPPlat

reduction with no Popt or ηEpenalty.

Other alternatives for the heat-blocking material include etching air holes (with specific

depth, diameter and pitch) through the layer structure outside the stripe, such that the

outer regions resemble a photonic crystal [117]. Such photonic crystals have reduced

, due

to the introduction of air as well as numerous semiconductor–air interfaces. As proposed

in [112], further alternatives are porous oxides or nitrides, e.g. highly-porous SiO

produced

using a “sol–gel” (solution to gel) method. These porous insulators can be made to have

very low

values, comparable to or even lower than air, while maintaining high mechanical

stability [112,118]. While the methods required for practical realization of such laterally-

structured porous insulators are compatible with semiconductor technology, they involve many

additional processing steps and thus increase process complexity and cost.

Summary and Conclusion

GaAs-based broad-area diode lasers (BALs) operating in the 9xx

wavelength range offer

the highest optical power (

Popt

) among semiconductor diode lasers and the highest power

conversion efficiency (

ηE

) among all light sources, and are therefore widely used in material-

processing applications such as metal cutting and welding. In addition to high efficiency, these

applications require high beam quality and brightness, which are typically limited in BALs

along the lateral axis, i.e. relatively high lateral beam parameter product (

BPPlat

) limiting

lateral brightness (

Blat

Popt/BPPlat

). Efforts to realize BALs with ever-higher

Popt

ηE

and

Blat

are thus highly beneficial for the material-processing industry, in addition to enabling new

applications. To this end, multiple aspects of BAL performance have to be simultaneously

optimized, including threshold current (

Ith

), power-current slope (

), series resistance (

thermal resistance (

Rth

), degree of polarization (

DoP

), as well as lateral near-field width

(W95%) and far-field angle (θ95%) with 95% power content.

Studies over many years have identified the thermal and non-thermal mechanisms that

limit BAL performance, and various design approaches have been employed to minimize their

negative impacts. Each approach has its benefits and drawbacks, usually involving a trade-off

between different performance aspects, with process complexity also being an important

variable. This dissertation focuses on design approaches based on lateral structuring, which are

implemented to address performance-limiting mechanisms along the lateral axis; specifically

lateral current spreading, lateral carrier accumulation (LCA) and thermal lensing. After a

state-of-the-art literature review, novel lateral designs are developed and realized, aiming to

overcome limitations and achieve performance enhancements in BALs without compromising

other performance aspects.

The first novel design is the enhanced self-aligned structure (eSAS), which uses a two-step

epitaxial growth process to integrate laterally-structured n-doped layers within the p-doped

side of the BAL to block current flow outside the central stripe, with the aim of reducing

lateral current spreading and LCA. It is an improved version of the established self-aligned

structure (SAS) design, with optimized current-blocking layers for improved process control

and repeatability, and a well-suited epitaxial structure that enables a small residual thickness

between the active zone and the current block, thus maximizing its benefits, without degrading

other performance aspects. Two eSAS design variants (eSAS-V1 and eSAS-V2) are developed

6. Summary and Conclusion

and implemented in this study (wavelength

= 940

), varying primarily in terms of the

residual thickness. Whereas the blocking layers in eSAS-V1 are located within the p-GaAs

(sub-)contact layer, increased process complexity (in the form of an additional in situ etching

step) is used in eSAS-V2 to realize the structured blocking layers closer to the active zone,

namely within a p-Al

0.8

GaAs cladding layer, representing the first reported lateral structuring

(etching followed by epitaxial regrowth) within a material with such high Al content. The first

step towards the realization of these eSAS variants is using device modeling and simulation tools

for design development and optimization, which is then followed by device fabrication in trial

and full wafer processes. Various quality control tests are then carried out to verify the correct

implementation, analyze the structural quality, and test the current-blocking capability in each

eSAS design variant. In terms of current blocking, both variants have demonstrated strong

blocking capability within and beyond the BAL operating voltage range, with eSAS-V2 showing

improved blocking using a modified blocking structure with reduced n-doping and additional

thin undoped layers (p-i-n-i-p configuration) to minimize band-to-band tunneling probability.

Alongside the processed eSAS BALs, gain-guided reference BALs are also processed on the

same wafers for a fair comparison. After facet passivation and coating, single BAL emitters

(SEs) of each lateral configuration (gain-guided, eSAS-V1, eSAS-V2) with 4

resonator

length and varying stripe widths are mounted on standard submounts and characterized under

continuous-wave operation at 25

°C

. Measurement results of a large number of SEs have shown

significant performance enhancements in eSAS BALs relative to their reference counterparts,

namely reduced

Ith

resulting in higher peak

ηE

by up to 1.5 percentage points and reduced

W95%

resulting in higher

Blat

by up to 13

5%, while maintaining very high

DoP

and roughly

unchanged

and

θ95%

. Some of the estimated eSAS performance benefits could thus be

experimentally demonstrated (

Ith

and

W95%

reduction) while others could not (

increase

and

θ95%

reduction). This suggests that the limiting mechanism for

and

θ95%

is not LCA

at stripe edges due to current spreading, which was shown here to be strongly suppressed,

but rather LCA within the stripe at the low-reflectivity front facet, corresponding to the

non-uniform temperature and carrier density profiles along the lateral and longitudinal axes

at high bias levels. It was also demonstrated that no penalties in terms of

DoP

were

introduced by implementing either eSAS variant. Overall, the first successful realizations of

the eSAS lateral design have resulted in BALs which exhibit state-of-the-art performance,

demonstrating simultaneously high

ηE

(up to 69%),

Blat

(up to 3

43 W

(

mm·mrad

)) and

DoP

(

∼

99% on average) up to high

Popt

levels. An overview of the eSAS study and its experimental

findings, highlighting related topics proposed for future studies, is provided in section 4.5.

The second novel design is based on centrally confining the flow of heat, rather than

current, by engineering a chip-internal thermal path under the central stripe and minimizing

heat dissipation outside it, with the aim of reducing thermal lensing (i.e. flattening the

lateral temperature profile) and thus minimizing the associated beam quality degradation.

In p-down-mounted BALs, this is realized by laterally structuring p-side epitaxial layers,

replacing them outside the stripe with materials with low thermal conductivity (

) that block

heat flow. In prior studies, a similar approach was implemented outside the semiconductor

chip, i.e. by laterally structuring the p-side metallization, exhibiting significantly enhanced

Blat

despite increased

Rth

leading to reduced

Popt

and

ηE

at a given bias. However, recent

studies based on thermal imaging have shown evidence of a substantial thermal barrier at the

p-side semiconductor–metal interface, which limits heat dissipation into the metallization and

thus reduces the estimated impact of chip-external design changes, therefore motivating the

aforementioned chip-internal approach. Many lateral design variants are investigated in this

work, with varying p-side epitaxial layers replaced with varying low-

materials, including

ternary and quaternary semiconductors, e.g. InGaP and InGaAsP (lattice-matched to GaAs),

as well as air (i.e. a mesa configuration). To estimate the benefit of each variant, a two-

dimensional thermal simulation based on finite element analysis is carried out, using a detailed

device model including semiconductor layers as well as metallization and packaging, with an

initial state based on calculating the heat generated within each layer and modelling the area

under the stripe as a heat source. After calibrating the simulation model against experimental

(thermal imaging) results of a gain-guided reference BAL, the different lateral design variants

are compared to the reference in terms of the simulated thermal lens bowing (

|B2|

) close to

the active zone, obtained from a quadratic fit of the lateral temperature profile within the

stripe, with

|B2|

reduction associated with improved beam quality (reduced

BPPlat

) based on

previous experimental studies. It is found that using air as the heat-blocking material, the

very large

contrast between central and outer regions results in strong

|B2|

reduction by

up to 73%, coming at the expense of increased

Rth

(see above) as well as the risk of strain

accumulation at the large surface steps leading to

DoP

degradation. A smaller

contrast

using InGaP results in

|B2|

reduction by up to 13%, which can be improved by 4 percentage

points by using a superlattice of alternating InGaP and InGaAsP layers, with the

Rth

penalty

being negligible in both cases. However, the drawback of such variants would be the increase

in process complexity associated with two-step epitaxial growth and subsequent processing

steps for surface flattening. Other alternatives for low-

materials include etching deep air

holes through the layer structure (resembles a photonic crystal), as well as porous oxides or

nitrides, which can provide very high

contrast (comparable to air) and high mechanical

stability but likely require even higher process complexity. In summary, the novel lateral

design with structured heat blocking has exhibited promising results in finite-element thermal

simulations, with a significant estimated reduction of thermal lensing. However, it is yet to

be optimized and practically realized to determine if its estimated beam quality benefits are

experimentally demonstrated, so this is proposed here as a promising topic for future studies.

List of Figures

1.1 Metrics and future trends of the global laser device market . . . . . . . . . . . 2

1.2 3-D schematic diagram of standard BAL and output laser beam . . . . . . . . . 3

2.1 GaAs wafer inside MOVPE reactor . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Processed wafer with multiple test fields & test field with multiple bars . . . . 13

2.3 Schematic diagram of adjacent BAL emitters after wafer processing . . . . . . . 14

2.4 Bar of BAL emitters after cleaving & single-emitter (SE) chip mounted on SSM 15

3.1 PUI characteristics of recent standard FBH BALs at 970 and 935 nm ...... 21

3.2 Lateral current spreading and lateral carrier accumulation (LCA) . . . . . . . . 24

3.3 Lateral structuring techniques: deep ion implantation and index trenches . . . 27

3.4 Lateral structuring techniques: RISAS and SAS . . . . . . . . . . . . . . . . . . 28

3.5 Lateral structuring techniques: BM and LBI . . . . . . . . . . . . . . . . . . . . 30

4.1 Refractive index and mode intensity profiles in ETAS vertical structure . . . . 35

4.2 Simulated current blocking in V1 block variants . . . . . . . . . . . . . . . . . . 36

4.3 eSAS-V1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4 Simulated lateral waveguiding in eSAS-V1 . . . . . . . . . . . . . . . . . . . . . 38

4.5 Sim. current blocking & lateral waveguiding with varying dres in V2 p-n-p block 39

4.6 Simulated energy band diagrams at varying bias voltages in V2 p-n-p block . . 41

4.7 Sim. tunneling current density & current blocking in V2 block variants . . . . . 42

4.8 eSAS-V2 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.9 Simulated lateral waveguiding in eSAS-V2 . . . . . . . . . . . . . . . . . . . . . 43

4.10 Simulated current spreading at Ith &Ith reduction in eSAS variants . . . . . . 45

4.11 Sim. current spreading at high bias & PUI characteristics in eSAS variants . . 46

4.12 SEM images of eSAS-V1 BALs . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.13 Measured vs. simulated V1 p-n-p current blocking . . . . . . . . . . . . . . . . 48

4.14 SEM images of eSAS-V2 BALs . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.15 TEM images of eSAS-V2 BALs (1) . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.16 TEM images of eSAS-V2 BALs (2) . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.17 SIMS measurement of oxygen incorporation in eSAS-V2 . . . . . . . . . . . . . 53

4.18 Measured vs. simulated V2 p-i-n-i-p current blocking . . . . . . . . . . . . . . . 54

4.19 Measured PUI and spectral characteristics in eSAS variants (W= 90 µm) . . . 56

4.20 Analysis of (experimental) Ith,S1&S2in eSAS variants (varying W) . . . . . 58

4.21 Measured PUI characteristics of eSAS-V2 SEs (varying W) up to Popt,max . . . 59

LIST OF FIGURES

4.22 Measured near-field and far-field profiles in eSAS variants (W= 90 µm) . . . . 62

4.23 Analysis of (experimental) W95%,θ95% &BPPlat in eSAS variants (W= 90 µm) 63

4.24 Analysis of (experimental) Blat in eSAS-V1 SEs (varying W) .......... 64

4.25 Measured DoP in eSAS variants (W= 90 µm) .................. 65

5.1 Meas. vs. sim. vertical & lateral temp. profiles in p-down-mounted BAL chip . 71

5.2

Schematic diagram of p-down-mounted BAL chip with lateral heat-blocking layers

5.3 Sim. impact of p-side lateral heat blocking (varying k) on thermal lens bowing 74

List of Tables

3.1 Key metrics of state-of-the-art 9xx nm BAL SEs (CW, 25 °C, passive cooling) . 20

4.1 Extreme-triple-asymmetric (ETAS) epitaxial layer structure (simplified) . . . . 34

4.2

Averaged metrics from measured PUI & spectrum in eSAS variants (

= 90

µm

)

4.3

Key metrics from PUI measurement of eSAS-V2 SEs (varying

) up to

Popt,max 60

Symbols and Acronyms

αiinternal optical loss

Γoptical confinement factor

ηdexternal differential quantum efficiency

ηEpower conversion efficiency

ηE,peak power conversion efficiency (peak)

ηiinternal differential quantum efficiency

θ95% far-field angle (with 95% power content)

λemission wavelength

λccentroid wavelength

BAL broad-area diode laser

|B2|thermal lens bowing factor

Blat lateral brightness

BPPlat lateral beam parameter product

BPP0intercept term of BPPlat vs. ∆TAZ linear fit

COMD catastrophic optical mirror damage

CW continuous-wave

dAZ active zone thickness

dblock total thickness of current block

dres residual thickness between active zone and

current block

DoP degree of polarization

Eelectric field

Egband-gap energy

eSAS enhanced self-aligned structure

FBH Ferdinand-Braun-Institut gGmbH, Leibniz-

Institut für Höchstfrequenztechnik

FF far field

gmmaterial gain

gth threshold gain

GG gain-guided

Icurrent

Ith threshold current

Ith,0 empirical estimate of current loss at threshold

Jcurrent density

Jbbt band-to-band tunneling current density

Jth threshold current density

kthermal conductivity

kBBoltzmann constant (∼1.381 ×10−23 J/K)

Lresonator length

LCA lateral carrier accumulation

LTV longitudinal temperature variation

ND,block n-doping concentration of current block

Nth threshold carrier density in active zone

neff effective refractive index

∆neff lateral effective refractive index step

NF near field

Pdiss dissipated (thermal) power

Popt optical power

Popt,max optical power (maximum)

Pbbt band-to-band tunneling probability

PBC polarization beam combining

PUI power-voltage-current

qelementary charge (∼1.602 ×10−19 C)

QW quantum well

Rffront-facet reflectivity

Rrrear-facet reflectivity

Rsseries resistance

Rth thermal resistance

Sslope of power-current curve

Sth slope term of BPPlat vs. ∆TAZ linear fit

SAS self-aligned structure

SE single emitter

SEM scanning electron microscopy

SHB spatial hole burning

SIMS secondary ion mass spectrometry

SSM screening submount

TAZ active-zone temperature

∆TAZ active-zone temperature increase

THS heat-sink temperature

TE tranverse electric

TEM transmission electron microscopy

TM transverse magnetic

Uvoltage

U0turn-on voltage

Uth bias voltage corresponding to Jth

Wstripe width

W95% near-field width (with 95% power content)

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