Document [original]

FAKULTÄT FÜR

ELEKTROTECHNIK,

INFORMATIK UND

MATHEMATIK

Identification and Simulation of Critical

Interconnect Paths with Respect to

Transient Noise on PCB-Level

Zur Erlangung des akademischen Grades

DOKTORINGENIEUR (Dr.-Ing.)

der Fakultät für Elektrotechnik, Informatik und Mathematik

der Universität Paderborn

vorgelegte Dissertation

von

Dipl.-Ing. Mohamed Taki

Paderborn

Referent: Prof. Dr.-Ing. Ulrich Hilleringmann

Korreferent: Prof. Dr. Wilfried Hauenschild

Tag der mündlichen Prüfung: 08.10.2008

Paderborn, den 19.11.2008

Diss. EIM-E/245

Aknowledgements

This thesis could not have been possible without the support and encouragement of num-

ber of people and organizations. I’m very gratefully to everybody who contributed to the

success of this enormous task.

This dissertation was carried out while I was working as a Research Engineer in the

department of Advanced System Engineering (ASE) at Fraunhofer IZM Paderborn and at

the Department of Electrical Engineering and Information Technology (EIM), University

of Paderborn.

First of all, I would like to thank cordially my supervisor Prof. Dr.-Ing. Ulrich Hiller-

ingmann for his interset, irreplaceable technical and human support. His remarks have

helped me to improve the structure of this thesis. I also would like to thank Prof. Dr.

Wilfried Hauenschild as a second supervisor for his support and encouragement. I am

very grateful that he managed to get financial support for my participations into several

conferences for presenting many parts of the work presented here.

I would also like to thank the other examining committee members, Prof. Dr.-Ing. Ulrich

R¨uckert, Prof. Dr.-Ing. Bernd Henning, Prof. Dr.-Ing. Rolf Schuhmann, and Prof. Dr.-

Ing. Andreas Thiede for their interest and commitment to review this work as well as

their useful comments and advice.

In particular I would like to thank Mr. John Hershberger and Professor Subhash Suri for

providing me the data structure of their efficient algorithm. Their support helped me to

save a huge amount of time during my research.

Special thanks go to Dr. Christian Hedayat, Mr. Uwe Keller and Dr. Peter Kralicek

for their guidance, encouragement, and technical discussions. Uwe Keller and Dr. Pe-

ter Kralicek never hesitated to enter discussions on questions related to my task within

the project MEDEA+ MESDIE. In addition to this role during the project MEDEA+

PARACHUTE, Dr. Christian Hedayat orgnized me the perfect work environment indis-

pensable to complete this dissertation. I would further like to thank Dr. Werner John

not only for giving me the opportunity to work in his department and pursue a doctorate

degree, but also for his encouragement.

Finally, I am grateful to all my colleagues for the friendly atmosphere, especially Christo-

pher Wiegand for his support concerning L

EX problems as well as Patrick RC Dickinson

for reading some parts of this manuscript and his precious remarks and corrections re-

garding my English language.

Paderborn, 19th November 2008 Mohamed Taki

Abstract

In this thesis an efficient approach to identify and evaluate the critical transient noise paths

on printed circuit board level is presented. This approach is based on the determination

of the flow of the noise power induced into a system of interconnects and distributed to

any sensitive integrated circuit device ports. The noise paths may result from all coupling

mechanisms between the transmission structures. Moreover, the noise paths are extracted

considering the entire printed circuit board.

Dominant and critical signal traces transferring significant noise from a specified noise

source to digital device I/O ports can be determined in the frequency domain using

advanced and efficient kshortest path algorithms. These are then combine with the signal

flow graph circuit matrix to compute the transfer function of the individual weighted signal

paths. The noise paths are evaluated in terms of the transmission coefficients over the

frequency range of interest. The superimposition of several dominant signal paths delivers

a good approximation to the total system response.

The associated coupling waveform can be computed by analyzing the whole dominant

signal paths, including device drivers and receivers, in the time domain. This can be

performed using a hybrid analysis like the harmonic balance technique or the S-parameter

analysis. Depending on the component noise margin the path can be identified as critical

or not. The approach proposed is able to predict the interconnects responsible for majority

of signal degradations at the chip ports. Based on this information protection measure

may be introduced to improve the printed circuit board design and develop more reliable

circuits.

Contents

Aknowledgements i

Abstract iii

Abbreviations and Symbols ix

1 Introduction 1

1.1 Statement of The Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 State of The Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Susceptibility and Immunity of Electronic Devices 5

2.1 EM Disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Electromagnetic Interference Model . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Electromagnetic Interference Sources . . . . . . . . . . . . . . . . . 6

2.2.2 Coupling Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.2.1 Capacitive Coupling Paths . . . . . . . . . . . . . . . . . . 7

2.2.2.2 Inductive Coupling Paths . . . . . . . . . . . . . . . . . . 7

2.2.2.3 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2.4 Galvanic Coupling Paths . . . . . . . . . . . . . . . . . . . 8

2.2.2.5 Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.3 Victim Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Fast Transient Perturbations . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.2 Burst Impulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Electronic Device Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 EMI Influence Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

vi CONTENTS

3 Elements of a Noise Propagation Path at the PCB-Level 15

3.1 Assumptions to Reduction of Complexity . . . . . . . . . . . . . . . . . . . 15

3.1.1 Circuit Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 Multiport Representation . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Passive Component Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 Multiconductor Transmission Lines . . . . . . . . . . . . . . . . . . 19

3.2.2 Transmission Line Discontinuities . . . . . . . . . . . . . . . . . . . 23

3.2.3 Passive Discrete Components . . . . . . . . . . . . . . . . . . . . . 24

3.3 Nonlinear Component Modeling . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.1 Passive Nonlinear Devices . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Active Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4 Analysis of a Complete Signal Propagation Path . . . . . . . . . . . . . . . 28

4 Analysis Techniques of Large Circuits 31

4.1 Basic Circuit Analysis Techniques . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Nodal Admittance Analysis . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2 Connection Matrix Method . . . . . . . . . . . . . . . . . . . . . . 32

4.1.3 Transfer Scattering Matrix Method . . . . . . . . . . . . . . . . . . 36

4.1.4 Multiport Connection Method . . . . . . . . . . . . . . . . . . . . . 41

4.2 Circuit Analysis by Signal Flow Graphs . . . . . . . . . . . . . . . . . . . . 45

4.2.1 Basic Notions on Graphs . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2.2 Signal Flow Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2.3 Transfer Function in Signal Flow Graphs . . . . . . . . . . . . . . . 48

5 Approach to Noise Path Tracing 51

5.1 Shortest Paths Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.1.1 Single Source Shortest Path Algorithms . . . . . . . . . . . . . . . . 52

5.1.2 K-Shortest Simple Paths Algorithms . . . . . . . . . . . . . . . . . 54

5.2 Approach to Dominant Signal Paths Analysis . . . . . . . . . . . . . . . . 62

5.2.1 Illustration of A Dominant Signal Path . . . . . . . . . . . . . . . . 62

5.2.2 Mathematical Background of the Algorithm . . . . . . . . . . . . . 62

5.2.3 Reciprocity of Dominant Signal Paths . . . . . . . . . . . . . . . . . 66

5.2.4 Workflow of the Dominant Path Approach . . . . . . . . . . . . . . 67

5.2.5 Analysis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

CONTENTS vii

6 Time Domain Analysis of a Complete Signal Path 73

6.1 Signal Path with a Linear Termination . . . . . . . . . . . . . . . . . . . . 73

6.1.1 Fourier Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.1.2 Fourier Transformation . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.1.3 Simulation Example . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2 Signal Path with a Nonlinear Termination . . . . . . . . . . . . . . . . . . 78

6.2.1 Conventional Nonlinear Methods . . . . . . . . . . . . . . . . . . . 78

6.2.2 Harmonic Balance Technique . . . . . . . . . . . . . . . . . . . . . 79

6.2.3 Example of a Linear Load . . . . . . . . . . . . . . . . . . . . . . . 83

6.2.4 Example of a Passive Nonlinear Device . . . . . . . . . . . . . . . . 84

6.2.5 Example of an Active Nonlinear Device . . . . . . . . . . . . . . . . 89

6.3 Investigation of Influence Parameters . . . . . . . . . . . . . . . . . . . . . 93

6.3.1 Signal Paths with Interconnects of Arbitrary Geometries . . . . . . 93

6.3.2 Propagation of Noise Impulses from Multiple Sources . . . . . . . . 97

6.3.3 Signal Propagation within Subcircuits . . . . . . . . . . . . . . . . 102

6.3.4 Impact of Linear Interconnect Terminations . . . . . . . . . . . . . 105

6.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.4.1 Efficiency and Convergence Issues . . . . . . . . . . . . . . . . . . . 107

6.4.2 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.4.3 Input and output Parameters . . . . . . . . . . . . . . . . . . . . . 109

7 Conclusion 111

A Complex Fourier Series 113

B Some Fundamental Scattering Matrices 117

References 119

viii CONTENTS

Abbreviations and Symbols

Abbreviations

2D, 2.5D, 3D Two, two and a half, three dimensional

ASCII American Standard Code for Information Interchange

BLT Baum, Liu and Tesche

BTL Bipolar Transistor

CAD Computer-Aided-Design

CDM Charged Device Model

CMOS Complementary Metal Oxyd Semi-conductor

CST Computer Simulation Technologies

CPU Central Processor Unit

DC Direct Current

DFT Discrete Fourier Transform

EFT Electrical Fast Transients

EM Electromagnetic

EMC Electromagnetic Compatibility

EMI Electromagnetic Interference

ESD Electrostatic Discharge

FR4 Flame Retardant type 4

FFT Fast Fourier Transform

GND Ground

HB Harmonic Balance

HBM Human Body Model

HFSS High Frequency Structure Simulation

HSPICE Circuit Simulator of Synopsys

IBIS IO Buffer Information Specification

xAbbreviations and Symbols

IC Integrated Circuit

IDFT Inverse Discrete Fourier Transform

IEEE Institute of Electrical and Electronics Engineers

I/O Input-Output Ports

LU Lower-Upper decomposition of a matrix

LVTTL Low Voltage Transistor Transistor Level

LVCMOS Low Voltage CMOS

MATLAB Matrix Laboratory

MM Machine Model

MNA Modified Nodal Analysis

MoM Method of Moments

MOS Metal Oxyd Semi-conductor

MTL Multiconductor Transmission Lines

NC Not Connect pin

PCB Printed Circuit Board

RFI Radio Frequency Interference

SFG Signal Flow Graph

SI Signal Integrity

SPICE Simulation Program with Integrated Circuit Emphasis

STL Standard Template Library

TEM Transverse Electromagnetic Waves

TSTR Transmission Structure

TTL Transistor Transistor Logic

List of Symbols

0zero matrix

1,1m−nunitary matrices

AnFourier coefficient of a periodic signal

avector of input waves

aiinput wave at port i

BnFourier coefficient of a periodic signal

B(s′, u′) path bundle of branch (s′, u′)

Abbreviations and Symbols xi

branchPath(u′, v′) path in G′representing branch (u′, v′) in Ti

Biblock of vertices with index i

block(u′) = iposition of vertex u′on the shortest path tree X

boutput wave vector

bioutput wave at port i

Cper unit length capacitance matrix

Ccapacitance

C−comp Die capacitance

C−pkg package capacitance

Cj, Cj0depletion capacitance of a diode

CDdiffusion capacitance of a diode

c(e′) cost of edge e′

c(u′, v′) cost of edge (u′, v′)

C(u′) equivalence class associated to the node u′

C(u′, tP) equivalence class associated to the branch (u′, tP)

C(u′, v′) equivalence class associated to the branch (u′, v′)

cvector of independent generators

cisubvector of independent generators for a multiport

Cset of complex numbers

Ccstorage capacitor

CdDC blocking capacitor

Cscharging capacitor

cncomplex Fourier coefficient of a periodic signal

d(u′, v′) distance between the vertices u′and v′

d(v′) distance from a source vertex s′to the vertex v′

dz small section of a line

dω differential frequency

det determinant

detPcofactor of a path P

detSF G determinant of a signal flow graph

E′set of edges in G′

E′

cut edges crossing the cut (Vx,Vy)

E′

iset of edges in E′\e′

xii Abbreviations and Symbols

e′

iedge with index i

Fdiagonal matrix defined from the inverse of the square

root of the normalization impedances

Gper unit length conductance matrix

Gconductance

G′graph

H(v′, u′) transfer function relating the nodes u′and v′

HPndirect path gain associated to the path Pn

Hv′total transfer function at a node v′for multiple sources

HPdirect path gain associated to P

Gdiagonal matrix of the reference impedances

H′, H′

isubgraph of a circuit graph G′

Issaturation current of a diode

Im imaginary part of a complex number

Iecurrent vector of external nodes

Iicurrent vector of internal nodes

Ipcurrent at the port pin a linear network

I′

pcurrent at the port pin a nonlinear network

Ip,q current at the port pin a linear network at the q-th

harmonic of the signal frequency

I′

p,q current at the port pof nonlinear network at the q-th

harmonic of the signal frequency

Ivector of currents

JJacobian matrix

κBoltzmann’s constant

Lper unit length inductance matrix

Linductance

L−pkg package inductance

L(u′, v′) first edge in path (u′, v′)

li,lij length of a line

minblock(v′) smallest index ifor which path(v′, y) traverses Bi

Pconnectivity matrix

Paths′t′all paths connecting s′and t′

Pu′,v′a path relating the nodes u′and v′

Abbreviations and Symbols xiii

Pidominant path of order i

Ptotal power available in a multiport

path(s′, t′) shortest path connecting the vertices s′and t′

Psimple directed Path

P(0) empty set of paths

P(k) set of first kshortest paths

prefixPath(u′) prefix path consisting of all the branches from s′to u′

qeelectronic charge

Rper unit length resistance matrix

Riset of candidate paths connecting s′to t′at iteration i

Re real part of a complex number

Rresistance

R−pkg package resistance

Rdlimiting resistor

Rccharging resistor

Rmimpedance matching resistor

Rsbulk resistance of a diode

Rsh pulse duration shaping resistor

S,Siscattering matrix and submatrix

su′v′(Pn) scattering coefficient associated to the path Pn

su′,v′scattering coefficient of the path or edge (u′, v′)

Ttransfer scattering matrix

Tibranching structure of first ishortest paths

tPleaf node representing the path Pin the branching

structure

TKabsolute temperature

Tij path transmittance for a path (i, j)

Thconstant threshold value

Tperiod of a signal

Vevoltage vector of external nodes

Vivoltage vector of internal nodes

Vcc common-collector voltage

VTthermal voltage

xiv Abbreviations and Symbols

V′set of vertices in G′

Vxset of vertices containing start vertex x

Vyset of vertices containing target vertex y

Vsvoltage source

v(t) time voltage

Vpvoltage at the port pin a linear network

Vp,q voltage at the port pand q-th harmonic of the periodic

signal

Vt′voltage at target load

Vvector of voltages

wik weight of edge (i, k)

Xishortest path tree rooted at xand without edge e′

xisignal variable at node i

Xshortest path tree with root start vertex x

Yadmittance matrix

Yshortest path tree with root target vertex y

YLcharacteristic admittance of a line system

ZN, ZNi reference impedance of a port

Z0characteristic impedance of a line

Zimpedance matrix

ZLload impedance of a line

αattenuation constant

βphase constant

Γwave matrix of a multiconductor transmission lines

Γrreflection coefficient

γpropagation constant

∆Pcofactor of the path P

∆ttime sampling period

∆ determinant of the circuit matrix

εrrelative permittivity constant

Eerror function

ηgrading coefficient of a diode

Φchain matrix of a parallel coupled line system

Abbreviations and Symbols xv

φbuilt-in potential of a diode

τDtransient time of a diode

ωangular frequency

ω0fundamental frequency of a harmonic signal

ω1, ω2, ... fundamental frequencies of a multitone excitation

signal

xvi Abbreviations and Symbols

Chapter 1

Introduction

1.1 Statement of The Problem

The recent trend in the electronic industry towards circuits of higher complexity with

many conductor traces per unit area, faster signal transition rate, operating frequency

and lower power consumption has made the signal integrity analysis (SI) of electronic

systems with focus on these trends a challenging task. Many of these signal integrity

problems derive from electromagnetic phenomena and hence are relate to the electromag-

netic interference (EMI) and the electromagnetic compatibility (EMC). The performance

of electronic systems is mainly affected by the design of the printed circuit board (PCB),

the design of the integrated circuit (IC) and its package, as well as the characteristics of

the signals for which the board is designed [1].

The continuous miniaturization combined with an increased integration density at the

PCB level in today’s PCBs have caused significant amount of crosstalk, reflections, and

internal radiation. These three kinds of signal integrity problems have become critical

issues in the design of modern electronic systems. PCB traces may act as unwanted

emitting and receiving antennas, which cause a strong coupling between neighbouring

structures [2]. In addition to this, technology trends at the chip level towards higher

speed and higher density have pushed the package performance of digital devices to its

limits. The space between integrated circuit pins continues to decrease leading to an

increase of parasitic couplings. The clock rate of present digital systems is approaching

several gigahertz. As the signal rise time decreases, the significant frequency content of

digital signals extends up to some gigahertz. These issues lead to major ringing and

crosstalk. On the other hand modern digital integrated circuits are characterized by low

supply and input voltages and the corresponding noise margin is decreasing. Therefore

the sensitivity of the digital components to EM perturbations increases dramatically.

In addition to the technology aspect, the performance of electronic systems is affected

by the presence of transient impulses [3, 4, 5]. The effects caused by these transients

are superimposed to the high frequency parasitic behaviour of the layout arrangement.

Conducted transients are the typical kind of transients that may affect an electronic

system. The transients’ waveform contains high-frequency components ranging up to

2CHAPTER 1. INTRODUCTION

several gigahertz. This makes their coupling with adjacent signal traces very easy. Since

most digital devices are specified and designed to generate and respond to signals with fast

rise times, comparable to electrostatic discharge (ESD) and electrical fast transients events

(EFT), vulnerability towards these events should be expected. Fast transient impulses

may be devided up into internal and external transient impulses. Internal transients are

generated from the microprocessor, and couple to the rest of the system in question.

External transients are generated from other systems, e.g. multiple PCBs, or may be of

natural sources, e.g. ESD.

External noise impulses can be captured by cables connected to the peripheral equipment

and propagate by conduction, inductive and capacitive coupling and is subject to dis-

tortion mechanisms on the board itself, like reflection. Typically the noise is distributed

within the circuitry by a variety of interconnect paths to finally arrive at the individual

sensitive digital integrated circuit component. The propagation impulses at the integrated

circuit devices are superimposed on the nominal signal at their pins. The level of the in-

curred failure depends on the sensitivity of the integrated circuit devices. The induced

impulses may cause errors in the operation of the IC or the overall system such as program

reset, a logic state change or even data corruption in the memory. Moreover, in many

situations, damage to the device is to be expected.

High frequency parasitics in conjunction with very fast transient signals lead to the per-

turbation or even destruction of sensitive IC. Therefore, an analysis of printed circuit

boards with focus on these transients is required so as to provide sufficient information

on the functionality and the reliability of the circuitry, and thus, to avoid poor printed

circuit board design at early stage of the implementation.

1.2 State of The Art

The SI analysis of printed circuit boards with a focus on the propagation characteristics

of transient interferences, namely conducting type, is required for providing sufficient

information on functionality and reliability of the circuitry. Different protection measures

towards transient impulses, depending on the application [6, 7, 8], are proposed. The

susceptibility analysis of integrated circuits is usually carried out for several types of

transients using numerical and measurement methods [4, 9, 10, 11, 5, 12, 13].

Numerical analysis methods which deal with the propagation of high-frequency transients

within a circuit are based on the combination of the global EM field approach and the

transmission line theory. In literature many numerical methods, or hybrid approaches,

are combined for the simulation of specific problems [14, 15]. The distribution of noise

including possible parasitic couplings can directly be determined by simulating the in-

terconnect structures of the whole system. To achieve efficient computation with less

computer memory storage, the system can be partitioned into subsystems in such a way

that significant electrical interactions occur only through common physical ports [14, 16].

Derived parasitic models of the structures are used within a circuit simulator to perform

a signal integrity analysis.

1.2. STATE OF THE ART 3

Recent investigations in the immunity of electronic systems towards fast conducted tran-

sients were made by using measurement procedures [13, 11, 10]. Tests regarding the effects

of various types of noise impulses on the pins of digital devices are carried out [10]. Many

articles present measurement concepts for the coupling noise impulses at specific IC pins

using standard methods [17]. The impact of noise impulses on the protection elements of

a variety of logic families is also investigated in order to select transient suppression com-

ponents in regard to the optimal operating conditions [18]. Noise generators producing

fast transients are also modeled in several contributions [19, 20, 21].

Typical circuit simulators are based on a nodal analysis. Microwave linear circuits are usu-

ally analyzed in the frequency domain. Transmission structures are modeled by lumped

circuit elements or appropriate admittance matrices. For large circuits the nodal analysis

leads to a very large matrix that renders the analysis process inefficient from the compu-

tation time and memory resources point of view. Alternatively, the multiport connection

method which solves circuits iteratively can be used.

Nonlinear circuits containing IC drivers and receivers are usually analyzed in time domain.

Conventional time domain analyzes are based on numerical integration techniques applied

to the set of difference equations describing the system. Modern approaches, like the

Harmonic Balance (HB) approach, which combines frequency and time domain techniques,

are more efficient. Therefore, the use in analyzing signal integrity of electronic systems

becomes of great interest. In most computer-aided-design (CAD) tools circuit simulators

and EM field solvers are implemented together [22, 23]. This allows for the results of field

solvers to be linked to circuit solvers in order to perform a complete analysis of the circuit

considering the parasitic behaviour of the interconnect structures.

The common property of most existing computer-aided-design tools for electronic circuit

analysis is to determine the physical quantities at the device pins. In literature, the prop-

agation of noise power between two specified components is always determined within a

simple interconnect structure by computing the parasitic elements or the transmission co-

efficient relating the corresponding ports [24]. Critical structures and single transmission

lines are mainly defined by their dimensions, especially the length.

The aim of this thesis is to develop a signal tracing algorithm for the identification and

characterization of the critical interconnect paths with respect to conducted transient im-

pulses considering the global system of interconnects on a PCB. The critical or dominant

propagation paths cause significant transfer of noise power from a noise source to a spe-

cific IC I/O pin. Because the PCB design becomes an interesting impact factor for the

immunity of IC, the identification of the whole propagation path at PCB-level is of more

importance. This methodology allows the extraction of the critical propagation paths by

taking into account all coupling mechanisms which relate a given noise source to a target

IC pin. Such functionality is not yet implemented in any circuit simulator. Moreover,

there is no scientific literature at all published which addresses the determination of the

whole signal propagation paths. The knowledge of these paths and their associated cou-

pling noise can be used to optimize the layout’s electrical and physical characteristics in

order to keep the coupling noise at an acceptable level and thus meeting the requested

specifications of the circuitry.

4CHAPTER 1. INTRODUCTION

Chapter 2

Susceptibility and Immunity of

Electronic Devices

This chapter presents the elements required for the description and analysis of an elec-

tromagnetic interference problem on printed circuit boards. Propagation, or coupling

mechanisms for conducted fast transient interferences are described. Some examples of

such transients are provided. The susceptibility of digital devices against electrostatic

discharges is discussed.

2.1 EM Disturbances

Electromagnetic Interference is defined as the influence of unwanted signals on electronic

devices and systems, making the operation of the device difficult or impossible. The noise

signal may come from other electrical circuits or from a portion of the circuit itself. The

electromagnetic energy is transmitted from one electronic device to another via radia-

tion paths, conducting paths, or a combination of both. A system that does not become

affected by its environment is said to be EM-compatible. The Electromagnetic Compat-

ibility is defined as the capability of electrical and electronic systems, equipment, and

devices to operate in their intended electromagnetic environment within a defined margin

of safety, and at design levels or performance, without suffering or causing unacceptable

degradation or interrupts as a result of electromagnetic interference. The immunity of an

electronic system or device is its ability to function satisfactorily in its environment while

maintaining a predefined performance level [25].

As high technology advances, so do the problems from electromagnetic interferences. EMI

issues are increasingly problematic when designing systems. Systems are not performing

to specifications to overcome all EMI problems, but satisfy certain conditions to avoid

some particular EMI problems.

6CHAPTER 2. SUSCEPTIBILITY AND IMMUNITY OF ELECTRONIC DEVICES

2.2 Electromagnetic Interference Model

A simple model to describe an interference problem consists of a noise source, a victim

circuit, and a coupling path. The source of electromagnetic energy needs a coupling path

to facilitate the transmission of the disturbance signal to the victim circuit. If one of

these three elements is removed from the system, the disturbance problem is solved. The

coupling path between source and victim does not have to be a conducting medium such

as an electric conductor, but can also be a free space or any other material as well. In

general the coupling path is a combination of conduction and radiation. A useful technique

that can be used to minimize EMI-problems is to keep the disturbance signals from the

source and across the coupling path below a certain level. Figure 2.2.1 illustrates the

relationship between these three elements.

Noise Source Victim Equipment

Coupling Path

Figure 2.2.1: Elements of an electromagnetic interference model

2.2.1 Electromagnetic Interference Sources

The source of interference is the active element producing the original waveform of the

disturbance. There exist two types of EMI sources depending on their creation. Ar-

tificial sources of EMI include microprocessors, microcontrollers, transmitters, transient

power components, such as electromechanical relays, and switching power supplies. For

instance within a microcontroller system, the digital clock circuitry represents a generator

of wideband noise. Natural sources on the other hand include electrostatic discharges and

lightning.

EMI sources can be also grouped into internal and external sources. Internal EMI sources

are the result of signal degradation along a transmission path, including parasitic cou-

pling between subcircuit elements, or devices, of the same system. More specifically, the

problems are signal losses and reflections along the path, and crosstalk between adja-

cent signal traces. An example of such sources of disturbances are the noise impulses

generated from a microprocessor and which may disturb other devices within the same

equipment [26, 27, 28].

External sources are applied to the system from the outside. Examples of such external

influences are electrostatic discharge and radio frequency interference (RFI). These can

directly be coupled to the circuit components or indirectly via an interface to the outside

of the circuit like I/O lines. The coupling waves are then transferred into the inside of

the system.

2.2. ELECTROMAGNETIC INTERFERENCE MODEL 7

2.2.2 Coupling Mechanisms

The EMI propagation path is the medium that carries the electromagnetic interference

energy from the interference source to the victim circuit. The EM energy is propagating by

conduction, radiation, or a combination of both. An obvious way noise can be conducted

into a system is through interconnects. An example of this type of coupling is found when

the noise enters a system through the power supply leads. The EM radiation does not

however need a conducting medium. The radiated fields propagate in a free space and

cause EM interaction with the system components.

There are four coupling paths for transmitting electromagnetic disturbances from an inter-

ference source to a victim circuit. The first belong to the radiated type, such as capacitive,

inductive, and field coupling, and the last is of conductive nature like galvanic coupling.

2.2.2.1 Capacitive Coupling Paths

Capacitive coupling is caused by an electrical field. Two or more electronic circuits or

subcircuits are coupled through their radiated electrical fields. The signal in the victim

circuit is influenced by fast voltage transition of the interference signal by way of an

interfering coupling parasitic capacitance. The influenced current can be modeled as a

current source in the victim circuit according to

I=CdV

dt ,

where Cis the parasitic capacitance relating both circuits.

For two signal traces with different electrical potential the value of the parasitic capac-

itance is depending on the ratio of their lengths and the distance between them. The

coupling or parasitic capacitance leads not only to delay, but also causes potential logic

malfunctions. This is a problem for designs with high clock frequencies, low supply volt-

ages, and usage of dynamic logic with low noise margin.

2.2.2.2 Inductive Coupling Paths

Inductive coupling refers to the influence of a magnetic alternating field generated by the

interference current on the victim circuit signal. By changing the flux an interference

voltage, due to fast current transients, is inducted in the victim circuit. The inducted

parasitic voltage is modeled as a voltage source in the victim circuit. For simple case where

two conductors are inductively coupled the inducted voltage from the active conductor

on the passive one is defined as

V=LdI

dt ,

where, Lis the mutual inductance between the two conductors.

Inductive coupling can be reduced by increasing the space between the conductors, de-

creasing the length of parallel conductors, and using orthogonal arrangement during the

placement.

8CHAPTER 2. SUSCEPTIBILITY AND IMMUNITY OF ELECTRONIC DEVICES

2.2.2.3 Crosstalk

The combination of capacitive and inductive couplings simultaneously is named Crosstalk.

Crosstalk occurs if the coupling path between parallel traces is very small. Consequently,

the traces are coupled through the electric and the magnetic fields. The close coupling at

the line start is called near-end crosstalk and the remote coupling at the line end is called

far-end crosstalk. In general crosstalk noise modeling consists of determining of near- and

far-end voltages, or currents at interconnect extremities.

The interconnect factors influencing crosstalk effect are those influencing capacitive and

inductive paths, i.e. dimensions of the wires and distances separating them [29, 30, 14]. A

crosstalk pulse generated on a victim line is depending also on the frequency of the signal

and the nature of its transitions at the aggressor line. The slew rate of the transition

signal depends on the frequency of signal. The current flow between two coupling wires

increases as this slew rate increases. This causes the charge increase or decrease at the

victim line.

Another effect which is usually implicitly analyzed when studying crosstalk are the reflec-

tions. Reflections, related to line terminations, result from impedance branches, which

are caused by mismatching [31, 14]. On a printed circuit board, if a line is not matched,

reflections occur and couple to the information signal on other signal lines. Thus, leading

to undesirable effects that influence the nominal signals. Terminations of signal lines help

to reduce these undesirable effects. A termination not only reduces signal reflection by

matching the impedance of the coupling path, but can also slow down the fast rising and

falling edge of the signals.

2.2.2.4 Galvanic Coupling Paths

A further coupling mechanism is the impedance coupling or galvanic coupling. It is the

dominating coupling mechanism for low frequencies and occurs if common impedances

are shared from two or more electronic circuits. In this case, a current of the interfering

circuit flows through an impedance belonging to the agressor and the victim circuit.

For instance, two circuits are sharing the conductor carrying the supply voltage and the

conductor carrying the return path to ground. If one circuit creates a sudden demand in

current, the other circuit’s voltage supply will drop due to the common impedance both

circuits share between the supply lines and the source impedance. This coupling effect

can be reduced by decreasing the common impedance.

2.2.2.5 Radiation

Radiation or electromagnetic wave coupling is produced by the antenna effect of spa-

tially extended circuits. The causes of this kind of interference are any sources which

emit electromagnetic waves. These include all kinds of transmission systems, as well as

lightning, etc.

Coupling can occur with radiated electric and magnetic fields which are common to all

electrical circuits. Whenever current changes, electromagnetic waves are generated. These

2.3. FAST TRANSIENT PERTURBATIONS 9

waves can couple into the interface cables which provide a conductive path into the cir-

cuitry or they may be directly coupled onto the printed circuit wiring when the assembly

is not shielded. When the amplitude of the radiated fields is sufficient, induced voltages

and demodulated carriers can affect the operation of a device. The coupling noise is

depending on the dimensions of the trace and the frequency of the applied signal [32, 33].

2.2.3 Victim Devices

All electronic circuits and devices are receptive to EMI transmissions. The coupling into

a circuit can be done through connected cables or radiation. For a PCB with dimen-

sions smaller than the interference wavelength, the interference collected by direct radio

transmission is negligible compared with that transmitted by conduction [34]. The noise

energy is transferred to devices susceptible to disruption. Due to their lower operating

levels of voltages modern digital circuits are more sensitive to transient interferences [6].

2.3 Fast Transient Perturbations

Examples of EMI sources are fast transient noise impulses. These can be divided into

single and repetitive impulses. Such kind of sources causes electrical overstress and leads

to integrated circuit failures. The result of an electrical overstress event can range from no

damage or degradation of the IC up to catastrophic damage where the IC is permanently

non-functional. Electrical overstress covers a broad spectrum of events, including elec-

trostatic discharge, power-up/power-down transients, and excessive DC current/voltage

levels. ESD and burst are typically the most common form of electrical overstress, and

consequently they are the focus of this subsection [20].

2.3.1 Electrostatic Discharge

The problem of static electricity accumulation and subsequent discharges becomes more

relevant for uncontrolled environments and the widespread application of equipment and

systems in a wide range of industrial plants. For instance ESD may affect many compo-

nents such as diodes, transistors, integrated circuit devices, metal-oxide-semiconductors

(MOS), and film passive components, etc. Device failures do not always occur immedi-

ately, often, the component is only slightly weakened or its parametric properties altered,

and therefore is less able to withstand subsequent ESD exposure and may constitute a

reliability problem [20, 21].

In particular, there are three general types of ESD events: the human body model (HBM),

the machine model (MM) and the charged device model (CDM). The HBM and MM

correspond to discharge current between any two pins on an IC as a result of a human

body discharging through a chip, and a metal discharging through a chip respectively. In

the CDM, the ESD event does not originate from outside the IC device itself, but instead

represents the discharge of an IC device to ground. The IC device is charged for example

10CHAPTER 2. SUSCEPTIBILITY AND IMMUNITY OF ELECTRONIC DEVICES

by an external field. The discharge leads to a high voltage pulse that may affect the

susceptible devices. The effects of the operator discharge may be a simple malfunction

of the equipment or damage of the electronic components. The dominant effects can be

attributed to the parameters of the discharge current (rise time, duration, etc.). The

general equivalent electrical model of an ESD simulator is depicted in Figure 2.3.1(a).

VCs

RcRd

(a)

100%

90%

10%

30ns

50ns

I at 30ns

I at 50ns

tr=0.7 to 1ns

(b)

Figure 2.3.1: ESD discharge circuit: (a) electrical model, (b) typical waveform

First a source capacitor Csis charged to a DC high voltage, then the high voltage power

supply Vis disconnected from the capacitor, and the capacitor is connected to the device

under test through a limiting resistor Rd. The value of the test capacitor and the limiting

resistor differ among the various test standards. The voltage source Vdefines the severity

level of the test impulses.

The HBM uses a source capacitor of 100 pF and a discharge resistor of 1.5 kΩ. The MM

uses a source capacitor of 200 nF, but no discharge resistor. This causes the device under

test to be subject to more voltage than the HBM testing. ESD test requirements are

specified in the standard IEC61000-4-2. Typical values of the charging resistance Rc

varies between 50 MΩ and 100 MΩ. The discharge resistance has a value of 330 Ω and the

capacitance Cshas a value of 150 pF.

The form of an ESD impulse is represented in the right side of Figure 2.3.1(b). The

waveform of the discharge current is characterized with an extremely short rise time of

0.7 to 1.0 ns and amplitudes of up to 45 A. Secondary effects caused by this edge steepness

are high electrical and magnetic fields strengths.

The problem of protecting CMOS chips against ESD events has gained considerable im-

portance for manufacturers and users. Protection circuits include ESD clamps configured

to maintain the voltage at a power line to a value that is safe for the operating cir-

cuits, and that will also not interfere with the operating circuits under normal operating

conditions [18].

2.4. ELECTRONIC DEVICE SENSITIVITY 11

2.3.2 Burst Impulses

Electrical fast transient noise impulses (EFT) are low-power high-voltage signals which

occur as a result of bouncing contacts in switches and relays. The pulsed voltage arises

several times and impulse packages, named Burst, are generated. These currents can

couple and propagate over power and data lines and consequently lead to a disturbance

or even destruction of attached devices or elements. IEC 61000-4-4 specifies the burst

threat in both power and data lines [24].

The simplified circuit diagram of the burst generator is given in Figure 2.3.2. In this

figure Rcis a charging resistor, Csis an energy storage capacitor, Rsis a pulse duration

shaping resistor, Rmis an impedance matching resistor, and Cdis a DC blocking capac-

itor. The values of the circuit elements Cs, Rs, Rm, and Cddiffer among the various test

standards. These are selected so that the generator delivers a fast transient under open

circuit conditions and with a 50 Ω resistive load.

RcRmCd

Figure 2.3.2: Circuit diagram of a burst generator according to IEC 61000-4-4

EFT impulses are described in terms of voltage across a 50 Ω load from a generator

having a nominal dynamic source impedance of 50 Ω. The output occurs as a burst of

high voltage spikes at repetition rates ranging from 2 kHz to 5 kHz. The burst duration

is defined as 15 ms with bursts repeated every 300 ms. Each individual burst pulse is a

double exponential waveform with a rise time of 5 ns and a total duration of 50 ns. EFT

impulses are characterized by voltage amplitudes up to 5 kV and current amplitudes up

to 30 A. The impulse waveform, the burst repetition rate, and a burst packet according

to IEC 61000-4-4 are shown in Figure 2.3.3.

2.4 Electronic Device Sensitivity

The sensitivity of integrated circuits is defined by the noise margin, which represents the

maximum value of noise that can be added to the input signal without affecting the signal

state at the IC pin. In other words, that is, the difference between what the driver IC

outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic

voltage. Any voltage that exceeds this noise margin causes a wrong output state.

12CHAPTER 2. SUSCEPTIBILITY AND IMMUNITY OF ELECTRONIC DEVICES

V(kV)

t(ns)

90%

50%

10%

rise time

impulse

duration

(a)

V(kV)

t(ns)

spike frequency

burst period

burst

duration

(b)

Figure 2.3.3: EFT impulse according to IEC 61000-4-4: (a) single impulse, (b) burst packet

There are two different types of noise margins, one for a logic high value and one for a

logic low value. These are defined by

Vh=VOH [driving device] −VIH [receiving device]

Vl=VIL [receiving device] −VOL [driving device] ,(2.4.1)

where Vhis the noise level immunity for the logic chip when the logic state is high, Vlis

the noise level immunity for the logic chip when the logic state is low, VOH is the minimum

high output generated by the driving gate, VIH is the minimum high input allowable for

the driven gate, VOL is the maximum low output generated by the driving gate, and VIL

is the maximum low input allowable for the driven gate.

In digital circuits, the most critical pins are that receiving significant EMI energy. These

include reset, interrupt, and control line signals. The coupling energy to a victim digital

device depends on the operating frequency of the circuit, the edge rate transition of digital

components switching logic states, and transfer mechanisms. Table 2.4.1 shows typical

noise margins for various logic families [35].

Logic VOH VIH Noise VIL VOL Noise

(V) (V) Margin

(mV)

(V) (V) Margin

(mV)

TTL [5volt] 2.4 2.0 400 0.8 0.5 300

BTL [5 volt] 2.1 1.62 480 1.47 1.1 370

CMOS [5 volt] 4.9 3.85 1050 1.35 0.1 1340

LVTTL [3volt] 2.4 2.0 400 0.8 0.4 400

LVCMOS [3 volt] 2.8 2.0 800 0.8 0.2 600

CMOS [2.5v] 2.0 1.7 300 0.7 0.4 300

CMOS [1.8v] 1.35 1.1 250 0.66 0.45 210

Table 2.4.1: Typical noise margins for various logic families

2.5. EMI INFLUENCE PARAMETERS 13

2.5 EMI Influence Parameters

The parameters influencing the EMI analysis of a problem are divided into two categories.

The first category adresses the interference signal and the second one describes the tech-

nology of the printed circuit board and its devices. Interference signal parameters include

frequency, amplitude, rise, and fall times. A noise source signal having a high voltage

amplitude and small rise time contains high frequencies in its spectrum and thus can

easily disturb the operation of a sensitive device.

Technology aspects on the other hand include the materials and the dimensions of the

interconnect traces on the PCB as well as on the chip level. Small dimensions of signal

traces on the PCB level lead to high crosstalk between them. On the chip level the

technology aspect is associated with low noise margins and therefore high sensitivity.

The parameters influencing the susceptibility of PCBs against parasitic interferences, at

each stage of the EMI model, are given in Table 2.5.1.

Noise Source PCB Interconnects Digital IC Pin

Noise waveform Technology issues Technology issues

Fast rise and fall times Complex structures Sensitive digital devices

High amplitudes Small dimensions

High-density

High frequency Conduction Small noise margins

components Reflections

Emission

Crosstalk

Table 2.5.1: The parameters influencing EMI models at PCB

Crosstalk on printed circuit boards in conjunction with fast transient signals represent

the most signal integrity problems in modern systems. Fast transient impulses are mainly

induced into a PCB by conduction through a single or multiple traces which distribute

the high frequency noise energy into the entire system, and thus affecting the sensitive

digital devices. Within this thesis a methodology for identifying and analyzing of coupling

signal paths considering the whole system of interconnects in a PCB is developed. The

coupling paths may include conductive, crosstalk and reflections paths.

14CHAPTER 2. SUSCEPTIBILITY AND IMMUNITY OF ELECTRONIC DEVICES

Chapter 3

Elements of a Noise Propagation

Path at the PCB-Level

This chapter presents the physical elements belonging to a noise propagation path at the

PCB-level. Some assumptions regarding the layout are made to reduce the complexity

of the analysis of the signal paths. A brief description of the modeling methodologies of

both linear and nonlinear components of the signal paths is presented.

3.1 Assumptions to Reduction of Complexity

This section presents the partitioning scheme of complex PCB structures usually used

for efficient numerical field simulation purposes. The multiport representation of the

transmission structures, which is useful for circuit analysis techniques, is described.

3.1.1 Circuit Partitioning

A traditional approach for the analysis of the high frequency parasitic behaviour of printed

circuit boards is based on the simulation of the electronic devices and the connecting

signal traces it consists of. The parasitic behaviour is obtained by combining the circuit

simulation and the electromagnetic field simulation. Thus, the parasitic effects between

signal traces, including crosstalk and reflections, can be incorporated into the overall

simulation of the system.

The entire PCB consisting of complex microstrip structures is usually characterized using

a partitioning procedure under the assumption that the modes propagating along the

coupled microstrip lines are assumed to be quasi-TEM. The resulting substructures can

be analyzed separately and their models can be easily added to a CAD system. This

procedure is hierarchical since the models for elementary blocks can be used to generate

circuit models of other structures created by a combination of those elementary blocks.

These blocks are consisting of coupled parallel transmission lines which are generally

accompanied by discontinuities of different types. The parasitic behaviour is modeled

16CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

using the transmission line theory and the electromagnetic field theory. Transmission

structures interconnecting circuit devices may be modeled as piecewise interconnected

conductors characterized by the per unit length matrices R,L,G, and C, or directly

by their frequency domain parameters. At high frequencies the discontinuities are better

parameterized using numerical full wave field solvers, which cover all electromagnetic

phenomena encountered in modern PCBs, e.g. transmission line effects, reflections, skin

effects, proximity effects, and couplings. The behaviour of the entire system is obtained

by the combination of all models of the structures that build it [36, 14, 16]. Figure 3.1.1

shows an example of an interconnect structure and its partitioning.

Figure 3.1.1: Principle of the decomposition of complex structures

The substructures are generated on the basis of their geometry. The structure in Fig-

ure 3.1.1 is divided into parallel lines and double bends discontinuities. This model shows

that only the coupling between adjacent traces is considered. A circuit should be devided

in places where coupling mechanism is at a minimum. Additional considerations such as

the symmetry of interconnect structures and the wavelength need to be addressed. Using

the adjacency aspect, only the coupling between neighboring traces is to be considered.

This assumption may give a better approximation if the space between the transmis-

sion lines is constant. The symmetry may be used to decouple any structures that have

some geometrical shape. This assumption may be a good approximation if the space

between both partitions is many times bigger than the space between the transmission

lines within a specified partition. Another assumption leads in neglecting the coupling

between a signal trace and any other transmission line of small length.

Modeling a PCB as an assembly of predefined substructure elements which are connected

to each others leads to efficient analysis. The number of these substructures is small and

their characterization requires less computer resources rather than the original structures.

3.1.2 Multiport Representation

Circuit analysis techniques provide solution to the circuit equations in the frequency and

time domains. The response of the circuit is computed in terms of the device parameters.

At high frequencies electrical networks consist of lumped elements and distributed ele-

ments. Distributed elements model the transmission lines and high frequency structures

present in the circuits. These are represented by multiports, characterized by some kind of

3.1. ASSUMPTIONS TO REDUCTION OF COMPLEXITY 17

matrices. Multiports can be characterized in terms of its terminal currents and voltages.

The impedance Zand the admittance Yof a multiport are defined by the equations

V=Z I (3.1.1)

I=Y V ,(3.1.2)

where Iand Vare the vectors of terminal currents and voltages of the multiport respec-

tively. For a multiport component with Nports the impedance and admittance matrices

have the size N×N. For reciprocal networks these matrices are symmetric. In addition,

if the network is lossless, then the elements of Zand Yare pure imaginary.

A much more convenient form for the description of microwave circuits uses normalized

wave variables and scattering matrix. It is the preferred description of microwave n-

ports which uses the transfer of the power between the ports of a microwave structure

by measuring of the incident and reflected waves aiand bi. The reason is that for some

structures the voltage and current may not be well defined, or even defined at all. The

specification of voltage and current in a distributed circuit requires a specification of the

exact location, and these quantities vary with location in the circuit. The determination

of the individual parameters of voltage and current equation sets requires short or open

circuit loads, which are sensitive to the precise location [37, 31].

The scattering parameters relate the power variables aiand biat the ports of a microwave

multiport. The incident and reflected power waves at the i-th port of the network are

defined in terms of the terminal voltage Vi, the terminal current Ii, and the reference

impedance ZNi, as follows:











ai=1

2pRe(ZNi)(Vi+ZNiIi)

bi=1

2pRe(ZNi)(Vi−Z∗

NiIi)

,(3.1.3)

where the superscript (∗) denotes the complex conjugate.

The scattering matrix for a multiport network with n-ports is defined by the equation

b=S a,(3.1.4)

where Sis a square matrix of the order n×nand aand bare vectors, respectively, of

the input and output power wave variables at the ports of the multiport.

The diagonal elements sii of the matrix Sare the power wave reflection coefficients at

the port i, and the off-diagonal elements sik, for i6=k, are the power wave transmission

coefficients between ports iand k.

The scattering parameters are physically interpreted by the power transfer between the

ports of a multiport. The total power P delivered to all nports of the circuit is the sum

of the corresponding powers delivered to the individual ports. It is given by the relation

i=1 |ai|2−

i=1 |bi|2=a+(1−S+S)a,(3.1.5)

18CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

where 1is a unit matrix of order n, and the superscript (+) indicates the complex conju-

gate transposed matrix or vector.

In a passive multiport, for which P≥0, the scattering matrix Ssatisfies the condition

1−S+S≥0,(3.1.6)

for all frequencies. Moreover, if the multiport is lossless, i.e. P= 0, (3.1.6) becomes

1−S+S= 0.(3.1.7)

Therefore, the scattering matrix of a passive lossless network is a unitary matrix. An

important property of the Smatrix for a reciprocal network is the symmetry, that is,

S=ST,(3.1.8)

where STis the transpose of the matrix S.

The scattering matrix of a multiport can be determined from the impedance and admit-

tance matrices. It is computed from the impedance matrix as

S=F(Z−G∗) (Z+G)−1F−1,(3.1.9)

where Fis a diagonal matrix defined in terms of the square root of the normalization

impedance by







2√Re(ZN1)0... 0

2√Re(ZN2)... .

.... ...0

0... 01

2√Re(ZNn)







,(3.1.10)

and Gis the diagonal matrix of the reference impedances ZNi

G=





ZN10... 0

0ZN2... .

.... ...0

0... 0ZNn







.(3.1.11)

The inverse transformations of (3.1.3) give the voltage and currents in terms of power

waves. Assuming the reference impedances of all the ports of a multiport are identical,

the impedance matrix can be computed from the scattering matrix by

Z=F−1(1−S)−1(SG+G∗)F.(3.1.12)

The admittance matrix can also be derived from the scattering matrix Sas

Y=F(1−S) (SG+G∗)−1F−1.(3.1.13)

3.2. PASSIVE COMPONENT MODELING 19

3.2 Passive Component Modeling

Passive interconnected structures and terminating loads constitute the physical signal

propagation paths in a PCB. High frequency parasitics of the transmission structures are

described by both the transmission line theory [38, 31], and the field theory [31]. The

topology in which the physical paths are connected is an important parameter for the

prediction of the signal propagation between two specified devices.

3.2.1 Multiconductor Transmission Lines

At high frequencies a short section of length dz of a transmission line can be modeled as

a lumped-element circuit. The electrical equivalent circuit representing this section of the

line is depicted in Figure 3.2.1. The parameters R, L, G, and Cmodeling the line section

are called the per unit length parameters.

i(z, t)i(z+dz, t)

v(z, t)v(z+dz, t)

Rdz Ldz

Gdz Cdz

Figure 3.2.1: Lumped-element equivalent circuit of a transmission line section

In Figure 3.2.1 a small section, dz element, of a transmission line is represented. It consists

of a series resistance Rdz, a series inductance Ldz, a shunt conductance Gdz, and a shunt

capacitance Cdz. The parameters R, L, G, and Cthat are distributed along the entire

line model the parasitic behaviour of the line at high frequencies. The series resistance R

is due to the finite conductivity of the conductor, i.e. ohmic losses and skin effect. The

series inductance Lrepresents the total self inductance of the conductors, and the shunt

capacitance Cis due to the close proximity of the conductors. The shunt conductance Gis

due to the dielectric loss in the material between the conductors. The line is homogeneous

if the per unit length parameters are constant along its expansions.

The two equations in the frequency domain describing the wave propagation for the

voltages Vand currents Ion the line are given by











−∂V

∂z =R I +L∂I

∂t

−∂I

∂z =G V +C∂V

∂t

.(3.2.1)

20CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

Under the steady state condition the equations in (3.2.1) can be transformed into differ-

ential equations, called also Telegrapher’s equations, in the frequency domain. These are

given by











∂2V

∂z2−γ2V= 0

∂2I

∂z2−γ2I= 0

,(3.2.2)

where γis the complex propagation constant of the waves, and is defined as

γ=α+jβ =p(R+jωL)(G+jωC).(3.2.3)

The propagation constant depends on the frequency and the length of the line. Its real

part αis the attenuation constant, and its imaginary part βis the phase constant. The

characteristic impedance Z0of the line is defined as

Z0=sR+jωL

G+jωC .(3.2.4)

The solution of equations (3.2.2) gives the wave equations for the voltages and currents

at any locations of the transmission line. This solution is given by







V(z) = V+

0exp(−γz) + V−

0exp(γz)

I(z) = I+

0exp(−γz) + I−

0exp(γz)

.(3.2.5)

The terms exp(−γz) and exp(γz) in (3.2.5) represent the wave propagation in the +zand

−zdirections respectively, and V+

0, V −

0, I+

0, and I−

0are constants which can be calculated

from the voltage and current at the position z= 0.

In general the propagation constant and the characteristic impedance are complex. In the

case where the line is losless, i.e. R=G= 0, the general expressions of the attenuation

constant and the characteristic impedance can be simplified to give

γ=jβ =jω√LC ,(3.2.6)

and

Z0=rL

C.(3.2.7)

The frequency domain voltages and currents become







V(z) = V+exp(−jβz) + V−exp(jβz)

I(z) = I+exp(−jβz) + I−exp(jβz)

.(3.2.8)

Due to the finite conductivity a transmission line has losses, which can be neglected in

many practical cases. In high frequencies the losses can however depend on the frequency.

3.2. PASSIVE COMPONENT MODELING 21

As an example, the per unit length resistance depends on the frequency according to the

relation

R(ω) = k1pk2ω,

where k1and k2are constants.

At high frequencies a transmission line can be represented by its scattering parameters.

The voltage and current and the associated incident and reflected waves in a transmission

line terminated with a load ZLare defined as shown in Figure 3.2.2.

b1a2

Figure 3.2.2: Two-port representation of a transmission line

If the characteristic impedance Z0of the line equals the load impedance ZL, then no

reflection of the power is produced and the line is said to be matched. If the characteristic

impedance is different from the load impedance a portion of the incident power is reflected

to the line. The reflection coefficient Γris defined by

Γr=ZL−Z0

ZL+Z0

Reflections may also be produced at the generator side, if the generator presents mis-

matched impedance to the line. Consequently multiple reflections may occur at both ends

of the line. Voltage and currents on the line consist of a superposition of the incident and

reflected waves. The normalized wave phasors can be expressed as a function of voltage

and current given by (3.2.5). A two-port network describing a single line represented by

its scattering matrix Sis shown in Figure 3.2.2.

If the single line is assumed to be lossless and has a characteristic impedance Z0and a

length l, then its scattering matrix is given by

S=



0 exp(−jβl)

exp(−jβl) 0 

.

The Telegrapher’s equations for a multiconductor transmission line system in the time

domain are given by











−∂v(z, t)

∂z =Ri(z, t) + L∂i(z, t)

∂t

−∂i(z, t)

∂z =Gv(z, t) + C∂v(z, t)

∂t

,(3.2.9)

22CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

where R,L,G, and Care the matrices per unit length, v, and iare vectors of voltages and

currents on the conductors. The diagonal elements of the matrices represent the coupling

of the lines to the reference conductor, the other elements represent the coupling of the

conductors with each other. These matrices are of order n×n, where nis the number

of the coupled conductors. Land Care the inductance and capacitance matrices whose

elements represent self and mutual parameters per unit length of the lines. In general

Land Cdo not change heavily like R.Gincreases proportionally with the frequency

because of the dielectric losses.

Again, and assuming the steady state analysis, (3.2.9) can be written as











∂V(z, ω)

∂z + (R(ω) + jωL(ω))I(z, ω) = 0

∂I(z, ω)

∂z + (G(ω) + jωC(ω))V(z, ω) = 0

.(3.2.10)

Introducing the impedance and admittance matrices defined by







Z(jω) = R(ω) + jω L(ω)

Y(jω) = G(ω) + jω C(ω)

the equations (3.2.10) become











∂2V(z, ω)

∂z2−Z(jω)Y(jω)V(z, ω) = 0

∂2I(z, ω)

∂z2−Y(jω)Z(jω)I(z, ω) = 0

.(3.2.11)

Similarly to the propagation constant γof a single line, the complex wave matrix Γcan

be defined for a multiconductor system as

Γ(jω) = pZ(jω)Y(jω).

The solution to voltage waves in (3.2.11) can be expressed in terms of the wave matrix Γ

V(z, ω) = V+exp(−Γ(jω)z) + V−exp(Γ(jω)z),(3.2.12)

where V+and V−are constant coefficients defining the conditions at the position z= 0 on

the lines. The current waves can be obtained by substituting the voltage solution (3.2.12)

in (3.2.10), and solving the resulting equation. The characteristic admittance matrix YL

of the transmission line system is defined by

YL(jω) = Z(jω)−1pZ(jω)Y(jω).

The voltages and currents at any location zof a multiconductor transmission line are

related by the chain, or transfer matrix Φ. It is a n×nmatrix that can be partitioned

into four submatrices Φ11,Φ12,Φ21, and Φ22, such that

3.2. PASSIVE COMPONENT MODELING 23





V(z, ω)

I(z, ω)

=



Φ11(z, ω)Φ12(z, ω)

Φ21(z, ω)Φ22(z, ω)





V(0, ω)

I(0, ω)

,(3.2.13)

where the submatrices are defined by

Φ11(z, ω) = 1

2(expΓ(jω)z+ exp−Γ(jω)z)

Φ12(z, ω) = −1

2(expΓ(jω)z+ exp−Γ(jω)z)Y−1

L(jω)

Φ21(z, ω) = −1

2(expΓ(jω)z+ exp−Γ(jω)z)

Φ22(z, ω) = 1

2(expΓ(jω)z+ exp−Γ(jω)z)Y−1

L(jω)

(3.2.14)

The impedance matrix Zcan be computed from the chain matrix as

Z=

−Φ11 Φ−1

21 −Φ−1

−Φ−1

21 −Φ−1

21 Φ22 

.(3.2.15)

The chain matrix Φof a system of transmission lines can be determined from the per unit

length parameters. The corresponding impedance matrix can be calculated from (3.2.15).

Using (3.1.9) the scattering matrix relating the line ends can be computed.

3.2.2 Transmission Line Discontinuities

Discontinuities are present on PCBs due to layout necessities. These cause disturbances

in the electric and magnetic fields which produce signal integrity effects like reflections

and radiation. At the discontinuity regions many high order modes in addition to the

propagating ones are produced. The accurate characterization of the EM behaviour of

complex discontinuities occurring along printed circuit board signal paths represents one

of the most important issues in the signal integrity analysis.

In a lumped equivalent circuit, disturbances in electric and magnetic fields are represented

as an equivalent capacitance and an equivalent inductance respectively. Lumped element

equivalent circuits of different types of discontinuities are provided in literature [37, 39,

40]. Many modeling techniques of complex discontinuities are based on the extraction of

passive lumped equivalent circuits from numerical field solutions and measurement data

[41, 42, 43]. For discontinuities with shorter longitudinal dimension one can model with

shunt or series reactance, whereas for large longitudinal dimensions one can model by a

T or Π network. The extraction of the R,L,G, and Cmatrices of single and coupled

transmission lines is carried out using 2D field solvers. For complex discontinuities 3D

field solvers are needed to get accurate simulation.

Full wave numerical analysis, that allows to account for the non-TEM propagation mode

occurring in proximity of a discontinuity, appears as the only reliable way of model-

ing accurately the electromagnetic behaviour of discontinuities. There are many field

24CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

solver tools for analyzing interconnect structures. All these are based on the solution

of Maxwell’s equations in one form or another. The main differences between the tools

are the equations solved, the numerical technique as well as the discretization procedure

used. For instance, the frequency domain scattering parameters of a discontinuity struc-

ture can be obtained by the finite element software tool HFSS of Agilent [44], or by the

finite integration technique tool Microwave Studio of CST [23]. These methods are very

flexible in modeling complex geometries and suitable to account for the dispersive nature

of the dielectric substrate. If necessary, the second tool provides the ability to synthesize

an equivalent electrical model of the discontinuity from the simulation data.

3.2.3 Passive Discrete Components

Discrete passive components, R,L, and C, are two port devices that often appear in

microwave networks as termination loads, or between the connection of many multi-

port elements. Like the transmission structures, these can also be represented by their

impedance, admittance, or scattering matrices. Since microwave networks are better

analyzed by means of the scattering parameters, it is also important to use this repre-

sentation for discrete passive components [45]. The scattering matrices of a termination

load, a series impedance, and a shunt admittance are given in Appendix B. For several

parallel admittances or series impedances the scattering matrix can be derived from the

equivalent admittance or impedance, respectively.

The scattering matrices for complex parallel and series connections, called also junctions,

connecting more than three electronic elements can be derived from the fundamental

matrices of the simple junctions given in Appendix B. In [46, 47], methods for the char-

acterization of various junctions using voltage and current waves are provided.

The scattering matrices of both the structures and discrete components are normalized

to a port reference impedance of 50 Ω. Because of the passivity property of the circuit

elements the symmetry of the matrices is fulffiled.

3.3 Nonlinear Component Modeling

In this thesis nonlinear devices are assumed only to appear at the terminations of the

propagation paths. The first part of this section describes the general model of a diode

which is frequently used in protection circuits of ICs against overvoltages. The second

part provides some examples of efficient models of chip ports used in circuit simulation.

3.3.1 Passive Nonlinear Devices

The most common nonlinear element used in microwave circuits is the schottky diode.

In signal integrity analysis the diode appears mainly in the protection circuits of digital

3.3. NONLINEAR COMPONENT MODELING 25

devices. The current-voltage characteristic of an ideal pn junction diode is described by

the equation

I=Isexp qeV

κ TK−1,(3.3.1)

where qe= 1.6022×10−19 C is the electronic charge, κ= 1.3806×10−23 J/◦K is the Boltz-

mann’s constant, TKis the absolute temperature in degrees Kelvin,Isis the saturation

current, which depends on the physical properties of the diode, and Vis the voltage across

the diode.

The dynamic conductance of a diode is defined as follows. When a constant voltage V0is

applied to the diode, a constant current flows through it. The slope of the curve (I, V ) at

the operating point V0is called the dynamic conductance of the diode. It is determined

as the derivative of Iwith respect to the voltage Vby

g(V0) = dI

dV V=V0

=Is

exp V0

VT,(3.3.2)

where VT=κ TK/qe.

Equation (3.3.1) is sufficient to describe the DC behaviour of the diode. At higher fre-

quencies additional parasitic effects have to be included into the diode model for more

accurate description. Parallel capacitances come into the model which are dependent on

the voltage across the diode [48, 49]. The dynamic model of the diode is depicted in

Figure 3.3.1.

CDCj

Figure 3.3.1: Dynamic model of the diode

In Figure 3.3.1, RSrepresents the bulk resistance which is assumed to be constant. The

capacitances Cjand CDare called the depletion and diffusion capacitance, respectively.

The depletion capacitance is defined as

Cj=









Cj0

1−V

φη,for V≤φ−φ0

K1V+K2,for V > φ −φ0,

(3.3.3)

26CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

where ηis the grading coefficient and is comprised between 0.33 and 0.5. A typical value

of the built-in potential φof the diode is 0.8. φ0is a constant value which depends on

the material of the diode and is between 0.05 and 0.5. The constant Cj0is the capacity

of the junction when V= 0 and depends on the physical construction of the diode. V0is

the barrier voltage which depends on the material.

The parameters K1and K2in (3.3.3) are defined by

K1=dCj

dV V=φ−φ0

K2=−K1(φ−φ0) + Cj|V=φ−φ0.

The diffusion capacitance is defined by

CD=





τD

dV , V > 0

0, V ≤0

,(3.3.4)

where τDis the transient time.

The diode is one of the powerful devices for chip ESD protection due to its low trigger

voltage, low turn-on resistance, and high ESD robustness. The function of the diodes

is to clamp the ESD overstress and to transfer it to the ground. The basic approach to

absorb the discharge is shown in Figure 3.3.2(a). The protection circuit must provide

the required level without degrading the input signal or the characteristics of the internal

circuit. There are different protection topologies depending on the type of the chip pin

to be protected. An example of ESD protection structure constructed from double clamp

diodes for I/O pin is shown in Figure 3.3.2(b). A negative ESD impulse will cause the

lower diode to forward bias, thereby transferring discharge through the lower diode into

ground. A positive impulse however, causes the upper diode to forward bias and the

discharge is transferred into Vcc. The capacitance connecting Vcc to ground dissipates the

discharge into ground. Instead of schottky diodes zener diodes can also be used. The

capacitance of the zener diodes from the I/O pin to ground is higher. Therefore, they are

not suitable to high-speed signals.

3.3.2 Active Device Models

Simulation of digital I/O buffers, together with their chip packages and printed circuit

boards, can mainly be done by many approaches. The traditional approach is to use

transistor level models, which is particularly useful when small circuits should be simu-

lated. This approach would be very time consuming for simulations of a large number of

buffers and their interconnections. As an alternative solution to this problem, behavioural

models of devices such as I/O Buffer Information Specification (IBIS) are introduced [50].

The behavioural IBIS modeling data can be derived from measurements as well as circuit

simulations. Simulations with behavioural models can be generally executed faster than

the corresponding simulations with transistor level models.

3.3. NONLINEAR COMPONENT MODELING 27

ESD

Protection

Circuit

Internal

Circuit

Vcc

GND

(a)

Internal

Circuit

Vcc

GND

(b)

Figure 3.3.2: Typical I/O ESD protection circuit

SPICE transistor level models are single buffer centric. They often represent one of several

inputs or outputs of a buffer. However, IBIS models are pin specific, the model describes

all pins of the physical component. A complete IC contains different models, depending

on the number of different driver and receiver types of the device [51]. A set of I/O pins

that have the same characteristic behaviour can be grouped together into one model. The

data are stored in forms of current-voltage tables, and switching and package information.

The pins are classified as input, output, 3-state, I/O, open drain, power, GND, and NC

pin. The model for an I/O buffer is represented in Figure 3.3.3.

Rise

Fall L−pkg R−pkg

C−pkg

C−comp

Figure 3.3.3: IBIS I/O buffer specification [50]

In this figure the blocks 1 and 2 represent the pulldown and pullup transistors of a

digital device I/O buffer output stage. Block 3 consists of DC I/V-tables representing the

ESD clamping diodes, power clamp and GND clamp. Block 4 represents the transition

time of the output as it switches from one logic state to another. Rise and fall times

are represented by the ratios of transition voltage to transition time dV/dt. Block 5

represents the die capacitance C−comp of the input pin and the package parasitics of

that pin. The package characteristic resistance, inductance and capacitance are denoted

by R−pkg,L−pkg, and C−pkg, respectively. These represent the models of the bond wire

and pin combination of the package. The model of the pin package is very important to

make an accurate characterization of the input signal at high frequencies. The schematic

28CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

representing the input stage consists only of the blocks 3 and 5.

IBIS is a data format including typical curves in tabular form, which contains dynamic

and static characteristics in three different conditions given as typical, minimum and

maximum values. IBIS models offer higher numerical efficiency than SPICE models. In

addition they are capable of maintaining suitable accuracy since the nonlinear aspects of

I/O structures, as well as package parasitics and ESD structures, are considered in the

model parameters.

Digital devices can be electrically described in time domain by accurate transistor level

models, or IBIS behavioural models. In the frequency domain linear approximations must

be made for the ports characteristics of nonlinear digital devices. Linear models are very

efficient to simulate, but lumped element model of digital IC do not provide the accuracy

needed for the signal integrity analysis. In [52] linear models representing the driver

switching behaviour of an IC, and which consist of a shunt RC at the IC-ports to GND

and a shunt capacitance Cto Vcc, are presented. Figure 3.3.4 shows these linear models

and their simple variants.

Vcc

GND

SIG 1

SIG 2

SIG n

Cvcc

(a)

SIG 1

SIG 2

SIG n

GND

(b)

Figure 3.3.4: Linear IC-port model: (a) general model, (b) simple model

3.4 Analysis of a Complete Signal Propagation Path

Physical paths on a printed circuit board include all the interconnected transmission struc-

tures connecting present electronic devices. They contain connectors, cables, PCB tracks

like microstrip and strip lines, discontinuities like vias, bends, and discrete linear and

nonlinear components such as resistors, capacitors, diodes, etc. The elements belonging

to a coupling path can be grouped into

•Linear elements: transmission lines, discontinuities, discrete components

•Nonlinear elements: diodes, IC I/O pins

Each of the components above can be considered as a small module. Discontinuities

and nonlinear components can be represented by simplified equivalent circuit models.

3.4. ANALYSIS OF A COMPLETE SIGNAL PROPAGATION PATH 29

These models can be derived in terms of lumped element circuit using resistors, inductors,

capacitors, transmission lines, and dependent voltage and current sources. The resulting

network from all these models generally produces an approximated model to the original

network.

Usually linear elements are well modeled in the frequency domain. However the behaviour

of nonlinear elements is analyzed in the time domain. A variety of circuit simulators use

linearized models of nonlinear devices and then perform a transient simulation. Alterna-

tively, there are also different hybrid approaches combining between both analysis.

The analysis of a complete signal propagation path from a noise source to a chip pin

requires the characterization of all the circuit elements along this path. The main parts

of a signal path at a circuit board level are the physical paths present in the system. IC

Drivers and receivers may be present at the terminations of signal paths.

Interconnect structures with complex geometry are treated as lumped multiports de-

scribed by passive macromodels or directly by their frequency domain data. In order to

identify dominant propagation paths, all the substructures on the PCB must be charac-

terized. Accurate and efficient models for each of these substructures lead to the reduction

of the analysis complexity.

Discontinuities in the noise propagation paths can strongly affect the signal behaviour at

the terminations of the paths. At the PCB level they constitute the critical parts which

decide how and where the noise will flow to the victim device. A proper modeling of

discontinuities should take into account geometry and material properties, thus requiring

a complex full wave electromagnetic analysis. Instead of applying this costly analysis to

the entire system, the subparts are analyzed separately. Each substructure is characterized

via full wave analysis. It is very important to limit the set of the substructures that should

be characterized small when partitioning the system. This can be reached by considering

only coupling between neighbouring transmission lines which is called first level coupling

before performing field simulation. As a result larger coupling effects are neglected and

errors may be produced at high frequencies. More accurate simulation results can be

obtained by taking into account higher order coupling, which requires more complex test

structures.

Circuit drivers and receivers are usually buffers characterized by strong nonlinearities and

relevant dynamic effects. Their intrinsic nonlinear and dynamic behaviour can signifi-

cantly affect the shape of the noise impulses propagating. SPICE transistor level models

and IBIS behavioural models of IC buffers are the most popular models used in the signal

integrity analysis.

In conclusion the main steps usually used for the simulation of signal paths are:

1. Simulation of the parasitic behaviour of the transmission structures by the use of a

2D, 2.5D, or 3D field solver

2. Combination of these simulation parameters with the driver and receiver models of

ICs as transistor based models or in the IBIS format.

3. Perform an electric simulation of the whole system

30CHAPTER 3. ELEMENTS OF A NOISE PROPAGATION PATH AT THE PCB-LEVEL

Chapter 4

Analysis Techniques of Large

Circuits

This chapter provides an overview of the techniques mainly used for the simulation of

microwave circuits. All these techniques are based on the formulation of the circuit

equations using specific variables. The choice of a given technique depends on some

features like the size, the topology, and the variables to be determined.

4.1 Basic Circuit Analysis Techniques

At low frequencies the analysis of electrical circuits is performed in terms of voltages

and currents at the circuit terminals. The nodal admittance matrix is the most used

method for computer-aided analysis of linear circuits in the frequency domain. When

high frequency parasitics should be characterized, scattering matrix analysis are preferred

[45]. Their derivation is based on introducing of power, voltage and current waves. In this

section methods based on power waves are described. More details on analysis methods

formulated in terms of voltage and current waves, known as Baum-Liu-Tesche (BLT)

equations, can be found in [53, 54, 55].

4.1.1 Nodal Admittance Analysis

The nodal admittance matrix is derived on the basis of the Kirchhoff ’s current law equa-

tions at the circuit nodes. The voltages at all nodes in the circuit are assumed to be

known. The solution for the currents is given by

I=Y V ,(4.1.1)

where Yis a square nodal admittance matrix, its degree equals the number of nodes in

the circuit. Vis a vector of node voltages, and Iis a vector of terminal currents of the

independent sources.

32 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

A more useful variant of the nodal admittance matrix is the indefinite admittance ma-

trix. This method reduces the memory space and computation time requirements in the

analysis of large circuits by deviding a circuit into subcircuits and separately computing

the indefinite admittance matrices of the successive circuits connected to others. The ref-

erence node is located outside of the subcircuits. At each step a subcircuit is considered

and its nodes are ordered into internal and external ones. For a subcircuit consisting of

many multiports, the nodes connecting these multiports are the internal ports and the

others are external nodes. The admittance matrix of the subcircuit can be written as

Ie

Ii=Yee Yei

Yie Yii Ve

Vi,(4.1.2)

where Ieand Veare the vectors of the currents and voltages relative to the external nodes

of the resultant circuit, Iiand Viare the vectors of the currents and voltages relative to

its internal nodes.

The resulting indefinite admittance matrix of this subcircuit, which relates voltages and

currents at its external ports, can be derived from (4.1.2). It is given as

Ye=Yee −Yei Y−1

ii Yie.(4.1.3)

4.1.2 Connection Matrix Method

The connection matrix method is applicable when the network contains arbitrarily inter-

connected multiports and independent voltage or current sources. Its derivation is based

on the formulation of the connectivity between the ports of the components that are

connected with each other. All ports in the network are assumed to be connected [45, 37].

In a network with mmultiport components, the incoming and outgoing wave variables ai

and biat the ports of the i-th component having nports, are related by the scattering

matrix Sias

bi=Siai.(4.1.4)

Considering the waves impressed by the independent sources to the mmultiport compo-

nents, represented by the wave vector c, the relation (4.1.4) becomes

b=S a +c.(4.1.5)

In (4.1.5) the supervectors a,b, and care defined by

a=











,b=











,c=











where, ai,bi, and ci, for i= 1,2, ..., m, are the subvectors representing the waves at the

ports of the multiport component i.

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 33

The supermatrix Sis defined by







S1··· 0··· 0

.··· .

0··· Si··· 0

.··· .

0··· 0··· Sm







=diag(S),

where, Sifor i= 1,2, ..., m, are the scattering submatrices of the individual multiports.

The matrix Sis a block matrix whose submatrices along the diagonal are the scattering

matrices of various ports, and zeros represent null matrices. For a pair of connected ports,

the outgoing wave variable at one port must be equal the incoming wave variable at the

other, assuming that the wave variables at the two connected ports are similarly normal-

ized. The connectivity between two ports is illustrated in the subnetwork of Figure 4.1.1.

M N

bkaj

Figure 4.1.1: A subnetwork showing a connection between two ports

For example, if port jof one component is connected to port kof another component as

shown in Figure 4.1.1, the incoming and outgoing waves satisfy

(aj=bk

ak=bj

.(4.1.6)

When the reference impedances of the two ports are equal, the two equations in (4.1.6)

may be written in a matrix form like

bk

bj=0 1

1 0 ak

aj.

This matrix contains only 1’s and 0’s because the normalizing impedances for the two

ports are assumed to be equal. Considering all the interconnections within a network,

one gets an equation like

b=P a,(4.1.7)

34 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

where, Pis a connection matrix describing the network topology. In each row of Pall

elements are zero except an entry 1 in the column indicating the interconnection. From

(4.1.5) and (4.1.7), one can get

a= (P−S)−1c.(4.1.8)

In this equation cis a vector of impressed wave variables and (P−S) is the connection

scattering matrix. The solution of this equation gives the incoming waves aat all the

component ports in the network, the outgoing waves bcan be obtained from equation

(4.1.7). The main diagonal elements in the matrix (P−S) are the negative values of the

reflection coefficients at the various components ports. The elements corresponding to

the ports of the same component are the negative of the transmission coefficients, and all

other elements are zero except those corresponding to the two ports connected together.

The zero-nonzero pattern depends only on the topology and does not change with fre-

quency. For a transmission line switched between nodes jand kwith a length ljk, the

propagation equation in (4.1.7) becomes

bj!= 0e−γljk

e−γljk 0! ak

aj!,

where γ=α+jβ is the propagation constant. αis the attenuation constant and βis the

phase constant. If the transmission line is lossless, the last expression becomes

bj!= 0e−jβljk

e−jβljk 0! ak

aj!.

Crosstalk Circuit Example

In this example, the connection matrix method is compared to the conventional SPICE

frequency domain analysis. Figure 4.1.2 shows a circuit consisting of three pairs of parallel

coupled microstrip transmission lines [56].

The lengths of the lines are: l1=5 cm, l2=4 cm, and l3=3 cm. The per unit length matrices

characterizing the coupled microstrips are given by the following matrices:

R= 75 15

15 75 !Ω

m,L= 494.6 63.3

63.3 494.6!nH

G= 0.1−0.01

−0.01 0.1!S

m,C= 62.8−4.9

−4.9 62.8!pF

The simulation results are given for the lossless and lossy cases in Figure 4.1.3. In the

lossless case, the per unit length matrices Rand Gare not considered. The wave variables

are computed at all the network ports and transformed into voltage ones. Then, the

results are presented in the Figures 4.1.3(a) and 4.1.3(b) in terms of the voltage transfer

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 35

100

10n

(1)

(2)

(3)

Figure 4.1.2: A transmission line circuit example (R1=25Ω, R2=50Ω, R3=75Ω,

R4=100Ω, C1=1 pF, C2=2 pF, L=10 nH) [56]

function at the node trespectively. The curves of the responses are compared to the

SPICE simulations.

In both cases the results of the connection matrix method are close to the ones provided

by the SPICE simulations over the frequency range of 2 GHz. For the lossless case a small

difference of the curves representing the connection matrix method and that of the SPICE

model is observed above the frequency of 1.8 GHz.

Frequency (GHz)

V1Magnitude (mV)

SPICE Simulation

Connection Matrix Method

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

(a)

Frequency (GHz)

V1Magnitude (mV)

SPICE Simulation

Connection Matrix Method

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

(b)

Figure 4.1.3: Voltage amplitude at the node 1

To conclude, the connection matrix method is an easy technique for the simulation of mi-

crowave circuits using the scattering parameters. The high frequency parasitic behavior of

the circuit layout can be included into the analysis considering the scattering parameters of

the transmission structures interconnecting the devices, and the connectivity information.

36 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

4.1.3 Transfer Scattering Matrix Method

The transfer scattering matrix in its classical form describes multiports with the same

number of input and output ports. For a multiport with ninput ports and noutput

ports, the scattering matrix is defined by

bin

bout =S11 S12

S21 S22  ain

aout ,(4.1.9)

where S11,S12,S21, and S22 are the scattering submatrices, ain, and bin are the vectors

of incoming and outgoing waves at the ninput ports of the 2 n-multiport respectively,

aout, and bout are the vectors of incoming and outgoing waves at the noutput ports of

the 2 n-multiport.

The transfer scattering matrix Tcan be derived from (4.1.9) by ordering the input and

output waves at both sides of the multiports as

bin

ain != S12 −S11S−1

21 S22 S11S−1

S−1

21 S22 S−1

21 ! aout

bout !=T aout

bout !(4.1.10)

If the number of the input and output ports is not equal, the submatrix S21 is not a square

matrix and therefore its inverse does not exits. Consequently the transfer scattering

matrix does not exist. To solve this problem, the scattering matrix is extended to have

the following form





bin

bout

be

=



S11 0S12

S21 SbS22

ScSd0





ain

aout 

,(4.1.11)

where beis a vector of additional virtual outgoing wave variables, aeis a vector of addi-

tional virtual incoming wave variables, all equal zero by definition, ae=0. Virtual waves

aeand becorrespond to virtual input ports that do not really exist. Sb,Sc, and Sdare

blocks of the extended square submatrix

21 =S21 Sb

ScSd.(4.1.12)

The number of columns in the submatrix Sbequals the number of the new added virtual

incoming wave variables located in the vector ae. Similarly the number of rows in the

submatrix Scdefines the number of the new added virtual outgoing wave variables be. The

equivalent circuit represented by the extended scattering matrix Sis shown in Figure 4.1.4.

The virtual ports do not exist physically.

Three different configurations of multiports may arise. If the number of input ports nis

smaller than the number of output ports m, then

21 =S10

S31m−n,(4.1.13)

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 37

bin

ain

aout

bout

n m

Figure 4.1.4: Extended network with virtual ports associated to the waves

ae, and be[45]

where 1m−nis the (m−n)×(m−n) unit matrix, and the generalized transfer scattering

matrix can be computed as







bin

ain







=





S12 −S11 S−1

10S22 S11S−1

−S−1

10S−1

S3S−1

1−1n−m−S3S−1





 aout

bout !.(4.1.14)

In the case of equality, that’s n=m, the submatrix does not need to be extended. If the

number of input ports nis bigger than the number of output ports m, then

21 =S1S2

01n−m,(4.1.15)

and the generalized transfer scattering matrix is

bin

ain =





S12 −S11 S−1

0!S22 S11 S−1

0!S11 S−1

1S2

−S−1

1S22 S−1

1−S−1

1S2

0 0 1









aout

bout



.(4.1.16)

For the analysis of cascaded microwave circuits composed of n-ports with the same port

impedance, the input and output waves and the transfer scattering matrix may be re-

38 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

ordered to give







bin1

ain1

bin2

ain2













aout1

bout1

aout2

bout2

be1

ben−m







The transfer scattering matrix method of a circuit with 2 n-ports is computed by the

product of the transfer scattering matrices of the individual cascaded components it con-

sists of. The generalized case of a cascaded connection of two multiports is shown in

Figure 4.1.5.

{

}

{

}

v21

u12 v22

u11

Figure 4.1.5: Generalized case of cascaded multiports [45]

In order to derive the transfer scattering matrix in the generalized case of cascaded two

multiports, the following wave variables are introduced:

v1= (bin1, ain1, bin2, ain2,...)T: vector of wave variables at input ports of the first element,

u11 = (aout1, bout1, aout2, bout2,...)T: vector of wave variables at the first element output

ports not connected with the input ports of the second element,

u12 = (aoutn, boutn, aoutn+1, boutn+1,...)T: vector of wave variables at the first element

output ports connected with the appropriate input ports of the second element,

v22 = (ain1, bin1, ain2, bin2,...)T: vector of wave variables at the second element input

ports connected with the appropriate output ports of the first element,

v21 = (aout1, bin1, ain1+1, bin1+1,...)T: vector of wave variables at the input ports of the

second element,

u2= (aout1, bout1, aout1+1, bin1+1,...)T: vector of wave variables at output ports of the

second element.

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 39

The transfer scattering matrix for the first element is

v1

01=A11 A12 A1e

A01 A02 A0e



u11

u12

be1

,

and for the second element





v21

v22

02

=



B11 B1e

B21 B2e

B01 B02 

u2

be2,

where 01,02are null vectors corresponding to the incoming waves at the additional

virtual input ports, respectively, of the first and second elements, be1,be2are vectors of

the outgoing waves at the additional virtual output ports, respectively, of the first and

second elements. The vectors of incoming and outgoing waves at input ports and output

ports of the cascade are:

v=vT

1,vT

21,0T

1,0T

2T

u=uT

11,uT

2,bT

e1,bT

e2T

After reordering of the individual transfer scattering matrices and their multiplication, one

gets the resulting transfer scattering matrix of the two cascaded multiports in Figure 4.1.5







A11 A12B21 A1eA12B2e

0B11 0B1e

A01 A02B21 A0eA02B2e

0B01 0B0e







Application Example

The generalized transfer scattering matrix is applied to the single layer PCB shown in

Figure 4.1.6. The subcircuit in Figure 4.1.6(a) consists of parallel microstrip lines mounted

on a dielectric substrate of thickness 1 mm and with a relative permittivity of 4.3. This

subcircuit, denoted B, is used to construct the cascaded circuit analyzed, which is depicted

in Figure 4.1.6(b). The microstrip transmission lines and the ground plane, of finite

thickness 100 µm, are assumed to be lossless. All the lines have the length l=4 cm. The

widths of the microstrips and spacing between them have the same values within the

individual structures. These values are 1 mm and 0.5 mm for the three and two coupled

lines, respectively.

The microstrips structures are characterized using the HSPICE MoM solver. The par-

asitic coupling between the three-parallel lines is given by the following per unit length

40 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

(a)

(b)

Figure 4.1.6: Schematic of the studied cascaded structures: (a) subcircuit, (b) whole circuit

inductance and capacitance matrices

L=





393.43 80.47 27.55

80.47 390.4 80.47

27.55 80.47 393.43







m,C=





85.26 −9.39 −0.73

−9.39 86.64 −9.39

−0.73 −9.39 85.26







whereas the two coupled lines are characterized by the parasitic inductance and capaci-

tance matrices

L= 499.70 176.91

176.91 499.70 !nH

m,C= 67.17 −16.88

−16.88 67.17 !pF

The frequency domain response is determined in terms of the voltage transfer function

between the terminals 1 and 2 specified in the circuit schematic. The transfer scattering

matrix Tof this circuit is computed and then converted into corresponding scattering

matrix Sin order to solve the voltage transfer function. The resulting response is com-

pared with the frequency domain HSPICE circuit simulation. Figure 4.1.7 shows a good

convergence between the results obtained by the generalized transfer scattering matrix

and that of the HSPICE simulation.

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 41

Frequency (GHz)

V2/V1(V)

Transfer Scattering Matrix

HSPICE Simulation

0 0.5 1 1.5 22.5 3 3.5 4 4.5 5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Figure 4.1.7: Far-end crosstalk voltage

4.1.4 Multiport Connection Method

The multiport connection method allows for the computation of large linear circuits using

an iterative procedure. The circuit characteristics are computed considering at each step

a part of the circuit. The size of the circuit decreases each step by the number of the

internal ports in the subcircuit processed. Thus at the last step the number of the ports

in resulting circuit equals the sum of the terminations and the number of the independent

sources [45]. Figure 4.1.8 illustrates the concept of external and internal ports used by

the multiport connection method.

Figure 4.1.8: A subcircuit showing internal and external ports, and

its equivalent multiport

When one or more independent generators are present in a network, these can be treated

as existing outside the remaining network and the present method yields the scattering

matrix for the network. This network contains iinternal ports and eports external to it.

If there are mcomponents in the network the governing relations for all components can

be written together as

b=S a.(4.1.17)

42 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

The rows and columns in (4.1.17) can be reordered so that the wave variables are separated

into two groups, the first corresponding to the eexternal ports, and the second to i

internally connected ports. Equation (4.1.17) can now be written as

be

bi=See Sei

Sie Sii ae

ai,(4.1.18)

where beand aeare the vectors of the wave variables at the eexternal ports, and biand

aiare the the vectors of the wave variables at the internal ports. The interconnection

constraints for the iinternal ports can be written as

bi=P ai,(4.1.19)

where Pis the connection matrix obtained in the same way as in Section 4.1.2. The

manipulation of (4.1.18), and (4.1.19) gives the relation

P ai=Sie ae+Sii ai.

The vector aican be computed as

ai= (P−Sii)−1Sie ae.(4.1.20)

The network scattering matrix Seis then computed from (4.1.18) substituting the ex-

pression for aiin (4.1.20). It is given by

Se=See +Sei (P−Sii)−1Sie.(4.1.21)

Equation (4.1.19) and (4.1.21) can be used to obtain the wave variables at the internal

ports for any arbitrary excitation at the eexternal ports.

The multiport connection method, which uses the scattering parameters, is an analogous

and iterative way to the indefinite admittance matrix described in Section 4.1.1. They

differ only in the variable used. Both methods can be implemented to allow automatic

computation of large circuits in the frequency domain. The pseudo-code of the algorithm

developed is given by

Algorithm 4.1.1 MultiPort Connection Method

1: Compute circuit constraints: degree of nodes, adjacent components for each mul-

tiport

2: repeat

3: Select a multiport component with a maximum number of ports

4: Get its adjacent multiports and construct a current subcircuit

5: Compute the equivalent multiport matrix relating external ports of current

6: subcircuit

7: Update global netlist: remove components processed and update

8: connections

9: until number of multiports is 1

4.1. BASIC CIRCUIT ANALYSIS TECHNIQUES 43

To make time domain simulation the resulting circuit matrix can be included in a HSPICE

netlist.

Application Example

Figure 4.1.9 shows a microstrip line circuit analyzed using the multiport connection

method. The microstrip traces (of width 200 µm and height 35 µm) are separated by

a space of 200 µm above a FR4 (εr= 4.2) dielectric substrate of 365 µm height. The

length of all the transmission lines is 3 cm. The microstrip lines are characterized over the

frequency range of 1 GHz. The termination resistances R1, ..., R15 are chosen to be 50 Ω.

V15

R15

Figure 4.1.9: Example of interconnect circuit

The voltage phasor at the node 90 is computed over the frequency bandwidth of 1 GHz.

That’s the voltage response corresponding to a Dirac impulse response applied at the

sources. Obviously, and as shown in Figure 4.1.10 the curves representing the magnitude

and phase responses determined using the multiport connection method are identical to

that provided by the circuit simulator HSPICE.

Frequency (GHz)

V90 (V)

HSPICE Simulation

Multi-port Connection M.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.98

1.02

1.04

1.06

1.08

1.1

1.12

Frequency (GHz)

V90 Phase (◦)

HSPICE Simulation

Multi-port Connection M.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-200

-150

-100

-50

100

150

200

Figure 4.1.10: Magnitude and phase of the transfer function at node 90

To investigate in the time domain analysis of this circuit with digital components the resis-

tive loads are replaced by 5 V CMOS inverters SN74LV04A of Texas Instruments [57]. The

44 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

Time (sec)

V90 (V)

Multi-port Connection M.

SPICE Simulation

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

×10−7

-1

(a)

Time (sec)

V90 (V)

IBIS Models

SPICE Models

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

×10−7

-1

(b)

Time (sec)

V90 (V)

Multiport Connection M.+IBIS Models

Multiport Connection M.+SPICE Models

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

×10−7

-1

(c)

Time (sec)

V90 (V)

Multiport Connection M.+IBIS Models

SPICE Simulation

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

×10−7

-1

(d)

Figure 4.1.11: Time domain response at node 90

output ports of these inverters are loaded by parallel circuits R C (R= 500Ω , C=50 pF).

The voltage sources are trapezoidal waves with transition times of 5 ns, widths of 25 ns,

and periods of 50 ns. The frequency domain data characterizing the linear circuit part

can be combined with SPICE or IBIS models of the inverter buffers. The time domain

responses of combining the conventional SPICE circuit analysis, the multiport connection

method, the SPICE and IBIS models of the inverter are depicted in Figure 4.1.11.

In Figure 4.1.11(a) the SPICE time domain analysis of the circuit is compared with

the multiport connection method combined under the use of SPICE macromodels of the

buffers. In Figure 4.1.11(b) the SPICE transient analysis is represented for both SPICE

and IBIS models. In Figure 4.1.11(c) the results of the multiport connection method

combined with SPICE and IBIS models are compared. In Figure 4.1.11(d) the SPICE

analysis is compared to the multiport connection method combined with IBIS models. For

all these cases the curves representing the results of all the combinations of the methods

and models are close to each others.

An important factor in the choice of the simulation method is the efficiency. For this

4.2. CIRCUIT ANALYSIS BY SIGNAL FLOW GRAPHS 45

purpose the speed of all the combinations analyzed in Figure 4.1.11 is computed on a

Sun SPARC Station with 2 processors of 359 MHz. The run time required for each

simulation is given in Table 4.1.1. It is clear that the simulation considering the whole

circuit matrix and transistor level model requires not only large memory resources, but

also more CPU time (110.5 sec), whereas the use of the multiport connection method in

a preprocessing step can save a lot of memory resources. The use of IBIS behavioural

models of the inverter buffers leads to significant efficiency increase with comparison to

the conventional time domain analysis (21.3 sec).

SPICE Transient Analysis Multiport Connection Method

SPICE Macromodels 110.5 sec 51.2 sec

IBIS Models 33.2 sec 21.3 sec

Table 4.1.1: Average CPU time for different combinations of methods and models

4.2 Circuit Analysis by Signal Flow Graphs

Another way to represent an electrical network is the graph model. The behaviour of

an electrical network can be analyzed by observing and solving the relevant properties

of the corresponding graphs. There exist different types of graphs to model an electrical

network depending on the physical quantities considered and the topology in which the

components are connected. In this section basic concepts and terms in graph theory,

that are of great importance for the derivation of a signal tracing approach, have been

introduced and discussed [58, 59].

4.2.1 Basic Notions on Graphs

A graph G′= (V′, E′) is a simple structure consisting of a finite set of vertices V′=

{v′

1, v′

2, ...}and a set of edges E′={e′

1, e′

2, ...}, such that each edge e′

kis identified by

an unordered pair (v′

i, v′

j) of vertices. The number of vertices is denoted by nand the

number of edges is denoted by m. The vertices v′

i, and v′

jassociated with the edge e′

kare

called the end vertices of e′

k. An edge which has the same vertex as both its end vertices

is called a self-loop. Each pair of vertices may be connected by many edges called parallel

edges. A graph G′is said to be weighted if there is a real number associated with each

edge of G′. A graph is named directed, or digraph, if the edges are assigned a direction.

This is represented by their arrows in the graph. Throughout this thesis the terminology

of directed graphs is defined.

In directed graphs an edge is incident into or incident out of a vertex. The vertex v′

which edge e′

kis incident out of, is called the initial vertex of e′

k. The vertex v′

j, which

edge e′

kis incident into, is called the terminal vertex of e′

k. An edge for which the initial

and terminal vertices are the same forms a self-loop. The number of edges incident out

of a vertex v′

iis called the out-degree of v′

i. The number of edges incident into a vertex

46 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

v′

iis called the in-degree of v′

i. If the in-degree of every vertex v′

iequals its out-degree,

the graph is called balanced. A digraph H′is said to be a subgraph, smaller portion, of

a graph G′if all the vertices and all the edges of H′are in G′, and each edge of H′has

the same vertices in H′as in G′. Two subgraphs H′

1and H′

2of a graph G′are said to

be edge disjoint if they do not have any edges in common, but they may have vertices in

common. Subgraphs that do not have vertices in common are said to be vertex disjoint.

A walk is defined by a set of sequence of vertices and edges, beginning and ending with

vertices, such that each edge is incident with the vertices preceding and following it. In a

walk no edge appears more than once. A walk is named a simple path if no vertex appears

more than once. That means a path does not intersect itself. The vertices with which a

path begins and ends are called its terminal vertices. In digraphs the path is associated

an orientation, such that each edge is oriented from the vertex preceding it to the vertex

following it. In a weighted graph the length of a path is defined by the sum of the weights

of all edges belonging to this path. A circuit is a walk in which the first and last vertices

are the same. A directed graph which does not contain a circuit is called acyclic graph.

A graph G′is connected if we can reach any vertex from any other vertex by traveling

along the edges. In other words there is at least one path between every pair of vertices

in G′. In a connected graph the distance d(v′

i, v′

j) between two of its vertices v′

i, and v′

jis

the length of the shortest path connecting them. A disconnected graph consists of many

connected graphs each of these disjoint subgraphs is called a component.

An important term in graph theory is the notion of a tree. A tree is a simple connected

graph without any circuits, i.e. having neither a self-loop nor parallel edges. There is

only one path between every pair of vertices in a tree. In a graph that is not a tree, there

are generally several paths between a pair of vertices. A special case of a tree is a rooted

tree with a start vertex which is distinguished from the other vertices. A straightforward

application of trees is in search procedures.

In many applications of graph theory, such as in electrical network analysis, matrices

are used to store the topology of a graph and then analyze the problem. A matrix

representation is a useful tool to investigate the properties of a graph by means of a digital

computer. Examples of such matrices are the incidence and the adjacency matrices.

A special type of a directed graph is the signal flow graph (SFG). It is used in the past in

control theory. In this thesis signal flow graphs are used to represent the parasitic coupling

paths between the ports of the transmission structures in a passive linear network.

4.2.2 Signal Flow Graphs

The analysis of linear systems is eventually reduced to solving the corresponding set of

simultaneous linear equations. Alternative methods to the matrix methods are based on

SFGs that contain the same information as the equations from which it is derived. The

analysis of such linear systems consists of generating of a corresponding SFG and then

solving for the required dependent variable. By the construction vertices are labelled and

edges {e′

1, e′

2, ..., e′

m}are associated appropriate weights. Usually in a SFG, the vertices

4.2. CIRCUIT ANALYSIS BY SIGNAL FLOW GRAPHS 47

{v′

1, v′

2, ..., v′

m}are directly represented by signal variables {x1, x2, ..., xm}in the equations.

An edge from xito xjmeans that variable xjdepends on variable xi. The dependency

is expressed by the direction of the edges. The coefficients in the equations are assigned

as the weights of the edges, such that the variable xkis equal to the sum of all products

wik xiwhere wik is the weight of the edge coming into xkfrom xi. Signals travel along the

edges and are multiplied by the weights of the edges traversed. The variable xjequals

all incoming signals, and is the strength of the signal in each outgoing edge from xj.

The weights in signal flow graphs are called the edge gains, and independent vertices are

referred to as sources. Each vertex xkrepresents one equation of the system in which xk

is the sum of the products of the weights of all incoming edges and the labels of the initial

vertices of these edges. A vertex xiis a sink if no edges originate from xi. A vertex xiis a

source if no edges terminates at xi. A sink xiis an input if only one edge originates from

it. A source xiis an output if only one edge terminates at xi. It is in many applications

very interesting to solve for one unknown variable as a function of another independent

variable. In general this procedure requires the manipulation of the edges and vertices of

the SFG so that a simplified graph is obtained. The four elementary rules to reduce a

SFG are shown in Figure 4.2.1.

x1x2

aba b

(a)

a+b

(b)

1−c

(c)

dab

(d)

Figure 4.2.1: Signal flow graph reduction rules

48 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

By the series rule in Figure 4.2.1(a) the edge weights of two successive edges in series

can be combined into one edge by multiplying their individual weights. When multiple

edges connecting the same two vertices exist, the associated edge weights can be added

as shown in Figure 4.2.1(b). A loop with the gain c, as shown in Figure 4.2.1(c), can be

eliminated if all other edges into the vertices are devided by the factor (1 −c). A vertex

with multiple input or output edges can be split into multiple equivalent vertices with

each of the separate input edges connected to the new vertices provided that each new

vertex contains all of the output edges. Similarly, the vertices will be equivalent if each

new vertex connects to each of the original output edges provided that each new vertex

is connected to all of the original input edges as depicted in Figure 4.2.1(d).

To determine the transfer function from a SFG applying these reduction rules requires

visual inspection on the graph. An alternative method which does not depend on visual

inspection is the Matrix from of Mason’s gain rule. It is based on the determination of

directed paths and their associated transfer functions.

Within this thesis the flow of parasitic noise is determined on the basis of signal propaga-

tion paths. These paths include all coupling subpaths relating the ports of the individual

network structures. The electrical network, assumed to be linear, consisting of transmis-

sion lines and passive discrete components are represented by their SFGs. The individual

subgraphs are concatenated to build the whole network. The network elements are rep-

resented by asymmetrical SFGs. That means vertices are joined by most one edge and

there is no self-loop in the signal flow graph. The edges of the graph are associated real

weights computed using a metric depending on electrical properties of the components.

The vertices represent the electrical signals, like waves, and voltages, that have to be de-

termined. For the analysis of microwave networks usually the flow of the power, expressed

in terms of transmitted and reflected power waves, is used. A four-port network, charac-

terized by its scattering parameter matrix S, and the corresponding SFG are depicted in

Figure 4.2.2.

Figure 4.2.2: A four-port network and its associated signal flow graph

4.2.3 Transfer Function in Signal Flow Graphs

Mason’s rule is a way to determine the transfer function between any input and any

output vertices in a SFG. The transfer function can be derived by studying the features

4.2. CIRCUIT ANALYSIS BY SIGNAL FLOW GRAPHS 49

of the SFG representing the microwave network. There are two variants of this formula.

The first variant is based on the determination of the circuits, i.e. cycles, and the paths

in the network graph. The second however, requires only the determination of the simple

paths, which are sufficient to derive the transfer function using the associated network

subgraphs, or submatrices [58].

Signal flow graphs representing a microwave network containing many transmission struc-

tures characterized by their multiports parameters consist of big number of cycles and

paths. The determination and storage of all these features, using the first variant, seems

to be a difficult task when analyzing large circuits with complex topology. In this sec-

tion the second variant representing an alternative procedure, which requires only the

knowledge of the paths, is described.

To derive the transfer function between two vertices in a SFG the set of linear equations

describing the network should be written in a matrix. For this purpose consider a signal

flow graph G′with vertices x1, ..., xnand source vertices y1, ..., ynrepresenting the external

signals at the vertices xi, i = 1, ..., n. There exist different representations of the network

equations depending on the order in which the variables xi, and yi, i = 1, ..., n are written.

A particular type of the set of linear equations representing the graph G′is defined by

(1 −w11)x1−w12x2−... −w1nxn=y1

−w21x1+ (1 −w22)x2−... −w2nxn=y2

−wn1x1−wn2x2−... + (1 −wnn)xn=yn

(4.2.1)

In this equation the coefficients wij ∈C, i, j = 1, ..., n. Since the SFG of a microwave

network does not consist of self-loops, wii=0, for i= 1, ..., n. Under this condition, the

matrix corresponding to (4.2.1), which is named the structure matrix of the signal flow

graph G′, is given by







1−w12 ... −w1n

−w21 1... −w2n

... ... ....

−wn1−wn2... 1







.(4.2.2)

This matrix represents all states of the network. The solution of this system of equations

provides the values of the waves at the corresponding vertices of the graph. A trivial

solution can be obtained using the Gaussian elimination. In the case where the ratio of

an output variable to an input one is required the Cramer’s method can be used. Another

way to compute this ratio, keeping the information on signal flow, is the combination of

graph and matrix approaches. The cofactor of each path Pin the signal flow graph G′is

defined by the determinant of the underlying subgraph without the vertices belonging to

P. It is denoted by

∆P=det(G′,P).

Each directed simple path Pin a SFG is associated a gain denoted HP, which is the

product of all edge gains, i.e. weights, belonging to this path. For a path Pconsisting of

50 CHAPTER 4. ANALYSIS TECHNIQUES OF LARGE CIRCUITS

the sequence of vertices x1, x2, ..., xNand connected by the edges with weights wi,i+1, the

path gain is defined as

HP=

N−1

i=1

wi,j+1.(4.2.3)

The transfer function between any input and output nodes of a SFG can be determined

by computing of the directed paths and associated cycle gains. For an input vertex x1

and for each other vertex xj, j = 2, ..., n in the graph G′, the ratio of the signal variables

at both vertices xjand x1is expressed in terms of all directed paths Pathj1relating these

vertices. It is defined as

xj=X

P∈P athj1

HP∆P

∆x1,(4.2.4)

where ∆ is the determinant of the structure matrix representing the signal flow graph.

Consequently, the solution of the system of equations consists of determining the deter-

minant of the whole matrix, and for each path the path gain and the determinant of the

modified network matrix after removing the vertices belonging to this path. In the case

of multiple inputs y1, y2, ..., yk, (4.2.4) can be applied for each input separately and the

resulting expression for an output node xjis then of the form

xj=

i=1

Tji yi,(4.2.5)

where

Tji =X

P∈P athji

HP∆P

∆,(4.2.6)

is the graph transmittance from the input yito the vertex xj.

Throughout this thesis the transfer scattering matrix and multiport connection methods

described in subsections 4.1.3 and 4.1.4 can be used as validation methods for the sig-

nal propagation paths. The transfer scattering matrix is preferred when the problem is

characterized by a simple topology. However, the multiport connection method is able to

analyze large interconnect circuits with complex topologies.

The expression of the transfer function given by (4.2.4) seems to complex if applied to large

circuits with a big number of paths. In order to compute the transfer function between

any two pair of vertices in a SFG all directed simple paths connecting these vertices have

to be determined. The cycle gains of the subgraphs associated to these paths can be

easily computed from the determinants of corresponding submatrices. The determination

of all paths still represent a hard problem in graph theory. In the next section efficient

algorithms are used to identify only the weighted simple paths, and therefore to compute

an approximation of the transfer function.

Chapter 5

Approach to Noise Path Tracing

The Mason’s formula described in Section 4.2.3 for the analysis of an electrical network by

its associating signal flow graph requires the determination of all signal paths connecting

the input and output vertices, called also the source and target vertices respectively. As

the computation of all paths in a graph is complex problem, shortest paths algorithms

can be introduced to identify only a few weighted signal paths which give a good approx-

imation to the total transfer function. In such a way the noise flow can be determined

efficiently.

5.1 Shortest Paths Algorithms

Shortest paths algorithms are used in operation research and computer science to search

for an optimal path in various applications [59]. The variant of algorithms used here is

limited to the determination of simple shortest paths in directed graphs, i.e. without

cycles of repeated vertices. The objective is to compute, for each vertex v′reachable from

the source vertex s′, the weight of a minimum-weight path from s′to v′. The weight of a

path is the sum of the weights of its edges.

There exist a variety of simple shortest paths algorithms for specific applications. The

first category allows the identification of the shortest paths from a single specified source

vertex to another specified vertex, or to all vertices, in the graph. The second category

deals with the determination of all shortest paths between any pair of vertices. The third

category is the k-shortest paths algorithms which focus on the computation of many

shortest paths connecting a given source-destination pair of vertices in the graph with

minimum total lengths [60, 61, 62, 63]. In the next sections two examples of the most

efficient algorithms belonging to the first and third categories are described. The first one

is the single source shortest path algorithm of Dijkstra. The second one is the k-shortest

paths algorithm of Hershberger et al. [63].

52 CHAPTER 5. APPROACH TO NOISE PATH TRACING

5.1.1 Single Source Shortest Path Algorithms

Different algorithms have been proposed in literature to solve shortest path problems

in directed graphs. Most of these types are developed to deal with particular graphs

depending on their structure and size. In this section single shortest path algorithm of

Dijkstra is described. It is mainly used to solve routing problems for different applications

[59].

Given a directed graph G′= (V′, E′) with vertex set V′and edge set E′. Each edge

e′= (u′, v′)∈E′has a positive real edge weight or cost c(u′, v′)≥0. The number of

vertices and edges in the graph G′are denoted nand mrespectively. A source vertex

s′and a destination vertex t′, assumed to be different from s′, are specified, for which

the shortest path is to be defined. The shortest path between two vertices v′

1and v′

qin

G′is defined as the path P={v′

1, v′

2, ..., v′

q}such that the sum over all c(v′

i, v′

i+1), for

i= 1, ..., q −1, is minimum. Its length is denoted by d(v′

1, v′

q).

Dijkstra’s algorithm is based on labeling the vertices of the given graph. That means each

vertex is associated a positive value dwhich represents its distance from the source s′.

At each step of the algorithm some vertices have permanent labels and others temporary

labels. The permanent labels indicate the shortest distance from the source s′to their

associated vertices. The algorithm starts with an initialization step by assigning a per-

manent label 0 to the source vertex s′, and a temporary label ∞, i.e. infinite distance, to

the remaining vertices. In each iteration the adjacent vertices of the permanent label are

updated according to the following rules:

1. Every vertex v′that is not yet permanently labeled gets a new temporary label

whose value is given by

min[d(s′, v′),(d(s′, u′) + c(u′, v′))],

where, u′is the last vertex permanently labeled, in the previous iteration, and

c(u′, v′) is the weight of the edge constructed from the vertices u′and v′. If u′and

v′are not joined by an edge, then c(u′, v′) = ∞.

2. The smallest value among all the temporary labels is found, and this becomes the

permanent label of the corresponding vertex. In the case of many candidate labels,

one of them is selected as permanent label.

The first vertex to be permanently labeled is at a distance of zero from s′. The second

vertex to get a permanent label, from the set of remaining vertices, is the vertex closest

to s′. The next vertex to be permanently labeled is the second closest vertex to s′. The

permanent label of each vertex is the shortest distance of that vertex from the source s′.

This procedure is repeated until the destination vertex t′gets a permanent label. As an

illustration of Dijkstra’s algorithm the digraph in Figure 5.1.1 is considered.

The labeling procedure is applied to the directed graph in Figure 5.1.1 to compute the

shortest distance from the source vertex A to the vertex F. Table 5.1.1 shows the algorithm

steps needed to get the solution.

5.1. SHORTEST PATHS ALGORITHMS 53

Figure 5.1.1: A directed graph example to illustrate Dijkstra’s single

shortest path algorithm

The first line in this table represents the initialization step, where only the source vertex is

reached. The vertex that gets permanent label at each step is indicated with a superscript

(∗) at its label. The distances to the remaining vertices are recomputed using the vertex

permanently labeled.

The shortest path can be determined by recording the vertices from which each vertex

was labeled permanently. If the shortest path from the starting vertex s′to each vertex is

determined, then these paths may be represented by a rooted tree at s′, called shortest-

distance arborescence.

A B C D E F G

0∞ ∞ ∞ ∞ ∞ ∞

0∗20 ∞50 ∞ ∞ ∞

0 20∗∞50 ∞ ∞ ∞

0 20 70 30∗∞ ∞ 60

0 20 50∗30 50 ∞60

0 20 50 30 50∗60 60

0 20 50 30 50 60 60∗

0 20 50 30 50 60∗60

0 20 50 30 50 60 60

Table 5.1.1: Steps for the determination of a shortest path by Dijkstra’s algorithm

Figure 5.1.2: Shortest paths arborescence for the graph in Figure 5.1.1

There exist a variety of implementations of Dijkstra’s algorithm which uses different data

54 CHAPTER 5. APPROACH TO NOISE PATH TRACING

structures. The asymptotic time complexity of Dijkstra’s algorithm depends on the choice

of the priority queue used for storing and handling the edges and vertices. Especially the

time required to perform some operations like insertion and deletion for different heaps

dominates this complexity. For general graphs, the use of Fibonacci heaps still provide

the best theoretical worst-case time of O(m+nlog n) using an adjacency list to represent

the graph data structure. For sparse graphs, binary heaps are more efficient and result in

the same asymptotic time complexity. A pseudo-code describing this algorithm is given

bellow.

Algorithm 5.1.1 Dijkstra’s Algorithm

1: Input: Graph G′= (V′, E′, c), c(u′, v′)>0, start and target nodes (s′, t′)

2: Initialization: d(s′) = 0, d(v′) = ∞for each v′6=s′,Q={s′}

3: repeat:

4: Select a node h′from Qwith minimum d(h′)

5: for each adjacent vertex v′of h′, with v′not yet visited do

6: if d(h′) + c(h′, v′)< d(v′)then

7: d(v′) = d(h′) + c(h′, v′)

8: Q=Q∪{v′}

9: end if

10: end for

11: Q=Q\{h′}

12: until Q=∅

5.1.2 K-Shortest Simple Paths Algorithms

In many applications a number of simple shortest paths is to be computed. That is, not

only the shortest path is to be determined, but also the second shortest, the third shortest,

and so up to the k-th shortest path. The paths are determined in increasing order of their

lengths, i.e. distance from the source. A comparative study of the algorithms that solve

the k-shortest path problems is provided in literature [61]. The recent algorithm used in

this thesis is the most efficient one developed by Hershberger et al. [63].

Given a directed graph G′= (V′, E′) with vertex set V′and edge set E′. Each edge

e′∈E′has a real positive weight c(e′)>0. The sizes of the sets V′and E′are mand

nrespectively. A start vertex s′and a target vertex t′are specified for which ksimple

shortest paths have to be determined. The shortest path between the vertices s′and t′is

denoted here by path(s′, t′).

The k-shortest path problem consists of the determination of a set P(k) = {P1, ..., Pk}

of simple paths, assuming at least one exists, between the vertices s′and t′when the

objective function, i.e. the weight, of the shortest path problem is considered and in such

a way that

d(Pk)≤d(P),for any P ∈ Paths′t′−P(k−1),

where Paths′t′is the set of all paths between s′and t′, and P(0) is the empty set.

5.1. SHORTEST PATHS ALGORITHMS 55

The algorithm in [63] is based on the application of single shortest path algorithms in sub-

graphs and an efficient best replacement path algorithm. The paths already determined

are stored in a rooted tree called the path branching structure. The nodes and branches

of this branching structure are associated equivalence classes which define the subgraphs

in which the next candidate shortest paths should be determined.

For a set P(i) = {P1,P2, ..., Pi}of first igenerated shortest paths a set Riof candidate

paths connecting s′to t′is defined. The set Ricontains the remaining k−icandidate

shortest paths. This set is partitioned into equivalence classes in order to find the next

shortest path in Riefficiently. The first ishortest paths are encoded in a branching

structure, denoted Ti, that shows how these deviate from each other. The equivalence

classes are related to this branching structure.

The branching structure Tiis constructed in a recursive way from the parameters (s′,P(i)),

where s′is the fixed source and P(i) = {P1,P2, ..., Pi}is the set of the first ishortest

paths. Tiis initialized to the root node s′. At each step the longest prefix path of the

paths in P(i) is considered. If (s′, a′, b′, ..., u′) is the longest subpath that is a common

prefix of all the paths in P(i), then the branching structure Tiis expanded by adding a

node labeled u′, which is the child of s′, and creating the branch (s′, u′).

The set of paths {P1,P2, ..., Pi}is called the path bundle of the branch (s′, u′) and denoted

by B(s′, u′). This path bundle B(s′, u′) will be partitioned into sets S1,S2, ..., Snsuch that

all paths in a given set Sj,j= 1, ..., n, follow the same edge after u′, and paths in different

sets follow distinct edges. This procedure is illustrated in Figure 5.1.3.

B(s′, u′)

s′u′

v′

t′

Figure 5.1.3: Path bundle of a branch (s’,u’)

The construction of the branching structure Tiis made by recursive calls (u′,Sj), for

j= 1, ..., n, until the path set Sjcontains only a single path P, i.e. |Sj|= 1. This path

is represented in the branching structure by a leaf node labeled tP.

For any given node u′in the branching structure Tia prefix path prefixPath(u′) is

defined. It is formed from the concatenation of all the branches from s′to u′. Therefore

the shortest path Pfor a leaf node tPis equal to prefixPath(tP). Each branch (u′, v′)

in the branching structure Tihas a path bundle B(u′, v′) associated with it, and which

consists of all the paths that terminate at leaf descendants of v′. For any branch (u′, v′)

56 CHAPTER 5. APPROACH TO NOISE PATH TRACING

in Tithere is a path in G′associated with it, and denoted by branchPath(u′, v′). This is

the path connecting the vertices u′and v′and which is shared by all the paths in B(u′, v′).

The first edge of branchPath(u′, v′) is called the lead edge of the path, denoted L(u′, v′).

The equivalence classes of candidate paths are associated with the nodes and branches

of Ti. Each non-leaf node u′∈ Tiis associated an equivalence class C(u′). If the node u′

has nchildren in Tilabeled v′

1, v′

2, ..., v′

n, then an equivalence class C(u′, v′

j) is associated

with each branch out of u′. The class C(u′) consists of the paths that overlap with each

prefixPath(v′

j) up to u′, and branch off at u′using an other edge that is distinct from

any of the lead edges L(u′, v′

j), for j= 1,2, ..., n. The class C(u′, v′

j) consists of the

candidate paths that coincide with the paths in prefixPath(v′

j) up to and including the

lead edge L(u′, v′

j), but branch off before v′

j. That is, the paths of C(u′, v′

j) diverges from

prefixPath(v′

j) between u′and v′

j. The equivalence partition associated with the path

branching structure Tiis the collection of these sets over all branches and non-leaf nodes

of Ti. The notion of node and branch equivalence classes is illustrated in Figure 5.1.4.

s′

u′

v′

1v′

2v′

(a)

s′

u′

v′

1v′

2v′

b′

(b)

Figure 5.1.4: Equivalence classes: (a) node equivalence class, (b) branch equivalence classes

A graph example and the corresponding branching structure are shown in Figure 5.1.5.

In this figure the node ahas three equivalence classes associated with it and its children.

The first class C(a) consists of the paths that overlap with P1, ..., P5up to a, then branch

off at a. The second class C(a, c) contains those paths that have the same subpath from s′

to awith P4,P5, and diverge somewhere strictly between aand c. The third class C(a, b)

includes the paths that share the subpath from s′to awith P1,P2, and P3until a, then

leave before b.

The problem of searching for many shortest paths between two vertices s′and t′can

now be reduced to handling of the equivalence classes. There is an equivalence class for

each non-leaf node and branch of the tree. To store the lengths of the shortest paths

from each of the equivalence classes, a heap is used. For each class, one determines the

minimum element, and then inserts it into the heap. The next shortest path corresponds

to the smallest entry of the heap. This path is then chosen and deleted from the heap.

Accordingly the path branching structure and the associated equivalence class partition

are modified.

The node and branch equivalence classes are determined after a shortest path compu-

tation. There are two situations that may occur. In the first one the current shortest

5.1. SHORTEST PATHS ALGORITHMS 57

s′

t′

fP1

P2P3

(1,2,3,4,5)

(4,5) (1,2,3)

(1) (2) (3)

(4) (5)

tP1tP2tP3

tP4tP5

Figure 5.1.5: Five shortest paths and their path branching structure according to [63]

path Pcomes from a node u′in the branching structure. That is, this node is already

contained in Ti. Here the node class C(u′) is modified and a new branch equivalence class

C(u′, tP) is created. In the second situation the current shortest path Pcomes from a

branch (u′, v′) in the branching structure. That means, from some node w′between u′

and v′, and which is not yet inserted in branching structure. Here, and as in the first

case, the classes C(w′) and C(w′, tP) corresponding to the new node w′are computed. In

addition, two equivalence classes C(u′, w′) and C(w′, v′) associated to the branches (u′, w′)

and (w′, v′) are determined. This procedure involves refining one equivalence class into at

most four classes. Both situations are shown in Figure 5.1.6.

Each of the four equivalence classes is associated a subgraph H′of G′, in which the shortest

path is determined. To solve the shortest path in an equivalence class C(u′)Dijkstra’s

algorithm is applied to compute the shortest suffix path from u′to t′in a subgraph H′

of G′obtained by deleting from G′all the vertices in prefixPath(u′) except u′, plus all

the lead edges that leave from u′. This path is then appended to prefixPath(u′). This

procedure is represented in Figure 5.1.6(a).

To solve the shortest path in a branch’s equivalence class C(u′, v′) the lead edge of

L(u′, v′) = (u′, b′) is considered. The paths in this class follow prefixPath(v′) up through

the lead edge b′, then branch off before v′. Thus the problem reduces to finding the short-

est suffix starting at b′, ending at t′, which is vertex-disjoint from prefixPath(u′) and

deviates from branchPath(u′, v′) before v′. This path is determined using a replacement

path algorithm, described later in this section, in a subgraph H′of G′, defined by deleting

from G′all the vertices on prefixPath(u′), including u′. Figure 5.1.6(b), 5.1.6(c), and

5.1.6(d) show this situation.

The overall complexity of the k-shortest paths algorithm is dominated by O(k) invocations

of the replacement paths subroutine. In the optimistic case, this takes O(m+nlog n)

time per invocation, which is equivalent to one Dijkstra’s call. In the pessimistic case, it

takes O(n(m+nlog n)) time per invocation. The pseudo-code of the algorithm presented

in [63] is given by Algorithm 5.1.2.

The computation of the shortest path in each branch equivalence class can be formulated

as a replacement paths problem. Given a directed graph H′= (V′, E′) with positive

edge weights, a start vertex xand a target vertex y. Consider P={v′

1, v′

2, ..., v′

m}, where

58 CHAPTER 5. APPROACH TO NOISE PATH TRACING

s′

u′

b′

(a)

s′

u′

b′

(b)

s′

u′

b′

v′

w′

(c)

s′

u′

b′

v′

w′

(d)

Figure 5.1.6: Equivalence classes associated to the nodes and branches of a branch-

ing structure: (a) node u′, (b) branch (u′, tP), (c) branch (u′, w′), (d) branch (w′, v′)

v′

1=x, and v′

m=y, the shortest path from xto yin H′. The best replacement path for

the edge (v′

i, v′

i+1), for each i∈ {1,2, ..., m −1}, is the shortest path from xto ythat does

not include (v′

i, v′

i+1).

A trivial procedure requires m−1 invocations of the single source shortest path compu-

tation in the graph H′\(v′

i, v′

i+1), and thus leads to a slower algorithm. An alternative is

the efficient replacement paths algorithm presented in [64]. This algorithm computes all

the replacement paths for each edge that belongs to the shortest path in O(m+n logn)

time. The replacement paths algorithm may fail for some directed graphs, but the failure

can be detected and switch into the trivial procedure.

Given a shortest path Pconnecting two vertices xand yfor which the best replacement

path is to be determined. For each edge e′in Pthe replacement distance d(x, y, G′\e′)

can be computed by combining two shortest path trees Xand Yconstructed from the

roots xand yrespectively. The shortest path tree Ywith root ycan be computed after

reversing the orientation of every edge in E′. These shortest path trees can be computed

in O(nlog n+m) time using Dijkstra’s algorithm and Fibonacci heaps.

5.1. SHORTEST PATHS ALGORITHMS 59

Algorithm 5.1.2 Algorithm k-Shortest Simple Paths [63]

1: Initialize the path branching structure T0to contain the source node s′, and put

path(s′, t′) in the heap. There is one equivalence class C(s′) initially, which corre-

sponds to Paths′t′.

2: repeat

3: Extract the minimum key from the heap. The key corresponds to

4: some path Pi.

5: if Pbelongs to an equivalence class C(u′) for some node u′then

6: Add a new branch (u′, tPi) to Tithat represents the suffix of Piafter

7: u′.

8: Remove from C(u′) the paths that share at least one edge with Pi

9: after u′and put all of them except Piinto the newly created

10: equivalence class C(u′, tPi).

11: else if Pibelongs to an equivalence class C(u′, v′) for some branch (u′, v′)then

12: Let w′be the vertex where Pibranches off from branchPath(u′, v′).

13: Insert a new node labeled w′, and split the branch (u′, v′) into two

14: new branches (u′, w′) and (w′, v′). Add a second branch (w, tPi) that

15: represents the suffix of Piafter w′.

16: Redistribute the paths of C(u′, v′) among the four new equivalence

17: classes C(u′, w′),C(w′, v′), C(w′, tPi), and C(w′), depending on where

18: they branch from branchPath(u′, v′) and /or Pi.

19: - Paths branching off branchPath(u′, v′) before node w′belong to

20: C(u′, w′).

21: - Paths branching off branchPath(w′, v′) after node w′belong to

22: C(w′, v′).

23: - Paths branching off Piafter node w′belong to C(w′, tPi).

24: - Paths branching off both Piand branchPath(u′, v′) at node w′

25: belong to C(w′).

26: end if

27: For each new or changed equivalence class, compute the

28: shortest path from s′to t′that belongs to the class. Insert these paths

29: into the heap.

30: until i=k

The algorithm is based on a partitioning of the vertices in V′into two sets Vxand Vy

such that x∈ Vxand y∈ Vy. These sets are easily obtained from the shortest path

tree Xby removing the edge e′

i= (v′

i, v′

i+1) in path(x, y), for which the best replacement

distance should be computed. For their determination the vertices of V′are assigned to

blocks Bi, which indicate their positions in the shortest path tree X. That is, for each

vertex u′∈ Bi,block(u′) = i. Thus for a given edge e′

i= (v′

i, v′

i+1) to be removed in

path(x, y), Vx=∪i

j=1Bj, and Vy=∪k

j=i+1Bj. Figure 5.1.7 shows a shortest path tree and

the associating blocks. As shown in Figure 5.1.7(a) the blocks of vertices are related to

their predecessor nodes on the shortest path. Figure 5.1.7(b) illustrates the replacement

paths procedure for the edge e′= (u′, v′).

60 CHAPTER 5. APPROACH TO NOISE PATH TRACING

(a)

VxVy

e′

v′

u′

(b)

Figure 5.1.7: Partitioning of vertices into blocks: (a) shortest path tree, (b) cut edges for the

edge e′= (u′, v′) [64]

The set of edges crossing the cut (Vx,Vy), denoted E′

cut, is defined based on the shortest

path tree X. That are the edges (u′, v′) that have their start vertex u′∈ Vxand their

target vertex v′∈ Vy. Any path from xto ymust include at least one edge from E′

cut. For

a given edge (u′, v′)∈E′

cut the shortest paths path(x, u′) and path(v′, y) are contained in

Vxand Vyrespectively. The corresponding distances are given by the shortest path trees

Xand Y. Thus, for each edge e′

i= (v′

i, v′

i+1) in the shortest path path(x, y) and for some

cut E′

cut = (Vx, Vy), the shortest distance is expressed by

d(x, y, G′\e′

i) = min

(u′, v′)∈E′

cut

(u′, v′)6=e′

(d(x, u′;G′\e′

i) + c(u′, v′) + d(v′, y;G′\ei)) .(5.1.1)

By evaluating (5.1.1) over all the edges e′

i= (v′

i, v′

i+1) of path(x, y) in sequence from i= 1

to n−1, the best replacement path can be obtained efficiently. It is the path with the

minimum distance over all the cut edges. For some directed graphs the replacement path

algorithm may fail. Figure 5.1.8 shows an example in which vertex v′belongs to the set

Vxthat contains y, but the shortest path path(v′, y) goes through the edge e′, and leads

to an incorrect path.

VxVy

1 1

100

e′

u′v′

Figure 5.1.8: Example of incorrect replacement path [64]

In order to detect which edges cause incorrect replacement paths, the vertices v′∈V′

are labeled according to the lowest-indexed block of the tree X, such that path(v′, y)

passes through. The smallest index ifor which path(v′, y) contains a vertex of block

Biis defined to be the minblock of v′, denoted minblock(v′). That is, minblock(v′) =

min

w′∈path(v′,y)block(w′). For any edge (u′, v′), minblock(u′) is just min(block(u′), minblock(v′)).

Figure 5.1.9 shows the definition of the terms block and minblock for a path (v′, y).

5.1. SHORTEST PATHS ALGORITHMS 61

v′

Figure 5.1.9: Notions of block and minblock: block(v′) = 4, minblock(v′) = 2 [64]

To formalize the condition for which the replacement path algorithm computes a cor-

rect path associated to a given edge e′= (u′, v′)/∈path(x, y), the quantities left(e′) =

block(u′) and right(e′) = minblock(v′) are defined. From these definitions, the set of

edges e′

ifor which (5.1.1) can be minimized satisfy left(e′)≤i < right(e′). Equation

(5.1.1) can then be written as

d(x, y, G′\e′

i) = min

(u′, v′)∈E′

cut

(u′, v′)6=e′

path(v, y)∩Vx=∅

(d(x, u′;G′\e′

i) + c(u′, v′) + d(v′, y;G′\ei)) .(5.1.2)

The pseudo-code of the replacement path algorithm described above is given by Algorithm

5.1.3.

Algorithm 5.1.3 Algorithm Replacement Path [63]

1: In the graph H′, let Xbe a shortest path tree from the source xto all the remaining

nodes, and let Ybe a shortest path tree from all the nodes to the target y. The

shortest path Pfrom xto ybelongs to both Xand Y.

2: for every edge e′

i= (v′

i, v′

i+1)∈ P do

3: Let Xi=X\e′

i. Let E′

ibe the set of all edges (a′, b′)∈E′\e′

isuch that a′

4: and b′are in different components of Xi, with a′in the same component

5: as x.

6: for every edge (a′, b′)∈E′

ido

7: let d(a′, b′) = d(x, a′) + c(a′, b′) + d(b′, y). Observe that d(x, a′)

8: and d(b′, y) can be computed in constant time from Xand Y.

9: end for

10: The replacement distance for e′

iis the minimum of d(a′, b′)

11: over all (a′, b′)∈E′

12: end for

The k-shortest paths algorithms can be used with an appropriate metric to compute the

weighted signal paths between any pair of nodes in a SFG representing an electronic

network. Their evaluation provides an approximation of the total transfer function. The

number of paths required can be determined using some given threshold value.

62 CHAPTER 5. APPROACH TO NOISE PATH TRACING

5.2 Approach to Dominant Signal Paths Analysis

The signal tracing approach presented in this section allows for the identification of

weighted propagation paths connecting a noise source and a victim pin in a PCB. Thus,

providing the ability to classify the interconnect paths into critical and less critical ones.

Instead of analyzing the transmission substructures separately, the global system is consid-

ered. Dominant propagation paths connecting two ports are characterized by the amount

of signal transmitted through them. The approach proposed to identify and evaluate

such paths is based on a combination of graph shortest paths algorithms and the transfer

function formulation in signal flow graphs. This approach is described in details in this

section.

5.2.1 Illustration of A Dominant Signal Path

A direct solution to determine the signal propagation paths with respect to induced

transient impulses within a printed circuit board is based on a separate analysis of all

interconnection structures. Thus, critical structures with higher field coupling can be

detected. For the simulation of the whole circuit, derived models are inserted into a circuit

netlist and the whole network is analyzed by applying an interference source model.

In this thesis dominant propagation paths are determined considering the entire system.

A dominant path is defined by a sequence of circuit nodes, or interconnects, transmitting

significant noise power from a noise source to a device pin. It is said to be critical

if the associated power transfer disturbs the function of the target device [65]. That

is, the coupling impulses are comparable with the noise margin of the digital sensitive

components. A dominant propagation path may contain galvanic paths as well as all

possible parasitic coupling paths.

The identification of dominant paths is limited to linear circuits consisting mainly of

transmission structures and passive linear components. Their evaluation is performed

by computing the physical quantities representing the signal transfer between specified

components. Particularly the wave quantities can be introduced to represent the signal

or energy transfer between the ports of these components.

To illustrate the notion of a dominant signal path the system of interconnects in Fig-

ure 5.2.1 is considered. It consists of single and parallel coupled transmission lines. The

signal path indicated by the dashed line in this figure is assumed to transmit high amount

of power from port 1 to port 2, and thus becomes dominant over the remaining paths. It

is composed of galvanic and coupling subpaths.

5.2.2 Mathematical Background of the Algorithm

This section will apply k−shortest simple paths algorithms to identify the dominant signal

paths between two ports in a linear network. The approach is developed by deriving an

approximation to the Mason’s formula given by (4.2.5). The total transfer function can

5.2. APPROACH TO DOMINANT SIGNAL PATHS ANALYSIS 63

Figure 5.2.1: Illustration of a dominant signal path [66]

be seen as a superposition of many partial transfer functions, related to the signal paths

connecting the input and output nodes in the circuit graph. Instead of computing the

transfer function using all the existing signal paths, between a noise source and a device

pin, shortest paths algorithms are applied to identify only the weighted terms of the

transfer function that characterize some directed simple paths between the corresponding

nodes. In Figure 5.2.2 the concept of weighted signal propagation paths between two

nodes in a signal flow graph is illustrated by means of the interconnected transmission

structures of Figure 5.2.1.

Figure 5.2.2: Signal transfer between two ports

The k-shortest simple paths algorithm described in Section 5.1.2 is applied to extract

the required number of paths that are dominant. For validation purposes the number

of signal paths which deliver a good approximation to the transfer function should be

extracted. This algorithm is applied to signal flow graphs with additive metric, or weights,

derived from the scattering parameters of the interconnection structures and their linear

termination loads.

For a path Pu′,v′relating two nodes u′and v′in a directed graph without cycles and

passing through a sequence of nodes u′

1, u′

2,...,u′

n, the transfer function associated to

this path, also called direct path gain, is computed from the scattering parameters of the

edges connecting these nodes by

HPu′,v′=su′u′

1.su′

1u′

2. . . su′

nv′.(5.2.1)

64 CHAPTER 5. APPROACH TO NOISE PATH TRACING

Figure 5.2.3 shows different directed simple paths connecting the vertices u′and v′in a

graph. The magnitudes of the transfer functions HPu′,v′associated to the paths are the

main criteria considered to determine the weighted ones.

u′u′

1u′

2u′

nv′

su′,u′

Figure 5.2.3: Directed simple paths between two vertices

The problem of computing dominant paths in a PCB is formulated as identifying some

shortest paths in a representing SFG. For its construction a mapping of scattering pa-

rameters onto additive quantities is required. A logarithmic metric allowing the addition

of the edge weights belonging to a direct path is defined. It is given by

c(u′, v′) = log 1

ksu′v′k.(5.2.2)

The value of c(u′, v′) is always positive, except if su′v′equals zero, which does not occur

in high frequencies. The use of such a positive metric is a condition to apply the most

efficient Dijkstra’s algorithm. Figure 5.2.4 shows the curve representing the proposed

metric derived from the scattering parameters having a magnitude in the interval ]0,1].

||su′v′||−1

c(u′, v′)

0 5 10 15 20 25 30 35 40 45 50

0.5

1.5

2.5

3.5

Figure 5.2.4: The function representing the edge metric in terms of scattering parameters

The algorithm to extract the dominant propagation paths starts with an initialization step

where the start node (noise source), destination node (chip port), and the first shortest

path is computed. In this thesis the number kof paths required to compute the transfer

function is not specified, but determined automatically by the algorithm using a threshold

5.2. APPROACH TO DOMINANT SIGNAL PATHS ANALYSIS 65

approach [66]. In other words, the ratio of the transmission coefficients associated to two

successive signal paths is compared with a given threshold Th. In the next step of the

algorithm the second dominant path is extracted. The ratio of the transmission coefficient

magnitudes associated to both paths is evaluated and compared with the threshold Th.

If this ratio is smaller than the threshold Th, the algorithm stops else the next shortest

path is extracted. This procedure is repeated for each new extracted path Pi+1 and its

predecessor Pi, i = 1,2,... until a ratio of transmission coefficients is reached, which

forces the algorithm to stop. Thus the number of signal paths identified corresponds to

the number krequired. The pseudo-code of the k-shortest path algorithm extended with

a threshold approach is given as

Algorithm 5.2.1 Algorithm Transmission Coefficient Threshold

1: Initialization:

2: - Set the start and target nodes u′and v′

3: -i= 1

4: - Extract the first path P1

5: - Set a threshold Th(e.g. 10%)

6: repeat

7: i=i+ 1

8: Extract the i-th path Piusing the k-shortest path algorithm

9: Compute Q=ksu′v′(Pi)k

ksu′v′(Pi−1)k

10: until Q <=Th

Equation (4.2.4) which requires the extraction of all paths connecting two nodes u′and

v′in a graph is modified. To compute the scattering parameter coefficients su′,v′between

both nodes, a limited number kof weighted signal paths is considered. Its new expression

is given as

sv′,u′≃

i=k

i=1,Pi∈Path(v′,u′)

HPidetPi

detSF G ,(5.2.3)

where HPiis the transfer function associated to the path Piand which can be computed

by the use of (4.2.3), detSF G is the determinant of the structure matrix associated to the

scattering parameters signal flow graph, and detPiis the determinant of the one associated

to the subgraph without the nodes belonging to the path Pi. That is, the matrix after

removing the rows and columns corresponding to the individual paths connecting the

input and output nodes u′and v′.

This approach represents a combined method to compute the power wave scattering pa-

rameters, since the transfer functions HPiassociated to the dominant paths extracted

have to be multiplied by the associated cycle transfer functions computed from a matrix

formulation. The transmission coefficients are formulated by identifying of dominant sig-

nal propagation paths relating a start and a target port of interest in an PCB. Using the

transmission coefficient as transfer function, (5.2.3) can be written as

su′,v′≃su′,v′(P1) + su′,v′(P2) + ...+su′,v′(Pk),(5.2.4)

66 CHAPTER 5. APPROACH TO NOISE PATH TRACING

where

su′,v′(Pi) = HPidetPi

detSF G ,i=1,2,. . . ,k.

Here, HPiis the value of the gain associated to the path Pi, and which is given by (5.2.3).

The principle of determining the dominant noise paths is illustrated in Figure 5.2.5.

Path

Interference Source 1st Dominant Noise

2nd Dominant Noise

kth Dominant Noise

Victim Pin

Figure 5.2.5: Principle of signal path extraction [67]

The reflection coefficients may also be obtained considering the dominant propagation

paths. Their use is however useful only when a complete simulation of the system is

required. If the nodes representing the reflected and the incident waves at the noise

source and the target load ports, in a PCB, are denoted by urand vi, the approximated

two-port scattering matrix relating these ports is given as

S≃





i=1

su′ur(Pi)

i=1

su′v′(Pi)

i=1

sviur(Pi)

i=1

sviv′(Pi)







,(5.2.5)

where kis the number of the paths giving a good approximation to the transmission

coefficients, and k1, and k2are the numbers of the paths giving a good approximation

to the reflection coefficients at the source and target ports respectively. For symmetrical

networks, the off-diagonal elements of (5.2.5) are equal.

In the case where multiple noise sources exist, i.e. several input nodes in the signal flow

graph, (4.2.6) can also be approximated using the notion of dominant signal paths. Each

noise source is analyzed separately, then the results are superimposed.

5.2.3 Reciprocity of Dominant Signal Paths

In this subsection the reciprocity of dominant signal propagation paths is investigated.

Up to now, only signal paths transmitting power from a noise source to a target load, also

5.2. APPROACH TO DOMINANT SIGNAL PATHS ANALYSIS 67

called forward paths, are considered. To demonstrate the reciprocity property of signal

paths for linear passive networks the noise source is applied at the target port and the

load is placed at the start port. In other words the start and target nodes in the circuit

are swapped. In the corresponding signal flow graph this is equivalent to considering

the nodes associated to the incident and transmitted waves at the target and start ports

respectively.

Due to the reciprocity of passive linear networks the matrices characterizing the individual

interconnect and discrete elements are symmetric. As a result the signal propagation paths

become also reciproc. Applying the k-shortest simple paths algorithm to the signal flow

graph with swapped start and target nodes delivers reversal directed paths, called here

backward paths, having same weights. These paths travel the same ports of the network

as the corresponding forward paths. That means the same nodes in the circuit. Using the

reciprocity property has the advantage to reduce the computation time when computing

the scattering matrix of the entire system. That’s, only the forward paths between every

pair of vertices should be considered [66]. Figure 5.2.6 shows a forward and its associating

backward signal path between two specified ports.

Figure 5.2.6: Illustration of the reciprocity of signal propagation paths for

passive linear networks

5.2.4 Workflow of the Dominant Path Approach

A conventional approach to determine the distribution of transient noise within a printed

circuit board consisting of complex transmission structures is based on the partitioning

of the global system into simple interconnect structures and the simulation of all relevant

structures including possible parasitic couplings using numerical methods. The simulation

data can be provided in form of matrices or equivalent electrical macromodels. These data

will be placed into the circuit matrix which can be solved using e.g. the nodal analysis

technique.

Such an approach provides only the system response at the circuit nodes and branches,

but no information on signal propagation paths. However the technique presented in this

thesis allows the identification of dominant signal paths relating two specified ports in the

circuit. The input and output ports correspond to the interference source and the target

68 CHAPTER 5. APPROACH TO NOISE PATH TRACING

load respectively. The work-flow of the proposed dominant path approach is depicted in

Figure 5.2.7.

PCB Partitioning

Substructures

Characterization

Circuit Generation

Dominant Signal

Paths Analysis

Generic Structures

Scattering Parameters

Signal Flow Graph

Dominant Paths

Identification

Dominant Paths

Evaluation

Circuit Matrix

Figure 5.2.7: Path tracing analysis flow

The approach starts with partitioning of complex structures on the PCB into fundamental

ones. In the nest step, the substructures are characterized in the frequency domain by

their scattering matrices. Then, at each frequency point both the circuit signal flow graph

and matrix are generated. The SFG is constructed by connecting the subgraphs of the

structures in the circuit. Each port of the substructures is represented by two nodes

associated to the transmitted and reflected waves. The edges are associated the weights

defined by (5.2.2). By means of shortest paths algorithms the dominant propagation paths

relating an impulse source and a destination target device pin can be extracted in the

circuit SFG. These paths are then evaluated in terms of transmission coefficients using

the circuit matrix formulation according to (5.2.3). The dominant signal paths may be

extracted at all frequency points in the interval of the analysis. Alternatively, the coupling

frequencies are determined in a preprocessing step and the signal paths are extracted at

the resonant ones.

5.2.5 Analysis Example

The proposed approach to dominant paths analysis is applied to a circuit consisting of in-

terconnects of parallel transmission lines and passive discrete components. The schematic

of this circuit is shown in Figure 5.2.8. It consists of six blocks of coupled parallel mi-

crostrip line systems. The microstrips are assumed to be lossless. The microstrips of width

200 µm, thickness 30 µm are placed on a dielectric substrate of a permittivity εr=4.5 which

5.2. APPROACH TO DOMINANT SIGNAL PATHS ANALYSIS 69

is placed on a conducting metal ground plane. The space between the microstrip lines is

300 µm. The blocks of two and three coupled traces are indicated by MTL 2 and MTL 1,

respectively. The length of MTL 2 is 2 cm, whereas MTL 1 have a length of 3 cm. The

lines which are not connected to each other are matched.

The three coupled microstrips are characterized by the per unit length inductance and

capacitance matrices

L=





512.71 136.11 56.26

136.11 509.61 136.11

56.26 136.11 512.71







m,C=





68.83 −11.62 −1.01

−11.62 71.07 −11.62

−1.01 −11.62 68.83







and the inductance and capacitance matrices per unit length of the two coupled lines are

L= 513.07 137.21

137.21 513.07 !nH

m,C= 68.81 −11.81

−11.81 68.81 !pF

A resistance R2= 75 Ω and a capacitance C1= 5 pF are connected between some trans-

mission lines of the circuit. The start node s′and the target node t′correspond to the

voltage source and the load resistance R1= 75 Ω respectively [65].

(MTL1)

(MTL2)

s′

t′

1st Path

2nd Path

3rd Path

Figure 5.2.8: Example of a circuit showing the dominant crosstalk paths between

the nodes s′and t′[65]

The scattering matrices, which are useful for the algorithm, are computed from the per

unit length matrices Land C. Because of the topology of this circuit all parasitic prop-

agation paths relating the start and target nodes are due to the crosstalk between the

transmission lines. That’s, there are no conducting paths contributing to the signal trans-

fer between both nodes.

The first three dominant paths relating the noise voltage Vssource and the target load

R1are extracted. These are indicated in the schematic of Figure 5.2.8. These represent

70 CHAPTER 5. APPROACH TO NOISE PATH TRACING

the propagation ways that transmit significant noise power from the voltage source to

the load R1. The remaining signal paths are negligible, since they do not contribute to

significant change in the total response. The magnitudes of the transmission coefficient

s12 associated to these paths are depicted in Figure 5.2.9.

Frequency (GHz)

s12 Magnitude

Sum of Dominant Path 1,2,3

1st Dominant Path

2nd Dominant Path

3rd Dominant Path

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.02

0.04

0.06

0.08

0.1

0.12

0.14

(a)

Frequency (GHz)

s12 Magnitude

Multiport Connection M.

1st Dominant Path

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.02

0.04

0.06

0.08

0.1

0.12

0.14

(b)

Figure 5.2.9: Transmission coefficient s12: (a) the first three dominant signal paths,

(b) comparison of P1with the total response

Clearly all the three paths are resulting from the coupling between the transmission line

ends. All coupling phenomena between the transmission lines are taken into account.

Figure 5.2.9(a) compares the magnitudes of the transmission coefficients s12(P1), s12(P2),

and s12(P3) associated to the three paths. The first dominant signal path shows significant

transfer of power over the frequency range of 5 GHz. The second dominant path has a

transfer function which is higher than the one of the third path up to the frequency

of 4.2 GHz. The same figure compares the response from the superposition of the three

dominant paths. In Figure 5.2.9(b) the magnitude of the most dominant path is compared

with the one obtained by multiport connection method (4.1.21). A good convergence is

achieved up to the frequency of 3.5 GHz. That means, the consideration of this path alone

may be enough to model the transmission of power between the voltage source and the

target load up to 3.5 GHz.

In order to compute the coupling voltage impulses at the target resistance R1an equiv-

alent two-port of the circuit is synthesized. Its input and output ports correspond to

the noise source Vsand target load R1respectively. The reflection coefficients at both

ports are computed and an equivalent two-port scattering matrix of the linear circuit is

obtained. Since the focus of interest is on the propagation of noise signal between the

noise source and the target load, i.e. two different ports in the network, the propagation

paths associated to the reflection coefficients are not indicated in the circuit schematic.

Figure 5.2.10 shows the magnitude responses of the reflection coefficients at the input and

output ports.

In this figure the reflection coefficients s11 and s22 are verified with the results of the

multiport connection method over the frequency range of 5 GHz. For the coefficient s11

5.2. APPROACH TO DOMINANT SIGNAL PATHS ANALYSIS 71

identical results are obtained considering only the first two dominant paths. The curve

of the coefficient s22 is obtained considering three dominant paths. The results can be

improved by considering secondary paths. As a result a scattering matrix associated to

the dominant signal paths is derived. It is given by

S≃





r=1

s11 (Pr)s12 (P1)

s21 (P1)

r=1

s22 (Pr)







.(5.2.6)

According to (5.2.5), k= 1, k1 = 2, and k2 = 3 are the number of signal paths required

to approximate the coefficients s12,s11, and s22, and thus the total system response.

Frequency (GHz)

s11 Magnitude

Multiport Connection M.

Dominant Path App.

0 0.5 1 1.5 22.5 3 3.5 4 4.5 5

0.1

0.2

0.3

0.4

0.5

(a)

Frequency (GHz)

s22 Magnitude

Multiport Connection M.

Dominant Path App.

0 0.5 1 1.5 2 2.5 33.5 4 4.5 5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

(b)

Figure 5.2.10: Magnitude of the reflection coefficients at : (a) noise source, (b) target load

The results in terms of the voltage transfer function Vt′/Vs′are shown in Figure 5.2.11.

The magnitude and phase responses obtained from the superposition of the individual

responses of the first and second dominant signal paths are represented. An increase of

crosstalk noise is observed with increasing operation frequency.

The resulting voltage responses, in term of magnitude (Figure 5.2.11a) and phase (Figure

5.2.11b), are compared with the total responses delivered by the HSPICE circuit simulator.

The superposition of the first two dominant paths only delivers good results in terms of

scattering coefficients and voltage phasor. Consequently only the first two dominant paths

can approximate the total response of the system over the range of the frequency analyzed.

In order to study the reciprocity of the extracted dominant signal paths the transmission

coefficient s21 is also computed using the same approach. In the schematic of Figure 5.2.12

the reciprocity is shown for each individual propagation path. The flow of the power

between the voltage source and the target load is represented using forward and backward

propagation paths. It is clear that each dominant signal path Pifrom the target load to

the noise source, for i= 1,2,3, traverses the same network ports like the one from the

voltage source to the target load with the same order.

72 CHAPTER 5. APPROACH TO NOISE PATH TRACING

Frequency (GHz)

Vt′Magnitude (V)

HSPICE Simulation

Sum of paths: 1,2

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

(a)

Frequency (GHz)

Vt′Phase (◦)

HSPICE Simulation

Sum of paths: 1,2

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(b)

Figure 5.2.11: Coupling voltage impulses at the target load: (a) magnitude, (b) phase

s’

t’

Figure 5.2.12: Forward and backward dominant propagation paths between two ports in a circuit

To conclude an approach for the extraction of dominant noise propagation paths relating

two nodes in a linear circuit is presented. The dominant noise paths are extracted using

k-shortest simple paths algorithms applied to the signal flow graph constructed from the

scattering parameters of the circuit. The noise paths evaluation is performed by the

computation of the corresponding transmission coefficients. The approach is illustrated

by an interconnect circuit example.

Chapter 6

Time Domain Analysis of a

Complete Signal Path

The dominant path approach presented in Section 5.2 is a frequency domain technique

for describing the interactions between two specified ports in a linear circuit. These

interactions are expressed in terms of the power flow through the weighted signal paths

relating these ports. The corresponding voltage and current transfer functions can then

be derived using appropriate transformations. The time domain analysis of signal paths

is carried out in this chapter. The waveform of dominant noise propagation paths is

investigated considering the characteristics of the excitation impulses and some features

of the PCB.

6.1 Signal Path with a Linear Termination

Time domain signals can be represented by their frequency contents using the Fourier

analysis. Periodic signals are often described by Fourier series while non-periodic signals

are represented in the frequency domain by Fourier integral or transform.

6.1.1 Fourier Series

Every periodic signal, represented by a function f, with a period Tcan be represented in

the time domain by the Fourier series expansion

f(t) = A0

∞

n=1

(Ancos(nω0t) + Bnsin(nω0t)) ,(6.1.1)

where ω0is the fundamental angular frequency of the signal which is given by

ω0=2π

74 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

The coefficient A0, An,and Bnare known as the Fourier coefficients. These are defined

A0=2

TZt0+T

t=t0

f(t)dt, (6.1.2)

An=2

TZt0+T

t=t0

f(t)cos(nω0t)dt, (6.1.3)

Bn=2

TZt0+T

t=t0

f(t)sin(nω0t)dt, (6.1.4)

where t0can be any value of time.

Equation (6.1.1) means that a periodic signal is a summation of sinusoidal signals, referred

to the harmonics of multiple frequencies and amplitudes. The frequency of each sinusoid

in the series is an integer multiple of the fundamental frequency of the signal. The more

sinusoids included in the sum, the better the approximation.

A more practical form of (6.1.1) is the discrete Fourier series, which approximates the

signal value at a sampling point of time using a limit number Mof discrete coefficients.

It is defined by

f(tk) = A0

n=1 Ancos(2π n k

N) + Bnsin(2π n k

N),(6.1.5)

where Nis the number of sampled signal values in the period Tand tk=k∆tare the

discrete time samples. The coefficients A0, An,and Bncan be determined as for the

continous Fourier series, but by replacing the integral by a sum.

Instead of using trigonometric functions the function fcan be expressed as complex

exponential terms. The definitions of complex Fourier series and coefficients are given in

Appendix A.

The frequency spectrum of a periodic signal depends on the parameters and shape of the

signal. An important parameter which influences the spectrum of a signal is the transition

time. To show the influence of this parameter a periodic trapezoidal wave is considered.

The signals and the corresponding frequency spectra are represented in Figure 6.1.1 for

the transition times 5 ns and 10 ns.

The amplitudes of both signals in Figure 6.1.1(a) are maintained constant, namely 100 V.

In Figure 6.1.1(b) the frequency spectum is represented. The common property is that

both spectra are decreasing with the frequency. From the comparison of the curves, it is

evident that an increase of the frequency content is resulted by a significant decrease of

the signal transition time.

An other important parameter which may affect the frequency content of a signal is the

amplitude. In Figure 6.1.1(c) two periodic trapezoidal waves having the same slope and

the amplitudes 100 V and 60 V are represented. Their frequency spectra are compared

in Figure 6.1.1(d). This figure shows the same values for the common frequencies. The

difference in the spectrum comes only from the frequencies which are not shared by both

6.1. SIGNAL PATH WITH A LINEAR TERMINATION 75

Time (sec)

Vs(V)

tr/tf=10 ns

tr/tf=5 ns

0 0.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 2

×10−7

-20

100

120

(a)

Frequency (Hz)

Voltage (V)

tr/tf=10 ns

tr/tf=5 ns

0 0.5 1 1.5 22.5 3

×108

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

(b)

Time (sec)

Vs(V)

Vmax = 60 V

Vmax = 100 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-20

100

120

(c)

Frequency (Hz)

Voltage (V)

Vs = 60 V

Vs=100 V

0 0.5 1 1.5 2 2.5 3

×108

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

(d)

Figure 6.1.1: Frequency spectrum for different transition times and amplitudes for

a trapezoidal wave

signals simultaneously. It is obvious that both spectra have no important frequency

components above 200 MHz. Therfore the analysis of the dominant signal paths can be

limited to the frequency range of the excitation impulses.

The transient analysis of the linear circuit in Figure 5.2.8 is carried out considering the

excitation signals represented in Figure 6.1.1(a) and 6.1.1(c). The transition time of a

trapezoidal can model approximately the slope of an ESD signal. The scattering parame-

ter matrices computed in Section 5.2.5 are inserted in a HSPICE circuit netlist containing

the impulse voltage sources and the transmission lines terminations. The transient anal-

ysis of this netlist is then performed to compute the coupling noise impulses at the target

load R1.

Figure 6.1.2 presents the time domain simulation results for the input signals in Fig-

ure 6.1.1. The Figure 6.1.2(a) shows the coupling transient impulses for two trapezoidal

input waves with 5 ns and 10 ns transition times. As shown, a significant coupling can be

observed for the wave with a transition time of 5 ns. Figure 6.1.2(b) shows the coupling

76 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

impulses for two trapezoidal input excitations with the same slope, but different ampli-

tudes of the input voltage. For both voltage amplitudes similar peaks of the coupling

impulses are obtained. As a result, the frequency content, or the signal transition time,

of the excitation impulses is the parameter which affects essentially their propagation at

the PCB-level.

Time (sec)

Vt′(V)

tr/tf=10 ns

tr/tf=5 ns

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

(a)

Time (sec)

Vt′(V)

Vmax = 60 V

Vmax = 100 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

(b)

Figure 6.1.2: Coupling voltage impulses at the target resistance R1of the circuit in Figure 5.2.8

for various parameters of a trapezoidal excitation signal: (a) different signal transition times, (b)

different amplitudes

6.1.2 Fourier Transformation

The Fourier transformation converts signals from the time domain to the frequency do-

main. The spectrum of a signal represented by a function fis defined by

F(ω) = Z+∞

∞

f(t)e−jωt dt. (6.1.6)

A given signal occupies a frequency spectrum. The Inverse Fourier Transformation (IFT)

is given by

f(t) = 1

2πZ+∞

−∞

F(ω)ejωt dω. (6.1.7)

In digital systems the signal f(t) and its spectrum F(ω), respectively, are sampled at

discrete time and frequency points. The Discrete Fourier Transformation (DFT) is defined

F(n) =

N−1

k=0

f(k)e−j2πk n

N, n = 0,1,...,N −1 (6.1.8)

where F(n) is the nth coefficient of the DFT, and f(k) denotes the kth sample of the

time signal which consists of a number Nof samples. The inverse operation (IDFT) is

defined by

6.1. SIGNAL PATH WITH A LINEAR TERMINATION 77

f(k) = 1

N−1

n=0

F(n)ej2π k n

N, k = 0,1,...,N −1.(6.1.9)

These expressions depend on the sampling period ∆tof the signal and the number of time

samples N. The frequency spectrum is choosen at equally spaced frequencies

n∆f=n

N∆t, n = 0,±1,±2,..., ±N

6.1.3 Simulation Example

A trivial time domain analysis method of linear circuits can be formulated by solving

the transfer function in the frequency domain and converting back into time domain

using Inverse Fourier Transformation (IFT). Then the response of the circuit at any time

can be determined by convolving the impulse response with an input waveform in every

iteration. The computational effort required with this type of methods is proportional to

the square of the number of time points in simulation, because the convolution operation

has to be extended over the entire past history. This makes the method computationally

inefficient and limits its usability. Alternatively the product of the transfer function with

the frequency spectrum of the input waveform can be determined. Time domain response

is then obtained directly using IFT.

The transient analysis of the circuit in Figure 5.2.8is performed using the two-port scat-

tering matix generated by the dominant paths approach. The transfer function relating

the target resistance to the voltage source is determined. The time domain response is

obtained using the Inverse Fast Fourier Transformation (IFFT) approach. Figure 6.1.3

presents the coupling voltage impulses Vt′for a trapezoidal excitation signal with an

amplitude of 100 V, a width of 50 ns, and a rise and fall times of 5 ns.

Time (sec)

Vt′(V)

IFFT

HSPICE Simulation

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.2

-0.1

0.1

0.2

0.3

Figure 6.1.3: Time domain response of the dominant

paths using the IFFT approach

The trapezoidal wave is synthesized using 40 harmonics of its fundamental frequency

10 MHz. For the validation the curve representing the conventional HSPICE transient

78 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

simulation is also represented in the same figure. Both curves are very close to each other.

The accuracy of the time domain analysis depends on the characterization of the linear

part of the circuit, i.e. the number of dominant signal paths extracted in the frequency

domain, and the accurate synthesis of the harmonic signal applied to the system. More

accuracy can be obtained by increasing the numbers of dominant signal paths considered

and the harmonics in the input signal.

In order to compute the coupling voltage impulses associated to each of the three dominant

paths in the schematic of Figure 5.2.8, time domain analysis of each of these paths is

performed. Figure 6.1.4 shows the results in terms of coupling voltages. Figure 6.1.4(a)

represents also the resulting curve obtained by superimposing all the three paths. The

zoomed region around the first impulse is shown in Figure 6.1.4(b). It is clear that the

amplitude of first dominant path P1is very close to the one obtained by the superposition

of all the three paths. Therefore the coupling voltages from the second and third paths,

and their impact on the target device, can be neglected.

Time (sec)

Vt′(V)

Paths 1+2+3

Path 1

Path 2

Path 3

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

(a)

Time (sec)

Vt′(V)

Paths 1+2+3

Path 1

Path 2

Path 3

00.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−8

-0.1

-0.05

0.05

0.1

0.15

(b)

Figure 6.1.4: Time domain responses of the three dominant propagation paths indicated in the

schematic in Figure 5.2.8

6.2 Signal Path with a Nonlinear Termination

Digital integrated circuit devices which appear onto the signal paths as terminations are

characterized by nonlinear models. These models are described in the time domain. In this

section some hybrid methods are used to simulate the transient behaviour of individual

dominant signal paths. The Harmonic Balance technique and the HSPICE S-parameter

simulation are applied for the analysis of many examples.

6.2.1 Conventional Nonlinear Methods

Conventional nonlinear circuit simulation techniques are based on the formulation of the

system equations that can be generally written as a set of first order nonlinear differential

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 79

equations. The solution of these equations can be determined in the frequency domain or

in the time domain. The domain of analysis depends on the nature of the circuit and the

quantity to be solved.

The frequency domain steady state behavior of a microwave circuit is typically of great

interest if some quantities, like frequency, power, noise, and transfer characteristics such

as gain and impedance, should be determined. Therefore all these can only be determined

accurately for linear circuits in the steady state. Time domain analysis is however of great

importance when analyzing of nonlinear networks. Time domain methods generally use

numerical integration to calculate the instantaneous value of the output of an element

from the instantaneous value of its input. An example of such computed aided analy-

sis technique using this approach is the popular circuit simulator SPICE. The transient

analysis using this tool requires a long simulation time and integration over an excessive

number of periods.

A more important class of nonlinear methods are the hybrid methods which combine

the frequency and time domain techniques. An example of hybrid methods is the HB

technique which is a more useful method for analyzing microwave circuits. Unfortunately,

it is limited to systems having only harmonically related signal components [68, 69].

6.2.2 Harmonic Balance Technique

The Harmonic Balance is a technique for computing the steady state response of nonlinear

circuits excited by single or multiple periodic sources. It is based on the assumption

that for a given sinusoidal excitation there exists a steady state solution that can be

approximated to satisfactory accuracy by means of a finite Fourier series. Therefore the

solution can be expressed as a sum of steady state sinusoids that includes the input

frequencies in addition to any significant harmonics or mixing terms. A circuit with a

single input source will require a single tone HB simulation [70]. A solution waveform is

approximated as follows:

v(t) = Re (K

k=0

Vkejk ω0t),(6.2.1)

where ω0is the fundamental radian frequency of the source, the Vk’s are the complex

Fourier coefficients that the HB analysis computes, and Kis the order of truncation. A

circuit with multiple input sources will require multitone HB simulation. In this case,

the steady state solution waveforms are approximated with a multidimensional truncated

Fourier series as follows:

v(t) = Re (K1

k1=0

k2=0 ···

kn=0

Vk1,k2,...,knej(k1ω1+k2ω2+...+knωn)t),(6.2.2)

where nis the number of tones, or sources, ω1. . . ωnare the fundamental radian frequencies

of each source, and K1. . . Knare the number of harmonics for each tone.

Harmonic Balance technique divides a nonlinear system into a strictly linear and a strictly

nonlinear network. In Figure 6.2.1 the separation of an electrical network into linear and

80 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

nonlinear parts is shown. The linear part in this figure is connected with Ksource

generators and to the nonlinear part through an interface of Mports.

Linear Nonlinear

Network

I1,h

IM,h

V1,h

VM,h

I′

1,h

I′

M,h

Figure 6.2.1: Hybrid analysis of circuits with nonlinear elements

The linear network is described in the frequency domain, e.g. through usage of admittance

matrix Y, and the nonlinear network is described in the time domain. The basic approach

used to solve a system of nonlinear circuit equations is first to formulate an error function

and then to perform a minimization by the use of an algorithms such as the Newton

iteration scheme. A solution is found by optimizing voltages between the linear and

nonlinear parts until both frequency and time domain analyzes agree sufficiently on the

port voltages and currents. That means the port voltages and currents on all harmonics

hmust agree. This is done for a fixed set of frequency points, or harmonics, as dictated

by the input parameters.

The currents flowing from nodes into linear elements including all distributed elements

are calculated by means of straightforward frequency domain linear analysis method.

The instantaneous currents for the nonlinear network can be described by the nonlinear

functions of the voltages which describe the behaviour of the nonlinear devices. According

to Kirchhoff ’s Current Law in the frequency domain, the objective, or error function can

be derived at all nodes at the interface ports. This error function should be minimized

until acceptable convergence is achieved.

Assuming the nonlinear network has Mnodes, the instantaneous current into the linear

network at the p-th node is the sum of Nfrequency components such that

Ip=

q=1

Re(Ip,qejωqt).(6.2.3)

Similarly, the current into the nonlinear network at the p-th node is

I′

q=1

Re(I′

p,qejωqt).(6.2.4)

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 81

In (6.2.3) and (6.2.4), Ip,q and I′

p,q are the phasors of the q-th frequency components of

current flowing into the linear and nonlinear subcircuits, respectively. The instantaneous

voltage at the p-th node is given by

Vp=

q=1

Re(Vp,qejωqt),(6.2.5)

where Vp,q is the phasor of the q-th frequency component of voltage at the p-th node. At

the interface nodes Kirchhoff ’s Current Law must be satisfied, so that Ip+I′

p= 0 for

all pfrom 1 to M. Therefore, the steady state solution of the circuit can be found by

minimizing the objective function

p=1

q=1 |Ip,q +I′

p,q |2.(6.2.6)

Since the current phasors Ipand I′

pare functions of all node voltage phasors at the interface

ports, equation (6.2.6) can be written as

j=1

p=1

q=1

Θ2

j,p,q(V) =

2MN

i=1

Ψ2

i(V),(6.2.7)

where

Θ1,p,q(V) = Re(Ip,q +I′

p,q),

and

Θ2,p,q(V) = Im(Ip,q +I′

p,q).

In (6.2.7) the elements Ψi(V) are equal to the elements Θj,p,q, where the subscript i

represents a unique choice for j, p, and q.Vis a vector of real and imaginary parts of the

phasors of the node voltages at the interface ports.

The evaluation of the objective function as a function of the node voltage phasors re-

quires the calculation of the node current phasors given the node voltage phasors. Its

minimization can be achieved using a variety of iteration techniques [68, 69, 48]. A suit-

able technique to minimize such a sum of squares is the Newton’s method [48]. This

method finds the minimum of Ewith respect to Vusing the iterative procedure

i+1V=iV−J−1(iV) Ψ(iV),(6.2.8)

where the leading superscripts iare the iteration numbers, and Jis the Jacobian matrix of

Ψ. For its determination the partial derivatives of the node current phasors with respect

to the real and imaginary parts of the node voltage phasors for all interface nodes and

frequencies computed.

82 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

The element of the matrix Jin the (2j−1)-th row and k-th column at the i-th iteration

is given by

J(iV)2j−1,k =∂Ψ2j−1(iV)

∂Re(iVk),

and the element in the (2j)-th row and k-th column is

J(iV)2j,k =∂Ψ2j(iV)

∂Im(iVk).

The calculation of the Jacobian requires partial derivatives of the current phasors with

respect to the real and imaginary parts of the node voltage phasors for all nodes of the

nonlinear subcircuit and frequency components.

The diagram in Figure 6.2.2 illustrates the Newton method for the scalar case. A function

fof a single variable vis considered for which a solution for the root v∗should be found.

For this method the first step is to make an initial guess, v(0), then linearize about v(0).

Then solve for the next guess v(1), and so on. As kbecomes large, v(k)will asymptotically

approach the exact solution v∗.

f(v)

v∗v(0)

v(1)

v(2) v

f(v(0))

f(v(1))

Figure 6.2.2: Illustration of the Newton’s method [70]

The steps used by the Harmonic Balance technique are described by Algorithm 6.2.1.

For signals with small transitions a few number of frequency spectra may be sufficient for

accurate analysis. Moreover, if a circuit contains weakly nonlinear devices, an efficient and

accurate analysis will be obtained. In strongly nonlinear circuits containing waveforms

with sharp transitions, the number of Fourier coefficients needed to describe the waveform

accurately is large. In this case oversampling will help to get convergence.

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 83

Algorithm 6.2.1 Algorithm Harmonic Balance

1: Specify fundamental frequency, number of harmonics, voltage sources

2: Calculate the admittance matrix for the linear network

3: Assume an initial set of interface port currents

4: Calculate interface port voltage due to interface port current in the linear network

5: Convert interface port voltage from frequency domain to time domain

6: Using time domain port voltages, compute the time domain current in the non-

linear network

7: Convert time domain current to the frequency domain

8: Compare the linear port current to the nonlinear port current

9: if currents are almost the same at each frequency then

10: the solution is found

11: else if they are not almost the same then

12: using some optimization technique compute the new interface port current and

go to line 4

13: end if

6.2.3 Example of a Linear Load

The Harmonic Balance technique is mainly used to analyze the steady state analysis of

nonlinear circuit, but it can also be applied to solve linear circuits. As an example the

circuit in Figure 5.2.8 is again analyzed using the HB technique. In Figure 6.2.3 the

time domain response in terms of voltage impulses, obtained using the dominant path

approach combined with the HB technique, is represented. The results of the dominant

path approach combined with HB technique shows a good convergence to the curve ob-

tained by the conventional HSPICE transient simulation. The small difference between

these results may be related to the number of harmonics considered by the HB approach.

Time (sec)

Vt′(V)

Harmonic Balance Analysis

HSPICE Simulation

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.25

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

Figure 6.2.3: Time domain analysis of the circuit

in Figure 5.2.8 by the Harmonic Balance technique

84 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

6.2.4 Example of a Passive Nonlinear Device

The Harmonic Balance technique is used to perform the time domain analysis of the circuit

depicted in Figure 6.2.4, which was analyzed in [71]. It consists of two and three parallel

coupled microstrip lines, and discrete components such as resistors and capacitors. The

three coupled microstrips are the same like that of the schematic in Figure 5.2.8. All the

lines have a length of 4 cm. The lines that are not connected to the others are terminated

with 50 Ω loads. The capacitance Cand the resistance R1have the values of 2 pF and

100 Ω, respectively. In this example all the propagation paths relating the voltage source

Vsand the load impedance of R2=75 Ω consist only of the coupling paths, i.e. crosstalk.

s′

t′

1st Path

2nd Path

Figure 6.2.4: Interconnect circuit showing the noise propagation from the source Vs

to the load R2[71]

Identification and Evaluation of The Dominant Paths

In the schematic of Figure 6.2.4 the circuit nodes representing the voltage source and the

target load are indicated by s′and t′, respectively. The first two dominant propagation

paths relating the voltage source Vsand the load impedance R2are extracted. For this

circuit the extraction is performed only at the single frequency of 1 GHz. This is sufficient

because there is no change of the order of the first and second dominant paths over the

frequency range of 5 GHz. In general the paths should be extracted at each discrete fre-

quency point in the interval of analysis. The two dominant paths extracted are evaluated

by their transmission coefficients. The results are shown in Figure 6.2.5.

The magnitudes of the transmission coefficient s12 corresponding to the first two domi-

nant paths P1and P2are plotted in Figure 6.2.5(a). The remaining signal paths may be

neglected over the whole frequency range considered. Clearly the most dominant path

transmits the highest level of noise to the target load. Obviously the coupling noise as-

sociated to each of these paths increases with the frequency. This is due to the high

frequency parasitic coupling between the transmission lines. In Figure 6.2.5(b) the re-

sponse obtained from the superposition of the two paths is compared to the multiport

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 85

Frequency (GHz)

s12 Magnitude

2nd Dominant Path

1st Dominant Path

0 0.5 1 1.5 2 2.5 3 3.5 44.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

(a)

Frequency (GHz)

s12 Magnitude

Connection Matrix M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

(b)

Frequency (GHz)

s11 Magnitude

Connection Matrix M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

(c)

Frequency (GHz)

s22 Magnitude

Connection Matrix M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

(d)

Figure 6.2.5: The magnitude of the scattering parameters relating the voltage source and the

target load

connection method. The superposition of the transmission coefficients associated to these

two paths shows a good agreement with the exact values of the magnitude of s12. Since

the circuit is passive and linear, the coefficient s21 is identical to s12 and is not determined

here. The propagation paths corresponding to its computation have also the same order

and travel over the same circuit nodes in an opposite direction.

The reflection coefficients s11 and s22 are computed considering the first dominant path

identified by the algorithm. The corresponding paths are not drawn in Figure 6.2.4, since

the focus is only on the signal transmission between the voltage source and the target load.

In Figure 6.2.5(c) the magnitude of s11 is represented over a frequency range of 5 GHz.

Again the results are validated by the multiport connection method. The approximated

reflection coefficient s11(P1) associated to the most dominant path reflecting the waves

at the source is compared with the validation method [37, 45]. In Figure 6.2.5(d) the

reflection coefficient s22(P1) is compared to the exact curve computed using the multiport

connection method. For both reflection coefficients good convergence betweeen the results

of the dominant path approach and the validation method are obtained. Consequently

86 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

an equivalent two-port scattering matrix approximating the system relating the voltage

source and the target load is obtained. It is given as

S≃





s11 (P1)

r=1

s12 (Pr)

r=1

s21 (Pr)s22 (P1)







.(6.2.9)

The solution of this matrix gives the incident and reflected power waves at the network

ports. Thus, the corresponding voltage and current responses at the network terminals

can be derived. In Figure 6.2.6 the voltage transfer function is represented.

Frequency (GHz)

Vt′(V)

Dominant Path Appr.

Connection Matrix M.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

Figure 6.2.6: Voltage phasor of the transfer function

The transfer function obtained from the two-port scattering matrix determined by the

dominant path approach is validated using the one derived by the multiport connection

method. The results using the dominant signal path approach agree very well with the

ones of the validation method. A small deviation is observed for the frequencies above

4.2 GHz.

Target Linear Termination

In the following the time domain analysis is performed by combining the frequency domain

results of the dominant path approach with the Harmonic Balance technique. First a sine

voltage excitation with an amplitude of 100 V, and a frequency of 10 MHz is applied to

the circuit in Figure 6.2.4. The response to this excitation at the target resistance R2is

depicted in Figure 6.2.7(a).

In the same figure a comparison with the multiport connection method combined with

the HB technique is represented. The curves representing both approaches are very close

to each others. The response to a trapezoidal voltage impulse with an amplitude of 100 V,

a basic frequency of 10 MHz, and a transition time of 5 ns is depicted in Figure 6.2.7(b).

That is, the transient coupling impulses at the target resistance R2. To synthesize the

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 87

Time (sec)

Voltage Vt′(V)

Dominant Path App.+ HB

Multiport Connection M.+ HB

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.0008

-0.0006

-0.0004

0.0004

0.0006

0.0008

(a)

Time (sec)

Voltage Vt′(V)

Dominant Path App. + HB

Multiport Connection M. + HB

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

(b)

Figure 6.2.7: HB analysis of dominant signal paths for a: (a) sine, and (b) trapezoidal

excitation

trapezoidal voltage 40 harmonics are used. Again, the curve representing the results is

very close to that delivered by the validation method.

Target Nonlinear Termination

The target resistance R2in the schematic of Figure 6.2.4 is now replaced by a semicon-

ductor diode of type d1n4148 with the parameters (Cj0=5 pF, φ=0.6, η=0.45, Rs=0.8 Ω,

Is=7 nA, τD=6 ns). A voltage source of trapezoidal impulses is applied at the input port

of the system. The Harmonic Balance is used to compute the effect of the nonlinear diode

on the behaviour of the propagating parasitic impulses. For this reason the periodic input

voltage vis decomposed using Fourier series into a number Nof harmonics approximating

its shape. The truncated exponential Fourier series is expressed by

v(t) =

n=N

n=0

cnejn ω0t,

where ω0is the fundamental radian frequency. The complex Fourier coefficients cnare

defined by

cn=1

TZT

v(t)e−jn ω0tdt,

where Tis the period of the voltage v.

The impedance matrix Zof the linear interconnect part is computed from the two-port

scattering matrix obtained by the dominant signal path approach using (3.1.12). The

elements of its equivalent T-network are given by







z1=z11 −z12

z2=z12

z3=z22 −z12

The simplified electrical equivalent circuit relating the noise source and the target diode

is represented in Figure 6.2.8.

88 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

I1I2I′

Figure 6.2.8: Linear/nonlinear interface with one port for the HB

analysis of the circuit in Figure 6.2.4 with a diode [71]

The nonlinear analysis is performed as follows. After the phasor voltage V2is computed

for all the harmonics composing the input signal V1a conversion using an IFFT algorithm

is performed to get the time domain voltage at the interface port. The time value is used

in the nonlinear analysis to compute the time domain current I′

2from the diode equation.

The nonlinear time domain current value should be converted into the phasor current I2.

In the case where the currents at both circuit parts are matched, i.e. their difference is

smaller than a specified threshold, a solution is found. Otherwise the Newton method is

used in an iterative way until an approximate value of I2satisfying the matching procedure

is found.

The simplified network in Figure 6.2.8 is simulated in time domain for a sine wave ex-

citation with a frequency of 200 MHz, and an amplitude of 1 kV, and for a trapezoidal

excitation with rise and fall times of 2 ns, a duration of 20 ns, a period of 50 ns, and a

voltage amplitude of 1 kV. The linear part of the circuit is first characterized by the re-

flection and transmission coefficients computed over the frequency range of 1 GHz. For

this simulation the most dominant signal path is only considered to compute each of these

coefficients.

The response to the input sine wave voltage at the diode pin is depicted in Figure 6.2.9(a).

In the same figure the curve of the HB technique is compared to the one of the standard

HSPICE simulation. The response to the trapezoidal voltage wave is presented in Figure

6.2.9(b). The trapezoidal voltage is approximated using 30 harmonics of its fundamen-

tal frequency 20 MHz. The crosstalk voltage at the target diode is computed using the

dominant path approach combined with the Harmonic Balance technique. The results for

both excitations are validated by the HSPICE transient analysis. The deviation between

the responses of the HB analysis and the validation method is related to the number of

harmonics used, the optimization method, and the number of dominant paths considered

by the approach.

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 89

Time (sec)

Vt′(V)

Harmonic Balance Analysis

HSPICE Simulation

0 0.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 2

×10−8

-5

-4

-3

-2

-1

(a)

Time (sec)

Vt′(V)

Harmonic Balance Analysis

HSPICE Simulation

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

×10−7

-1.5

-1

-0.5

0.5

(b)

Figure 6.2.9: Harmonic Balance analysis of the circuit in Figure 6.2.4 loaded with a diode for a: (a) sine

excitation, and (b) trapezoidal excitation

6.2.5 Example of an Active Nonlinear Device

The simulation of a complete dominant signal path consisting of linear interconnects and

digital integrated circuit devices switched at some terminations is carried out in [66]. In

this subsection the same circuit example, shown in Figure 6.2.10, is again analyzed. It

consists of two and three parallel coupled microstrip transmission lines (of width 200 µm,

height 35 µm) separated by a space of 200 µm above a FR4 (εr= 4.2) dielectric substrate of

365 µm height. The transmission lines which are not connected to the others are matched.

The transmission line structures are characterized by their scattering parameter matrices.

A voltage source representing a transient impulse and a nominal signal source are applied

at the terminals 1 and 2 respectively.

s′

t′

Figure 6.2.10: Interconnect schematic with a disturbance source and a nominal signal source [66]

The most dominant propagation path relating the disturbance source Vsand the target

90 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

resistance R1is extracted at the frequency of 2 GHz. For this interconnect it is sufficient

to consider only the first weighted path, which transmits a significant amount of noise to

the load R1. This is, because this path remains the most dominant one over all the other

frequency points considered. This path is drawn on the circuit schematic (dashed line).

The characterization of the most dominant noise path is performed in terms of the trans-

mission coefficients, i.e. s13(P1). The results of all the scattering parameters are depicted

in Figure 6.2.11. The comparison of the magnitude of the coefficient s13(P1) with the ref-

erence results, provided by the multiport connection method, is shown in Figure 6.2.11(a).

The curves representing the dominant path approach and the validation method are iden-

tical over the whole range of the frequency analyzed. Thus, the remaining propagation

paths may be neglected.

The dominant path approach can be applied to any linear circuit with more than two

external ports connected to its noise, or signal sources. The complexity of computing the

characterization matrix associated to the dominant signal paths can be reduced consid-

ering the passivity property. Since the propagation paths are extracted over the passive

linear part of the network, the transmission coefficient s31 is identical to s13. The domi-

nant propagation path P1associated to its computation is the same like that associated

to s13. That means that the most transmitted power from the target load R1to the source

Vsflows through the same way, but in opposite direction. Moreover, there exist only one

dominant path as was the case for s13.

Using the same procedure the transmission coefficients s12 and s23, representing the trans-

fer of the power between the circuit ports 1, 2, and 3, are computed. The results in terms

of the magnitudes are depicted in Figures 6.2.11(b) and 6.2.11(c). In addition the mag-

nitude of the reflection coefficients s11,s22 and s33 are also computed considering a num-

ber of reflection paths approximating their exact responses (Figures 6.2.11(d), 6.2.11(e),

6.2.11(f)). Also identical results are obtained here considering only the dominant signal

paths reflecting the most power to each input port itself. The results in terms of phases,

not presented here, agree also very well with that of the validation method. In general

the number of the paths delivering a good approximation may be different for each of

the reflection or transmission coefficients. For lucidity and because the focus of interest

is only on the noise transmitted from the noise source Vsto the load R1, these paths are

not drawn in the circuit schematic.

The resulting three-port scattering matrix associated to the dominant signal paths is given

S≃





r=1

s11 (Pr)s12 (P1)s13 (P1)

s12 (P1)s22 (P1)s23 (P1)

s13 (P1)s23 (P1)s33 (P1)







.(6.2.10)

Consequently a three-port network described by the scattering matrix Sfrom the domi-

nant paths, relating the noise voltage source (port 1), signal generator (port 2), and the

target load (port 3), is synthesized.

In order to consider the chip port behaviour by the simulation of the whole dominant

noise propagation path the target resistance R1of the circuit in Figure 6.2.10 is replaced

6.2. SIGNAL PATH WITH A NONLINEAR TERMINATION 91

Frequency (GHz)

s13 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 22.5 3 3.5 4 4.5 5

0.0016

0.0018

0.002

0.0026

0.0028

0.003

(a)

Frequency (GHz)

s12 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.0005

0.001

0.003

0.0035

0.004

(b)

Frequency (GHz)

s23 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.997

0.9975

0.998

0.9995

1.0005

(c)

Frequency (GHz)

s11 Magnitude

Multiport Connection M.

Dominant Paths Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

(d)

Frequency (GHz)

s22 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

(e)

Frequency (GHz)

s33 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

(f)

Figure 6.2.11: The magnitude of the scattering parameters: (a-c) transmission

coefficients, (d-f) reflection coefficients

by a 5 V CMOS inverting buffer SN74LV04A of Texas Instruments, loaded by a shunt R C

(R=100 Ω, C=2.5 pF). Another buffer of the same type which represents a chip output

92 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

port is switched to the second terminal of the resulting interconnect network. This buffer

is driven by a digital data signal. The noise impulses are injected into the interconnect

through the first port of the resulting network. The schematic of this reduced network

with the inverters is depicted in Figure 6.2.12.

Figure 6.2.12: Simplified network structure for time domain analysis

The inverters are represented by their encrypted SPICE transistor level macromodels.

The transient waveform analysis of the resulting netlist is performed using the HSPICE

circuit simulator. The noise impulses and the data signal are represented in Figure 6.2.13.

The noise voltage in Figure 6.2.13(a) is a repetitive trapezoidal signal Vscharacterized

by the rise and fall times of 5 ns, a duration of 45 ns, a period of 100 ns, and a maximum

voltage value of 1 kV. To determine the influence of the noise impulses on a data signal

the input bit sequence (01001000), represented in Figure 6.2.13(b), is applied at the input

port of the inverter connected to the port 2 of the circuit.

The resulting waveform at the port 3 and at the pin R C are also shown in Figure 6.2.13.

In Figure 6.2.13(c) the coupling impulses are superimposed to both signal states at the

input pin of the second inverter. In Figure 6.2.13(d) the shape of the functional signal at

the pin R C is represented. Obviously the noise impulses affect the low-states of the output

data, causing static faults, i.e. logic perturbation. For voltage impulses with amplitudes

exceeding the value of 1 kV the dominant transmission path between the source Vsand

the load inverter becomes critical.

In general the failure is depending on the amplitude and rise/fall times of the noise im-

pulses as well as on the dimension of the interconnection structures. The determination

of the noise level that may affect the digital signal at a specified chip pin and the propaga-

tion paths of the noise provides important information on the susceptibility of electronic

systems.

A comparison of the time domain response obtained from the HSPICE S-parameter sim-

ulation of the dominant signal paths with the conventional transient analysis of HSPICE

is provided in Figure 6.2.13(d). The comparison between both approaches show small

differences in the number of impulses coupled which are due to the time step control in

the transient simulation.

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 93

Time (sec)

Vs(V)

0 0.5 1 1.5 2 2.5 3 3.5 4

×10−6

200

400

600

800

1000

(a)

Time (sec)

Vp(V)

0 0.5 1 1.5 2 2.5 3 3.5 4

×10−6

(b)

Time (sec)

V3(V)

00.5 1 1.5 2 2.5 3 3.5 4

×10−6

-4

-2

(c)

Time (sec)

V4(V)

HSPICE Simulation

Dominant Path App.

0 0.5 1 1.5 2 2.5 33.5 4

×10−6

-0.5

0.5

1.5

2.5

3.5

4.5

(d)

Figure 6.2.13: Signal at the ports of the network in Figure 6.2.12: (a) noise impulses, (b) nominal

bit sequence, (c) signal at driver output pin, (d) signal at receiver output pin [66]

6.3 Investigation of Influence Parameters

This section will apply the dominant path approach considering many aspects of a circuit.

First a circuit with discontinuities is analyzed. Second multiple sources of noise impulses

are considered. Third the approach is used to analyze critical subcircuits. In the last part

the effects of the termination loads on the propagation of transient impulses is investigated.

6.3.1 Signal Paths with Interconnects of Arbitrary Geometries

The dominant signal path approach presented so far can be applied to any PCB with trans-

mission structures of arbitrary geometries. In this subsection the circuit in Figure 6.3.1

which consists of blocks of interconnect transmission structures and linear passive compo-

nents is analyzed [72]. The first and the second blocks, indicated by (TSTR 1), are three

deformed coupled microstrip transmission lines. The third block, denoted by (TSTR 2), is

94 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

a single trace with a two bends. The fourth block, i.e. (TSTR 3), consists of two parallel

coupled microstrip lines and the last block, i.e. (TSTR 4), is a three-parallel coupled

traces.

(TSTR1)

(TSTR2)

(TSTR3)

(TSTR4)

s′

t′

R1R2

1stPath

2ndPath

Figure 6.3.1: Interconnect circuit with arbitrary geometric structures [72]

A voltage source modeling a disturbance is applied to the circuit at the first and second

strips of the first and second blocks (TSTR 1) respectively. Two resistances R1and R3

of 100 Ω and a capacitance C1of 5 pF are connected between some traces belonging to

different blocks. The target load consisting of a shunt R2C2(R2= 75 Ω, C2=5 pF) is

located at the fifth port of the structure (TSTR 4).

All the microstrip structures are mounted on a FR4 substrate of thickness 365 µm and

with a relative permittivity 4.5. The ground plane and the microstrips of thickness 35 µm

are assumed to be perfect conductors. The geometrical dimensions of the individual

structures are represented in Figure 6.3.2. Their characterization is performed in terms

of the scattering parameters using the high frequency structure simulator HFSS.

The most dominant signal path from the noise source Vsto the target load R2C2is

extracted and evaluated. This path is indicated in the circuit schematic (dashed line).

The extraction is performed at the frequency of 2 GHz. The CPU time required for its

extraction on a Pentium IV 2 GHz platform is about 10 ms.

The dominant signal propagation path results from the crosstalk between the ports of the

transmission structure (TSTR 4). This propagation way is trivial since the bends of the

structure (TSTR 2) and the big space of the structure (TSTR 4) reflect and damp a large

portion of the noise flowing over these structures. Propagation paths may generally also

include reflection subpaths.

In Figure 6.3.3 the most dominant signal path P1, evaluated in terms of the magnitude

of the voltage transfer function Vt′/Vs′, is represented. A good agreement is obtained

comparing with the total transfer function provided by HSPICE frequency domain sim-

ulation. It is obvious that this propagation path does not change for frequencies up to

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 95

(TSTR1) (TSTR2)

(TSTR3)

(TSTR4)

45◦

1 cm

3 cm

200 um

300 um

Figure 6.3.2: Physical characteristics of the microstrip struc-

tures of the PCB in the schematic 6.3.1 according to [72]

5 GHz, even for resonant ones. This represents only a special case since a dominant path

may vary with the frequency, and therefore changes its order.

Frequency (GHz)

Vt′/Vs

Dominant Path Appr.

HSPICE AC-Simulation

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.005

0.01

0.015

0.02

0.025

Figure 6.3.3: Voltage transfer function associated to the most dom-

inant coupling path connecting the source Vs′and the load RC

Clearly the transfer function associated to the most dominant signal path is very close to

the total transfer function relating the noise source and the target load R2C2, and which

corresponds to all existing propagation paths. Eventhough it is very important that the

most dominant path will be extracted at many frequency points and then interpolated

over the interval of the analysis. In that way the resonant frequencies leading to higher

parasitic coupling, and which are responsible for the failure of sensitive digital devices

may be captured.

In order to reduce the coupling impulses, protection procedures have to be made at some

96 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

circuit nodes belonging to the most dominant or critical path. The great advantage of

such procedure leads in attenuating the noise at several target device pins by accessing

only a single or a small number of nodes at the PCB-level.

The time domain analysis of the circuit in Figure 6.3.1 is performed using a single transient

impulse generated according to the ESD model presented in [21]. The electrical network

of this model is depicted in Figure 6.3.4.

C1C2

R1L1L2

Figure 6.3.4: Example of a ESD generator network: R1=330 Ω,

C1=150 pF, L1=90 nH, C2=2.5 pF, and L2=60 pF

For this analysis a discharge voltage of 6 kV is considered. The characteristics of the ESD

voltage waveform generated by this model, loaded by a resistance R=50 Ω, is represented

in Figure 6.3.5(a). The corresponding frequency spectrum is presented in Figure 6.3.5(b).

It is clear that the energy spectrum of this pulse is contained in the frequency range of

1 GHz, since no significant components exist above this frequency.

Time (ns)

Vs′(V)

02 4 6 8 10 12 14 16 18 20

200

400

600

800

1000

1200

(a)

Frequency (GHz)

Vs′(V)

0 0.5 1 1.5 2 2.5 3

100

200

300

400

500

600

700

(b)

Figure 6.3.5: Example of an ESD impulse: (a) waveform, (b) spectrum

The time domain response to the ESD pulse, up to 200 ns, is given in Figure 6.3.6. The

coupling impulses are computed using a combination of the ESD generator model and

the scattering parameters determined considering the most dominant transmission path.

Comparing with the total response obtained by the conventional time domain analysis,

significant amplitudes of the path extracted are observed.

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 97

Time (sec)

Voltage Vt′(V)

1st Dominant Path

HSPICE Simulation

1st and 2nd Dominant Paths

00.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

×10−7

Figure 6.3.6: Time domain response to the ESD waveform in Figure 6.3.5

6.3.2 Propagation of Noise Impulses from Multiple Sources

In this subsection the dominant path approach is applied to more than one noise source.

Dominant, or critical, signal traces transferring significant noise form multiple noise

sources to digital device input ports are determined separately. Accordingly, a scatter-

ing matrix describing the linear interconnect system, which is terminated with the noise

sources and IC I/O ports, is synthesized.

The dominant path approach has been applied to the PCB shown in Figure 6.3.7. It con-

sists of eleven parallel coupled microstrip transmission lines, passive linear terminations,

inverter gates and voltage sources. Microstrip lines which are not connected to each other

are terminated by 50 Ω loads. The voltage sources V1and V2are assumed to be noise

sources, whereas V3represents the nominal signal source. The transmission lines have the

same physical properties like that of the schematic in Figure 6.2.10.

The linear part of the circuit containing the transmission lines and their passive linear

terminations is analyzed using the dominant path approach in thefrequency range of

5 GHz. The scattering matrix relating the external ports, corresponding to the voltage

noise sources and the chip pins, is determined by evaluating the dominant signal paths

relating these ports. For each coefficient the number of signal paths required to give

a good approximation to its exact value are extracted. The extraction of the paths is

performed at the frequency of 2.5 GHz. This is here enough to speed up the algorithms

instead of processing all the frequency points in the range of the analysis, since if the order

of the first set of the paths remains unchanged. The extraction in DC or low frequencies

must be avoided.

The dominant transmission paths relating the voltage noise sources V1and V2and the

target inverter at the node t′are indicated in the schematic of Figure 6.3.7. For both

noise sources a good approximation is already reached considering only the most domi-

nant propagation path. In Figure 6.3.8(a) the magnitude of the transmission coefficient

s14 is represented. The curve representing the value obtained by the dominant path ap-

proach overlaps with the exact analytical curve computed using the multiport connection

98 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

t′

Figure 6.3.7: Interconnect system with two noise sources [73]

method. The remaining propagation paths for the determination of the coefficient s14

may be neglected. Similarly, the transmission coefficient s24 associated to the voltage

source V2is computed. Its magnitude over the frequency range of 5 GHz is represented

in Figure 6.3.8(b). Also here, the results are very close to the exact value of s24. The

phase of the transmission coefficients s14 and s24 are also computed. Their results are

represented in the Figures 6.3.8(c) and 6.3.8(d), respectively. Except a small shift below

the frequency of 1 GHz for s14, a good agreement between the dominant path approach

and the multiport connection method is obtained.

The remaining transmission and reflection coefficients describing the interactions between

the ports connected to voltage sources and inverters are also computed. The magnitudes

of transmission coefficients s12, s13, s23, and s34 are depicted in Figure 6.3.9. For the

computation of the coefficients s13 and s34 in the Figures 6.3.9(b) and 6.3.9(d), the first

dominant path is required, whereas three dominant signal paths are extracted for the coef-

ficients s12,s23 in the Figures 6.3.9(a) and 6.3.9(c). The results show a good convergence

with comparison to the validation method.

The magnitudes of the reflection coefficients s11, s22, s33,and s44 are depicted in Fig-

ure 6.3.10. For the coefficients s11 and s33 two dominant signal paths are required to get

the approximations shown in the Figures 6.3.10(a) and 6.3.10(c). However, the reflection

coefficients s22, and s44 represented in the Figures 6.3.10(b) and 6.3.10(d) are computed

using a superposition of three dominant signal paths.

The scattering matrix computed in that way can be used to perform the frequency and

time domain simulations. Of course, the superposition of the phases of the paths is also

considered. Again, and due to the reciprocity of the paths, the transmission parameters

s21,s31,s32,s41,s42, and s43 do not have to be extracted and evaluated. Their propagation

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 99

Frequency (GHz)

s14 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.00002

0.00004

0.00006

0.00014

0.00016

0.00018

0.0002

(a)

Frequency (GHz)

s24 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 33.5 4 4.5 5

0.00005

0.0002

0.00025

(b)

Frequency (GHz)

s14 Phase (◦)

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(c)

Frequency (GHz)

s24 Phase (◦)

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(d)

Figure 6.3.8: Transmission coefficients s14 and s24 of dominant paths: (a-b) magni-

tudes, (c-d) phases [73]

paths are similar to those of their symmetrical coefficients. In other words the transmitted

power between two nodes takes the same way or path. The linear circuit part analyzed so

far can be regarded as four-port network characterized in terms of the scattering matrix

expressed by







r=1

s11 (Pr)

r=1

s12 (Pr)s13(P1)s14(P1)

r=1

s12 (Pr)

r=1

s22 (Pr)

r=1

s23 (Pr)s24(P2

r=1 Pr)

s13(P1)

r=1

s23 (Pr)

r=1

s33 (Pr)s34(P1)

s14(P1)s24(P2

r=1 Pr)s34(P1)

r=1

s44 (Pr)







100 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

The structure of the resulting circuit is shown in Figure 6.3.11. This circuit is analyzed

in time domain considering the voltage sources and two 1.8 V CMOS single inverter gates

of the type SN74AUC1GU04 of Texas Instruments [57]. Two types of excitation voltages

that are applied at the ports 1 and 2 of the network are studied. The first is a repetitive

fast trapezoidal wave modeling an EFT burst, and characterized by the rise and fall times

of 5 ns, a duration of 45 ns, a period of 100 ns, and a variable amplitude. The second is

a ESD impulse generated by a standard R C model (R= 330 Ω, C= 150 pF) under a

discharge of 1 kV. At port 3 an input voltage source representing a data signal is applied.

The inverter connected to port 3 represents an integrated circuit output port, i.e. driver.

The one connected to port 4, represents the input port of another digital IC, i.e. receiver.

Its input pin is connected to the target node, i.e. port 4, and its output port is terminated

by a shunt R C (R=1 kΩ, C=30 pF).

The determination of the time domain response is performed using an S-parameter sim-

ulation. The scattering parameter model of the four-port network is used in a HSPICE

circuit netlist which includes the voltage sources and the SPICE models of the CMOS

Frequency (GHz)

s12 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 44.5 5

×10−5

(a)

Frequency (GHz)

s13 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.2

0.4

0.6

0.8

1.2

×10−4

(b)

Frequency (GHz)

s23 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.2

0.4

0.6

0.8

1.2

×10−4

(c)

Frequency (GHz)

s34 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

9.95

9.96

9.97

9.98

9.99

10.01

×10−1

(d)

Figure 6.3.9: Magnitude of the remaining transmission coefficients: s12, s13, s23, s34

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 101

inverters including the package parasitics.

To analyze the failure of the CMOS receiver located at the port 4 due to glitches induced

by the coupling propagation paths, time domain simulation is performed. The results

are depicted in Figure 6.3.12. The noise impulses from both disturbances are superposed

to the data signal at the input pin of the receiver. Figure 6.3.12(a) shows the voltage

impulses obtained at the pin RC for the trapezoidal excitation. The shape of the im-

pulses is obtained by the amplitudes of 10 V, and 30 V for V1and V2respectively. In

Figure 6.3.12(b) the voltage waveform obtained at the pin RC for ESD excitations is

represented [74]. Here, the ESD impulses from V1and V2are applied to the circuit at the

time instants 0.3 µs and 0.9 µs respectively. For both impulse types perturbations of the

logic states of the functional signal at the receiver output pin are observed.

For the periodic excitation the coupling impulses cause permanent signal failures, whereas

single impulses affect the functional signal only for the duration of the impulses. In general

the coupling disturbance from many noise sources depends also on the polarization of the

individual pulses and the delay between them. The time domain response obtained by

Frequency (GHz)

s11 Magnitude

Multiport Connection M.

Dominant Path Appr.

00.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

(a)

Frequency (GHz)

s22 Magnitude

Multiport Connection M.

Dominant Path Appr.

00.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

(b)

Frequency (GHz)

s33 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 11.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

(c)

Frequency (GHz)

s44 Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 11.5 2 2.5 3 3.5 4 4.5 5

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

(d)

Figure 6.3.10: Magnitude response of the reflection coefficients

102 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

Linear

Network

R C

Figure 6.3.11: Simplified multiport structure for transient simulation

Time (sec)

Voltage V5(V)

Dominant Paths Appr.

Input Signal

Ref. Method

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

×10−6

0.5

1.5

(a)

s23

s24

Time (sec)

Voltage V5(V)

Dominant Paths Appr.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

×10−6

-0.5

0.5

1.5

(b)

Figure 6.3.12: Coupling noise impulses at the shunt RC for a: (a) trapezoidal excitation,

and (b) ESD impulse [73]

the S-parameter simulation is compared to the conventional transient circuit simulation.

For both types of excitations the system responses considering dominant paths show good

agreement with the total system response.

The simulation time of the whole signal path is dominated by the transient analysis due

to the nonlinear behaviour of the inverters. Nevertheless the S-parameter simulation

proposed is more efficient than the conventional SPICE transient analysis.

6.3.3 Signal Propagation within Subcircuits

In order to study the influence of preprocessing some subcircuits on the dominant signal

paths the transmission structures in the dashed frame of Figure 6.3.7 are grouped as a

single subcircuit which is characterized separately. Figure 6.3.13 shows the structure of

the resulting schematic after this modification.

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 103

Dt′

Figure 6.3.13: Signal paths belonging to different subcircuit parts

For this purpose the circuit netlist is modified and the dominant transmission paths relat-

ing the voltage sources V1and V2, and the target component located at node t′, are again

determined and the associated coefficients are evaluated. The dominant transmission

paths associated to the coefficients s14 and s24 are identical to the ones already computed

without subcircuit reduction. As shown in Figure 6.3.13 the dominant transmission paths

associated to the sources V1and V2travel over the pairs of external nodes (B,C) and

(A,C) of the subcircuit, respectively.

The magnitude of the transmission coefficient s14 in the original case, where the global

system is considered, is compared to the case where the subcircuit in the dashed area is

represented by an equivalent multiport. The results of this comparison are in presented

in Figure 6.3.14. Identical curves are computed for the coefficient s14. The same will still

valid for the remaining coefficients.

The advantage of preprocessing a set of interconnect structures as a subcircuit leads in

the reduction of the circuit size. This procedure may be used when local information

within a subcircuit are not important. This is the case when some structures could not

be changed during the layout design. These can be considered and analyzed as a single

subcircuit whose external ports only are connected to the rest of the system.

On the other hand the subcircuit in the dashed area is analyzed separately. The inter-

actions between its external ports A,B,C, and D are analyzed using the dominant path

approach. Thus, allowing for the determination of weighted noise propagation paths in

local structures and subcircuits. Figure 6.3.15 shows the analyzed subcircuit.

Considering this subcircuit the dominant signal paths between the ports A,B, and C

are extracted. In the subcircuit schematic the most dominant signal paths relating the

ports A,B to the port C are shown. As in the case of considering the global system, the

subpaths extracted within the subcircuit travel the same circuit nodes. As a result the

104 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

Frequency (GHz)

s14 Magnitude

DPA Subcircuit Reduced

DPA Global System

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

×10−4

Figure 6.3.14: Magnitude of s14(P1) computed using the

whole system, and the system after subcircuit reduction

Figure 6.3.15: Subcircuit schematic analyzed

global dominant path contains the local subpath determined between the external ports

of the subcircuit. The results of evaluating the transmission coefficients associated to the

local dominant paths between the external ports of the subsircuit in Figure 6.3.15 are

depicted in Figure 6.3.16.

It is in many situations very important to identify a dominant noise path which does not

include some specific transmission substructures, especially when these substructures are

already well designed. In other words the layout arrangement should be improved using

any other substructures that have a secondary effect on the signal paths. To illustrate

such procedure the circuit schematic in Figure 6.3.13 is considered. In order to extract a

further signal path which does not share any nodes with the substructures in the dashed

area, the approach to dominant signal path extraction is applied until a propagation path

is determined which does not intersect the specified subcircuit.

This procedure is applied to the source V2in the schematic in Figure 6.3.13 for the

identification of a dominant path which has no common nodes with the substructures in

the dashed area. The extracted path is indicated in the same figure. It corresponds to

6.3. INVESTIGATION OF INFLUENCE PARAMETERS 105

Frequency (GHz)

sBC Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.002

0.004

0.006

0.014

0.016

0.018

(a)

Frequency (GHz)

sAC Magnitude

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.0128

0.013

0.0132

0.014

0.0142

0.0144

(b)

Frequency (GHz)

sBC Phase (◦)

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(c)

Frequency (GHz)

sAC Phase (◦)

Multiport Connection M.

Dominant Path Appr.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(d)

Figure 6.3.16: Evaluation of the transmission coefficients sBC and sAC : (a-b) magni-

tudes, (c-d) phases

the second dominant path if the whole system is considered. The evaluation of the new

path extracted is shown in Figure 6.3.17. In Figure 6.3.17(a), the magnitude of s24(P2)

is represented up to the frequency of 5 GHz. Its comparison to the first dominant path

is shown in Figure 6.3.17(b). From this comparison, the second dominant path and its

influence on the functional signal can be neglected above the frequency of 400 MHz.

6.3.4 Impact of Linear Interconnect Terminations

In order to investigate on the effects of the transmission structures terminations on the

noise propagation paths the interaction between the ports 2 and 4 of the circuit in Fig-

ure 6.3.7 is studied [74]. For this purpose, the first dominant propagation path s24(P1) is

determined for different ohmic loads: 50 Ω, 100 Ω, 500 Ω, and 1 kΩ. The results in terms

of the magnitude and phase are presented in Figure 6.3.18.

In Figure 6.3.18(a) the magnitude of s24(P1) is shown. With increasing values of the

106 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

Frequency (GHz)

s24 Magnitude

00.5 1 1.5 2 2.5 3 3.5 4 4.5 5

1.7

1.8

1.9

2.1

2.2

2.3

2.4

2.5

×10−5

(a)

Frequency (GHz)

s24 Magnitude

Second dominant path

Most dominant path

0 0.5 11.5 2 2.5 3 3.5 4 4.5 5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

×10−4

(b)

Figure 6.3.17: Transmission coefficient s24 for: (a) s24(P1), and (b) s24(P1) and s24(P2)

Frequency (GHz)

s24 Magnitude

1 kΩ loads

50 Ω loads

100 Ω loads

500 Ω loads

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.0002

0.0004

0.001

0.0012

0.0014

(a)

Frequency (GHz)

s24 Phase (◦)

1 kΩ loads

50 Ω loads

100 Ω loads

500 Ω loads

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-200

-150

-100

-50

100

150

200

(b)

Figure 6.3.18: Transmission coefficient s24 for various resistive terminations [74]

termination resistances resonances appear periodically. Moreover, the crosstalk noise at

the resonance frequencies is increasing with the values of the terminations. The reason

is that the reflected noise power from the termination loads of the transmission lines,

which increases with the value of the termination resistance, is transmitted through the

individual signal paths to the target load. The phase of the same path, i.e. s24(P1), is

shown in Figure 6.3.18(b). The curves of the phases show almost similar results, except

for the frequencies between 2 and 2.4 GHz. This result is not always the case, especially

when the termination loads consist of capacitors or inductors.

Generally the order of a propagation path may change when applying different load condi-

tions to the terminations of the interconnect structures. For instance the second dominant

path s24(P2) for a 50 Ω and 1 kΩ loads are different. Figure 6.3.19 shows the magnitudes

of the transmission coefficient of the second path s24(P2) for 50 Ω and 1 kΩ loads. The

curve corresponding to 1 kΩ resistances is absolutely above the one corresponding to 50 Ω

terminations over the frequency range of the analysis.

6.4. IMPLEMENTATION 107

Frequency (GHz)

s24 Magnitude

1 kΩ loads

50 Ω loads

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0.2

0.4

0.6

0.8

1.2

1.4

×10−3

Figure 6.3.19: Magnitude of the transmission coefficient s24(P2)

for different terminations

The effect of linear termination loads on the characterization of the propagation paths

can be added to the parasitic behaviour of the layout to get a complete view on the noise

propagation in the circuit. For this purpose appropriate linear models of digital devices

ports can be used to model the pins terminating the transmission structures.

6.4 Implementation

This section describes the implementation process in this thesis. The algorithm efficiency

and convergence are discussed. The modules of the algorithm and program input netlist

and output parameters are described.

6.4.1 Efficiency and Convergence Issues

The simulation of circuits can be regarded as solving related systems of linear algebraic

equations. The classical method used to solve a system of linear equations is the Gaussian

elimination. This method is not efficient for large circuits. Alternatively, the system

matrix can be decomposed into a lower triangular matrix Land an upper triangular

matrix U. For dense matrices, such decomposition requires a total number of arithmetic

operations of

Nt=n3

3+n2−n

where nis the dimension of the circuit matrix. For sparse matrices, this number grows

approximately linearly with the size of the matrix. The LU decomposition can be applied

to compute the determinants of the matrices, given by (5.2.3), and thus called once for

each dominant path. The structure and the size of the circuit matrix and SFG depend

on the topology and the partitioning of the PCB. More partitions lead to sparse matrices

and graphs, whereas less partitions give dense matrices and graphs.

108 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

The identification of the dominant signal paths relating two nodes in a graph leads to

efficient analysis according to equation (5.2.3). Now the summation over all paths is

reduced to a limited number of weighted ones. For a circuit with a number nof nodes

and nTtermination loads, the circuit scattering matrix used for the evaluation of the

signal paths has n′= 2 (n−nT) entries. The SFG generated from this matrix has also

the same number of nodes n′, and a number mof edges

i=nB

i=1

where niis the number of internal ports in the block representing the i-th multiport in

the circuit, and nBis the total number of these blocks.

The problem of solving k-shortest paths algorithm using the algorithm proposed in Section

5.1.2 leads to o(k(m+n′log n′)) operations in the optimistic case. This is the additional

time to the conventional frequency domain solution of the circuit matrix. For dense

circuit matrices, this time overhead can be neglected when compared to the polynomial

time required by the classical methods that are based on the determinant, or inverse

matrix computations. In the case of sparse matrices the total simulation time, including

the time to determine the dominant paths, still vary roughly linearly with the size of the

matrix. The dimension of the problem is then the number of the paths multiplied by the

number of all simulation frequency points.

The transient analysis of the individual propagation paths characterized by their trans-

mission coefficients may be carried out using the time domain convolution of the HSPICE

simulator. The scattering parameters of each port are converted into voltages and cur-

rents. This requires the application of the IFFT to the frequqency domain scattering

parameters to compute the impulse responses. The accurcy of this method depends on

the number of data samples available. This method is very accurate results, but inefficient.

An important technique which is more efficient in comparison with the conventional time

domain analysis is the HB technique. This technique is best suited for weakly nonlinear

circuits with almost sinusoidal excitation. In strong nonlinear circuits containing wave-

forms with sharp transitions, the number of Fourier coefficients needed to describe the

unknown waveform accurately is large. Accordingly, a rapid increase in memory and sim-

ulation time consumption are caused. Therefore, HB cannot be applied accurately and

efficiently. Another disadvantage of this method is its limitation to periodic signals. In

such cases the HSPICE S-parameter simulation can be performed.

6.4.2 Data Structures

The main algorithms for the identification of dominant signal paths are implemented in

C++ language using Microsoft Visual Studio 6.0. The matrix routines have been imple-

mented in a stand-alone applications using the package of MATLAB and then exported

in form of dynamic link libraries to the signal tracing module.

The whole module to dominant path tracing uses also a Complex and a Matrix library

containing the routines of complex numbers manipulation and memory allocation and

6.4. IMPLEMENTATION 109

deallocation, respectively. For the generation of the SFG and the circuit matrix a Mul-

tiPort library, which manages the transmission structures data and the topology of the

circuit, is implemented.

The algorithms to identify and evaluate the critical signal paths are coded within the

module KSShortestPaths. The main application is implemented in the module Domi-

nantPaths. The modules constituting the whole program are represented in the diagram

of Figure 6.4.1.

Complex Matrix Matlab DLLs

MultiPort

SystemGraph

KSShortestPaths

DominantPaths

Figure 6.4.1: Modules of dominant path approach

For the implementation of the algorithms the C++ Standard Template Library (STL)

is used [75, 76]. It provides a significant level of flexible functionality, generalized and

efficient algorithms, and low run-time cost.

6.4.3 Input and output Parameters

The program uses input network files which are similar to the SPICE netlist. However

there are some internal transformations which convert the circuit data into a multiport

representation. The transmission structures can be expressed directly in terms of the

scattering parameters, or in terms of the per unit length matrices R,L,G, and C. The

interconnect scattering matrices are stored in touchstone files and the per unit length

matrices are saved in ASCII files, respectively. An example showing the general format

of a network file is given as

V 2 0 1

P 7

B1 [ 6 ] 3 4 2 5 7 1 block Area00 . tch

B2 [ 4 ] 7 8 19 9 r l g c t c h F i l e 0 2 . r l g c

R1 9 12 1.000000E+3

R2 5 0 1.000000E+3

110 CHAPTER 6. TIME DOMAIN ANALYSIS OF A COMPLETE SIGNAL PATH

C1 5 0 5.000000E−12

L1 9 12 5.000000E−9

...

In this netlist the start node is assumed to be located at the noise source V, and the

target node is represented by the letter P. The symbol Bn[m] represents a transmission

structure with the identifier nand a number of ports m. R, L, and C represent any

lumped elements in the circuit.

The input parameters needed to run the program are:

•Name of the circuit file

•Start, stop, and step frequencies

•Extracting frequency

The output parameters of the programm are the circuit critical connections that belong

to the dominant noise path nodes. At the circuit SFG-level these are given by the nodes

in the SFG. Bellow an example of such output representation.

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

Processing Path Number 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

0 Path cost :9.24 695 Number of nodes : 15 5−2−16−15−29−28−40−38−66−65−

74−72−53−51−57

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

Processing Path Number 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

1 Path cost :13.1 686 Number of nodes : 15 5−2−16−15−29−28−40−39−67−64−

73−72−53−51−57

...

At the netlist level the paths are given by the multiports identifiers and the associating

ports numbers. The following example shows the output connections for such represen-

tation.

MultiPortId : 1 PortId : 3

MultiPortId : 2 PortId : 1

MultiPortId : 3 PortId : 4

...

Chapter 7

Conclusion

This thesis presented a CAD-technique for the determination of noise distribution with

respect to conducted transient impulses at the PCB level. The shown methodology merits

the capability to extract the dominant or critical noise propagation paths that carry

significant noise power from a specified peripheral connector pin to a sensitive device

pin, while the entire system under consideration. The extraction of the dominant paths

is performed for linear interconnects in the frequency domain and their contribution to

the faults of the digital device pins is predicted. The noise propagation paths include

capacitive, inductive, galvanic and multiple reflections paths.

This approach can be used to analyze PCB architectures including passive interconnection

structures with different geometry configurations and lumped circuit elements. Instead

of simulating the entire complex system consisting of complex interconnecting structures

in an electromagnetic field simulator all at once, the whole system is partitioned into

substructures. From these substructures only a fundamental set that may represent ap-

proximately all existing substructures in the system is characterized. Therefore a reduc-

tion of the complexity of the system is achieved by considering only a specific number of

fundamental structures representing the existing physical paths in the circuit.

The extraction of the critical noise propagation paths is carried out using a combination

of efficient graph searching algorithms and the scattering matrix representing the circuit

equations. By means of the k-shortest paths algorithm, simple signal paths are identified

in the signal flow graph that represents the electronic network. These paths are extracted

in a rating order of their associated weights or transfer functions. Their evaluation is

performed by employing the circuit scattering parameters matrix. The scattering param-

eters associated to the individual paths are computed by the means of the matrix form

of Mason’s Formula.

The time domain analysis of the dominant signal paths terminated with passive linear

models of the IC ports is carried out by the Inverse Fourier Transform algorithm for

the frequency domain results. For a complete simulation of the dominant signal paths

consisting of non-linear terminations, hybrid analysis methods are used. An example of

such hybrid methods is the harmonic balance technique, which interfaces the frequency

domain analysis of the linear part of a circuit with the conventional time domain analysis

111

112 CHAPTER 7. CONCLUSION

of the non-linear part. This technique is more efficient than the conventional time domain

analysis based on numerical integration techniques. Its disadvantages are the aliasing

problem and its limitation to periodic signals. The errors introduced by aliasing can be

avoided by over-sampling, but this is achieved at the cost of a higher run time.

The time domain simulation of the whole signal path consisting of the noise source, the

interconnects and the chip’s I/O ports, represented with their electrical or behavioural

models, can be performed by combining the scattering parameter model of the signal

paths and the buffer models of the chip. The resulting circuit netlist can be simulated

using the HSPICE circuit simulator.

Examples of single and repetitive excitation impulses with fast signal transitions and high

amplitudes are applied to some interconnecting systems with CMOS inverter gates. The

propagating noise impulses considering dominant signal paths are computed at the input

ports of these inverters. This methodology provides the ability to analyze and to detect

the critical structure for a detailed analysis. Multiple sources of noise are simulated and

their responses are superimposed.

It was shown that the consideration of a limited number of dominant paths with respect

to a specified noise source and a target device pin may be enough to describe the inter-

action between the corresponding ports. Consequently, the results in terms of scattering

parameters and coupling impulses show a close alignment with the validation methods

corresponding to the global system response.

Since the methodology presented is a frequency domain technique, the signal propagation

paths depend generally on the frequency. A dependency of the signal paths on intercon-

nects characteristics and transient noise parameters is obvious. The signal waveform at

digital device pins is dependent on the noise margin of the device. The consideration of

such a dependency may be helpful for the designer to attenuate the noise transmitted by

these paths.

Moreover, the method proposed takes into account that the critical paths provides not

only an approximation to the total system response, but also allows the identification of

a minimum set of weak subnets at an early stage before any physical implementation of

circuits takes place. The information about signal paths carrying considerable amounts of

the electromagnetic power may be helpful for the designer to develop reliable layouts. The

parasitic behavior can be compensated by taking appropriate and efficient compensation

procedures into account by accessing the critical positions on the PCB level.

Appendix A

Complex Fourier Series

An alternative way to determine the Fourier series is to use the complex form of its

coefficients. In that way the Fourier coefficients can be easily computed than in the case

of the trigonometric form. A periodic signal with a period Tcan be represented in the

time domain by the complex Fourier series expansion defined as

f(t) =

+∞

−∞

cnexp(jnω0t),(A.1)

where ω0is the fundamental angular frequency of the signal and which is given by

ω0=2π

The complex Fourier coefficient cnare defined by

c0=1

TZt0+T

t=t0

f(t)dt, (A.2)

cn=1

TZt0+T

t=t0

f(t) exp(−jnω0t)dt, (A.3)

c−n=1

TZt0+T

t=t0

f(t) exp(nω0t)dt, (A.4)

where t0can be any value of time.

The complex form of the Fourier series contains positive and negative values of the har-

monic frequencies. To obtain the one-sided spectrum (positive frequencies), the coeffi-

cients cnfor the double-sided spectrum are doubled, and the DC component c0remains

unchanged. In contrast to the real-valued trigonometric coefficients anand bn, the Fourier

coefficients cnmay be complex-valued. The trigonometric Fourier coefficients anand bn

can be computed from cnusing the relations

an= 2 Re{cn}

bn=−2Im{cn}.

113

114 APPENDIX A. COMPLEX FOURIER SERIES

For each frequency point the amplitude spectrum is given by

An=pa2

n+b2

The time domain analysis of the individual signal paths using the HB technique is carried

out by considering a number of harmonics approximating the periodic transient signal.

Both signal rise and fall times should be accurately approximated in order to represent the

frequency spectrum. The highest sine wave frequency required, i.e bandwidth, depends

on the rise time.

Figure A.1 shows an example of a periodic trapezoidal signal for which the Fourier coeffi-

cients and the frequency spectrum are evaluated. The switching time during each period

is denoted by ti. The rise and fall times are assumed to be identical and denoted by tr.

trT/2

Figure A.1: Characteristics of a trapezoidal wave

The coefficient a0can be computed as

a0=2

T"Zti/2

A0dt +Zti/2+ts

ti/2

A0(−t

+ti

2+ts)dt#(A.5)

a0=A0

T(ti+ts) (A.6)

The coefficient anis computed as

an=4

TRti/2

0A0cos(nω0t)dt +Rti/2+ts

ti/2A0(−t+ti/2

+ 1) cos(nω0t)dt

=A0T

n2π2ts−cos(2n π

T(ts+ti

2)) + cos(n π ti

T)

= 2 A0T

n2π2tssin(n π

T(ts+ti)) sin(n π ts

T)

(A.7)

Using the symmetry of the function in Figure A.1, bn= 0. Therefore, the total amplitude

spectrum Anis given by an.

An= 2 A0T

n2π2tssin(nπ

T(ts+ti)) sin(n π ts

T)(A.8)

115

Figure A.2 shows the frequency spectrum of a trapezoidal signal with a period T= 100 ns,

a transition time tr= 5 ns, and a pulse width ti= 50 ns. The same figure shows also the

frequency spectrum envelopes approximating this signal at three regions.

Harmonic order

Amplitude (An/A0)

100101102103

10−35

10−30

10−25

10−5

100

Figure A.2: Frequency spectrum envelope

The direct computation of the Fourier coefficients can become difficult for some wave-

forms. More complex periodic, but piecewise linear waveforms, can be decomposed into

a linear combination of more simple functions. For each of these simple functions the

Fourier coeffcients are easily computed. Using the properties of Fourier Transformation

the resulting spectrum of the original waveform can be derived.

116 APPENDIX A. COMPLEX FOURIER SERIES

Appendix B

Some Fundamental Scattering

Matrices

In order to generate the signal flow graphs of various components and junctions that occur

in a microwave circuit the scattering matrices should be derived. The individual subgraphs

can be be connected together to construct the entire network. Some basic microwave

circuit elements commonly used in CAD programs and their scattering matrices are given

bellow.

S11 =Z−Z∗

Z+ZNZ

S=1

Y+ 2YN−Y2YN

2YN−YYYN

S=1

Z+ 2ZN−Z2ZN

2ZN−ZZZN

S=1

3



−1 2 2

2−1 2

2 2 −1

ZN

117

118 APPENDIX B. SOME FUNDAMENTAL SCATTERING MATRICES

S=1

3



1 2 2

2 1 −2

2−2 1 

1

3ZN

S=1

3



1−2 2

−212

2 2 1 

1

3ZN

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