University of Paderborn
Heinz Nixdorf Institute
F¨
urstenallee 11
33102 Paderborn
Modeling and Automated Synthesis of
Reconfigurable Interfaces
Dissertation
A thesis submitted to the
Faculty of Computer Science, Electrical Engineering and Mathematics
of the
University of Paderborn
in partial fulfillment of the requirements for the
degree of Dr. rer. nat.
Stefan Ihmor
Paderborn, Germany
September 14, 2006
Supervisors:
1. Prof. Dr. Wolfram Hardt, Chemnitz University of Technology
2. Prof. Dr. Franz J. Rammig, University of Paderborn
3. Prof. Dr. Daniel D. Gajski, University of California, Irvine
Date of public examination: 22 November, 2006
Acknowledgements
This work was carried out at the Department of Computer Science, Electrical Engineering
and Mathematics of the University of Paderborn from 2002 to 2006. Initially starting my
Ph.D. in the Informatik und Prozesslabor (IPL), I finished this thesis at the Heinz Nixdorf
Institute (HNI), an interdisciplinary center of research and technology of the University
of Paderborn.
First of all, I would like to express my gratitude to my supervisors, Professor Rammig and
Professor Hardt (Chemnitz University of Technology). I consider it a great accomplishment
to have completed this dissertation under their direction. I was very fortunate to work as a
member of both chairs. Therefore, I thank Professor Hardt and Professor Rammig for their
helpful advice, their excellent support and their constant guidance during this work.
Within the working groups of both professors, I had the opportunity to work on research
projects, to supervise student projects, and to advise several students on their bachelor and
master theses. All of this, including my involvement in the lectures of Prof. Rammig and
Prof. Hardt, has given to me a detailed insight into the wide field of embedded systems.
In the same way I want to thank my colleagues Klaus Danne, Florian Dittmann, Marcelo
G¨
otz, Tales Heimfarth, Peter Janacik, Christophe Bobda, Thomas Lehmann, Achim Ret-
tberg, and Mauro Zanella for their cooperation in different projects. Their constructive
criticism improved the quality of the thesis considerably and brought novel ideas into my
work. Furthermore, I am particulary thankful to my colleagues Markus Visarius and Andr´e
Meisel from the Chemnitz University of Technology for their cooperation and interesting
discussions.
I also thank my working students Michel Camel Kouamo Sime, Bertrand Gnokam Defo
and all Bachelor and Master Students who implemented a considerable part of my con-
cepts. Thanks also to Sheila Fleißner who spent a lot of time to revise the language of the
manuscript.
Finally, I would like to express my gratefulness to my dear parents Anna and Gerhard. Their
care and never ending support were a great motivation for me.
Paderborn, September 2006
Contents
List of Figures iii
List of Tables viii
1 Introduction 1
1.1 Motivation and Challenges ............................. 1
1.2 Aim of the Thesis .................................. 3
1.3 Contribution of the Thesis ............................. 5
1.4 Organization of the Work ............................. 6
2 Communication Framework for Embedded Systems 7
2.1 Framework ..................................... 7
2.1.1 Tasks & Media ............................... 8
2.1.2 System Composition ............................ 8
2.1.3 Hardware & Software Interfaces ...................... 9
2.1.4 Modeling Interfaces ............................ 11
2.1.5 Scenarios for Interface Adaptation .................... 17
2.2 System Architecture ................................ 17
2.2.1 The IFS System Architecture Model ................... 17
2.2.2 Modeling the IFB Target-Platform .................... 19
2.2.3 Hardware Execution Platform ....................... 20
2.2.4 Software Execution Platform ....................... 22
2.2.5 The Hardware/Software Interface ..................... 23
2.3 The Role of Reconfiguration ............................ 25
2.4 Summary ...................................... 26
3 Background & Related Work 27
3.1 System-Level Design ................................ 27
3.1.1 Levels of Abstraction ............................ 28
3.1.2 Y-Chart and P-Chart ........................... 30
3.1.3 Intellectual Property and IP-Based Design ................ 31
3.2 Interface-Aware (System-Level) Design Flows .................. 34
3.2.1 Interface and IP Descriptions ....................... 34
3.2.2 Design Flows ................................ 40
3.3 Reconfigurable Systems .............................. 42
3.3.1 The FPGA – A Reconfigurable Hardware Platform ........... 42
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