Advanced Silicon MMICs for
mm-Wave Automotive Radar
Front-Ends
vorgelegt von
Master of Science
Alexander Kravets
geb. in Kiew, Ukraine
von der Fakult¨at IV – Elektrotechnik und Informatik
der Technischen Universit¨at Berlin
zur Erlangung des akademischen Grades
Doktor der Ingenieurwissenschaften
Dr.-Ing.
genehmigte Dissertation
Promotionsausschuss:
Vorsitzender: Prof. Dr. G. Tr¨ankle
Berichter 1: Prof. Dr.-Ing. habil. W. Heinrich
Berichter 2: Prof. Dr.-Ing. Dr.-Ing. habil. R. Weigel
Berichter 3: Prof. Dr.-Ing. N. Pohl
Tag der wissenschaftlichen Aussprache: 29. Oktober 2014
Berlin, 2015
D 83
Acknowledgement
I would like to express my gratitude to Prof. Wolfgang Heinrich and to Prof. G¨unther Tr¨ankle
for having offered me the opportunity to carry out this work at the Ferdinand-Braun-Institut,
Leibniz-Institut f¨ur H¨ochstfrequenztechnik (FBH). Prof. Heinrich’s supervision, involvement
and the fruitful discussions have been of help during the course of this work.
I would like to thank Prof. Robert Weigel and Prof. Nils Pohl for kindly accepting reviewing
this thesis.
The FBH team deserve a big mention: I thank Dr. Udo Pursche for the fruitful cooperation
and for the translation of the abstract to German, Prof. Dr. Matthias Rudolph for all things
modeling, Dr. Franz-Josef Schm¨uckle for his EM wisdom and great mood, Ralf D¨orner and
Jens Schmidt for their assistance with the measurements. I thank Dr. Chafik Meliani and
Dr. Eldad Bahat-Treidel for the friendship and the support.
I thank Dr. Vadim Isaakov for his valuable advices.
I would like to thank Dr. Volker M¨uhlhaus for his support in usage of an EM simulator.
My family’s contributions are too many to be succinctly summarized. Thank you.
i
Abstract
This work presents a high-linearity automotive radar front-end at 77 GHz in 0.25 µm SiGe
technology. The passive elements are realized using thin-film microstrip lines. A detailed
transformer balun synthesis procedure was developed. The realized passive baluns (“rat-race”
and transformer) show excellent common-mode rejection ratios exceeding 30 dB and low losses
of 2.5 dB. On the active side, a low-gain, high-linearity single stage common-emitter LNA
was realized. The selected topology allowed finer trade-off between linearity and sensitivity of
the front-end compared to multi-stage LNA solutions. For the mixer, a low voltage supply,
high-linearity, low-noise double-balanced concept was employed. It uses AC-coupling between
the two stages, which allowed an independent optimization of transconductance, core sizing
and bias: the transconductance was designed for best noise performance, while the core was
chosen for maximum linearity. A high-fidelity two-channel receiver was realized using these
circuit components, which achieved a performance comparable to the published state-of-the-
art results in SiGe: Single sideband noise figure better than 16.5 dB, 1-dB compression point
exceeding -12 dBm, while consuming moderate 82 mA DC current from a 1.6 V supply for
both channels.
ii
Zusammenfassung
Mit der vorliegenden Arbeit wird ein besonders lineares 77-GHz-Front-end in 0,25 µm-SiGe-
Technologie f¨ur Radaranwendungen in Fahrzeugen vorgestellt. Die passiven Komponenten
wurden als D¨unnschicht-Mikrostreifenleitungen hergestellt. Die so realisierten Baluns (rat-
race-Koppler und Transformator) weisen eine hervorragende Gleichtaktunterdr¨uckung (besser
als 30 dB) und niedrige Verluste (ca. 2,5 dB) auf. An aktiven Komponenten wurde zun¨achst
ein einstufiger LNA in Emitterschaltung entwickelt, der zwar eine geringe Verst¨arkung, daf¨ur
aber eine hohe Linearit¨at aufweist. Im Gegensatz zu einer mehrstufigen LNA-L¨osung stellt
er einen besseren Kompromiss zwischen der Linearit¨at des gesamten Front-ends und dessen
Empfindlichkeit dar. Der Mischer wurde rauscharm und besonders linear nach dem doppelt
balancierten Konzept mit niedriger Speisespannung realisiert. Durch Verwendung von Wech-
selspannungskopplung zwischen beiden Stufen des Mischers konnten die Transistorgr¨oßen und
die Arbeitspunkte der beiden Stufen des Mischers getrennt optimiert werden: Die erste Trans-
konduktanzstufe ist rauschoptimiert, die zweite Stufe, der eigentliche Mischerkern, ist f¨ur hohe
Linearit¨at ausgelegt. Aus all diesen Komponenten wurde ein Zweikanal-Empf¨anger aufgebaut,
der den gegenw¨artigen publizierten Stand der Technik in SiGe-Technologie repr¨asentiert: Einer
einseitenbandbezogenen Rauschzahl von weniger als 16,5 dB und einem eingangsbezogenen 1-
dB-Kompessionspunkt von -12 dBm stehen dabei eine Stromaufnahme von 82 mA aus einer
1,6-V-Speisespannungsquelle f¨ur beide Empfangskan¨ale gegen¨uber.
iii
Contents
1 Introduction 1
1.1 RoadSafety...................................... 1
1.1.1 Automotive Comfort and Safety Systems . . . . . . . . . . . . . . . . . 2
Comfort Systems Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2
SafetySystemsOverview .......................... 3
1.2 Automotive Radar Applications – Brief History and Status . . . . . . . . . . . 4
1.2.1 Automotive Short-, Mid- and Long-Range Radar . . . . . . . . . . . . . 5
1.2.2 Automotive Radar Frequency Band Regulation . . . . . . . . . . . . . . 5
1.2.3 Multi-Channel Automotive Radar Front Ends . . . . . . . . . . . . . . . 6
1.3 Thesis Objectives and Organization . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Automotive LRR FMCW Radar – System Level Approach 9
2.1 FMCW Radar Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 WaveformDerivation............................. 9
2.1.2 Two-way Radar Equation . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Leakages and Reflections in FMCW Radar . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Automotive Radar Classification According to TX-RX Separation, Sys-
tem Architecture and Trends . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Antenna-Transceiver Combining . . . . . . . . . . . . . . . . . . . . . . 14
2.2.3 FMCW Radar with System Non-idealities . . . . . . . . . . . . . . . . . 15
Noise Floor with Blockers Present . . . . . . . . . . . . . . . . . . . . . 16
Analysis of Blockers Passing through a Non-linear Transfer Function . . 20
2.2.4 Conclusions.................................. 28
3 Circuit Environment 29
3.1 MMIC Process and Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.1 The Process of Choice: SG25H1 by IHP . . . . . . . . . . . . . . . . . . 29
3.1.2 HBTModeling ................................ 29
3.2 PassiveElements................................... 30
3.2.1 Stack ..................................... 30
3.2.2 Resistors ................................... 31
3.2.3 Capacitors .................................. 31
3.2.4 Passivated Microstrip Transmission Line Model . . . . . . . . . . . . . . 33
The Selected TL Modeling Approach . . . . . . . . . . . . . . . . . . . . 34
3.2.5 ProberPadsModels ............................. 35
Pad Model
1–RC ............................ 35
Pad Model
2–RLC............................ 36
v
Contents
4 Design of Circuits 39
4.1 LNA.......................................... 39
4.1.1 Main Requirements imposed on the LNA . . . . . . . . . . . . . . . . . 39
4.1.2 TransistorSizing ............................... 40
4.1.3 LNA Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.4 Bias Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Vcc valueselection .............................. 44
Ice,q valueselection.............................. 45
4.1.5 Low-Frequency On-Chip Bias Circuitry . . . . . . . . . . . . . . . . . . 45
4.1.6 MatchingCircuitry.............................. 46
RFInputMatch ............................... 46
RFOutputMatch .............................. 48
Stability.................................... 49
4.1.7 RealizedLNA................................. 51
4.1.8 S-Parameters................................. 52
Simulated vs. Measured S-Parameters . . . . . . . . . . . . . . . . . . . 52
4.1.9 NoiseFigure ................................. 54
Noise Figure Measurement Setup . . . . . . . . . . . . . . . . . . . . . . 54
LNA NF Measurements vs. Simulations . . . . . . . . . . . . . . . . . . 56
4.1.10Linearity ................................... 57
Linearity Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 57
Simulated vs. Measured Gain Compression . . . . . . . . . . . . . . . . 57
4.1.11 Measurements vs. Simulations: Gain, Linearity, NF . . . . . . . . . . . 58
4.1.12 Benchmarks and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 Balun ......................................... 60
4.2.1 Main Requirements imposed on the Balun . . . . . . . . . . . . . . . . . 60
4.2.2 Balun Performance Evaluation Setups in Simulation and Measurement . 60
4.2.3 ActiveBalun ................................. 61
Functionality ................................. 61
Overview of Existing Topologies . . . . . . . . . . . . . . . . . . . . . . 62
Performance ................................. 62
4.2.4 Passive Balun
1 – Rat Race Coupler . . . . . . . . . . . . . . . . . . . 63
Classical Rat Race Coupler Operation Principle . . . . . . . . . . . . . . 63
Reduced-Length Rat Race Coupler Design . . . . . . . . . . . . . . . . . 65
Realized Reduced-Length Rat Race Coupler . . . . . . . . . . . . . . . . 67
Characterization Approach for mm-Wave Baluns . . . . . . . . . . . . . 67
Reduced-Length Rat Race Coupler Measurements vs. Simulations . . . 70
4.2.5 Passive Balun
2–Transformer ...................... 73
Transformer Background . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General Transformer Core Design Guidelines – Circuit Level Approach . 73
Transformer Balun Synthesis Flow – System level Approach . . . . . . . 74
RealizedTransformer ............................ 76
Transformer Measurements vs. Simulations . . . . . . . . . . . . . . . . 77
4.2.6 Balun Overview and Discussion . . . . . . . . . . . . . . . . . . . . . . . 81
4.3 Mixer ......................................... 83
vi
Contents
4.3.1 Main Requirements Imposed on Mixer . . . . . . . . . . . . . . . . . . . 83
4.3.2 Mixer Balancing Approaches . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.3 Transconductance Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TopologySelection.............................. 85
Common Mode Suppression Techniques Overview . . . . . . . . . . . . 86
4.3.4 Mixer Transconductance-to-Core Interface . . . . . . . . . . . . . . . . . 86
4.3.5 MixerCore .................................. 88
Core Transistors’ Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LOInterface ................................. 91
4.3.6 MixerIFInterface .............................. 93
IF – Post-Mixer Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Mixer IF Interfaces Overview [49] . . . . . . . . . . . . . . . . . . . . . . 93
Mixer IF Interface Design . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3.7 RealizedMixer ................................ 95
4.3.8 NoiseFigure ................................. 95
DSB vs. SSB Noise Figure Definitions . . . . . . . . . . . . . . . . . . . 97
Noise Figure Measurement Setup . . . . . . . . . . . . . . . . . . . . . . 97
Noise Figure: Single-Ended vs. Differential . . . . . . . . . . . . . . . . 98
Total Noise Temperature Derivation and Analysis . . . . . . . . . . . . 100
4.3.9 Linearity ................................... 104
Linearity Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 104
Simulated vs. Measured Conversion Gain Compression . . . . . . . . . . 104
4.3.10 Measurements vs. Simulations: Conv. Gain, Linearity, NF . . . . . . . . 105
4.3.11 Benchmarks and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 106
5 Receiver Integration 109
5.1 1-ChannelReceiver.................................. 109
5.1.1 Realized 1-Channel Receiver . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.2 NoiseFigure ................................. 110
Total Noise Temperature Derivation and Analysis . . . . . . . . . . . . 110
5.1.3 Linearity ................................... 114
Linearity Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1.4 1-Channel RX Measurements . . . . . . . . . . . . . . . . . . . . . . . . 114
Conversion Gain and NF vs. Core Bias . . . . . . . . . . . . . . . . . . 114
Conversion Gain, Linearity, NF . . . . . . . . . . . . . . . . . . . . . . . 115
5.2 2-ChannelReceiver.................................. 116
5.2.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.2.2 LOSplitter .................................. 117
Functionality ................................. 117
RealizedLOSplitter............................. 117
Large Signal Measurements vs. Simulation . . . . . . . . . . . . . . . . 118
5.2.3 Isolation.................................... 119
Isolation Improvement Techniques . . . . . . . . . . . . . . . . . . . . . 120
5.2.4 Realized 2-Channel RX . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.5 2-Channel RX Measurements . . . . . . . . . . . . . . . . . . . . . . . . 122
vii
Contents
Isolation.................................... 122
ConversionGainvs.IF ........................... 122
Conversion Gain, Linearity, Isolation, NF . . . . . . . . . . . . . . . . . 122
5.2.6 Benchmarks and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 125
6 Conclusions 129
Bibliography 131
viii
1 Introduction
1.1 Road Safety
Road safety is a major societal issue. While the likelihood of having a road crash for a single
individual, on average, is in the range of once every 25 years (in developed countries), society
as a whole pays a crushing price for the cumulative effects of crashes [13]. Annually worldwide
between 20 to 50 million people suffer non-fatal injuries (with many incurring a disability) and
1.24 million people are killed because of accidents involving motorized vehicles. Road traffic
injuries are the leading cause of death among young people, aged 15–29 years. On the roads
of the European Union in 2012 28,000 people died, i.e. the equivalent of a medium town, and
about 250,000 people were seriously injured [17].
In July 2010 The European Commission has adopted challenging plans to reduce the number
of road deaths on Europe’s roads to one half by 2020 [16]. There are seven strategic objectives
for this end:
1. Improved safety measures for trucks and cars
2. Building safer roads
3. Developing safer vehicles
4. Strengthening licensing and training
5. Better enforcement
6. Targeting injuries
7. A new focus on motorcyclists
Vehicle safety can be loosely separated into 2 categories: passive and active. Passive measures
should reduce injury rate when an accident is inevitable. In this category are: seat belts,
airbags, anti-lock braking systems (ABS) and electronic stability control (ESC). Active safety
means having the ability to predict a situation which could probably result in an accident and
having the capability to react to it timely so the accident could be avoided, or at least its’
impact is reduced (pre-crash sensing).
Human limitations in sensing and control multiply when hundreds of vehicles share the same
roads at the same time. Traffic flow consisting of cars controlled by people is doomed to
inefficiency due to human aspects of delayed response to traffic conditions. When we detect
brake lights ahead, time is expended as we assess the situation and proceed to apply our own
brakes, if needed. When traffic ahead accelerates, a similar lag time is incurred to sense that
1
Introduction
condition and follow suit. The aggregate effect of these factors creates “accordion effects” or
“shock waves” in dense traffic flows, as well as the relatively slow clearance time for intersections
controlled by traffic signals. Traffic congestion is also caused by the sheer volume of vehicles
attempting to use roadways, exceeding physical capacity limitations.
Moreover, reducing the time interval from the recognition of the situation to the vehicle’s stop
could greatly reduce collision probability. If the reaction time could have been improved by
0.25 s collision probability in case of rear-end collisions reduces by 30 % [35], [26]. Collisions at
intersections could have been avoided in 50 % of all cases if the driver knew about the situation
0.5 s in advance. If it is too late to avoid the accident, the information about the location and
the severity of the impact lets the vehicle take safety measures such that the risk of injuries
is minimized. For example, the detection of an unavoidable side impact gives enough time to
inflate airbags [21].
Planning engineers envision a cooperative ecosystem where vehicles exchange data with other
vehicles (V2V), between vehicles and the infrastructure (V2I) and between infrastructures
(I2I) in real time to have drivers better informed, reducing risks of accidents and making
traffic flows run more efficiently and smoothly overall. The human inefficiencies noted above
will be gradually moved to the domain of machine sensing and control. From a legal standpoint,
sensors and computers are not allowed to make important decisions instead of humans on the
highways, but to complement human natural sensors that were not suited for operation while
moving at high speeds.
To create such a cooperative ecosystem:
a system based on fusion of sensors has to be made available
the costs of these technical solutions have to be brought down so they can be fitted onto
mid- to lower-end of the vehicles
1.1.1 Automotive Comfort and Safety Systems
The term “comfort systems” (or “convenience systems”) came into being in the late 90ies when
automotive companies were ready to offer driver-assist systems to their customers but were
not yet ready to take on the legal implications and performance requirements that would come
with introducing a new product labeled as “safety system” [13].
Comfort Systems Overview
Parking Assist. The simplest form of such system is a rear-facing camera, which simply
offers a view of the area behind the vehicle but no driver warnings. Warning capability
can be added by an ultrasonic sensor, covering the immediate area around the car. More
advanced systems use short range radar to cover an extended range and provide the
driver with more precise information as to the location of any obstacle.
2
Road Safety
Adaptive Cruise Control (ACC). It is the primary comfort system for highway driving.
ACC allows a driver to set a desired speed which is automatically reattained when the
road ahead is unobstructed. If a close vehicle in front moves at a slower speed then
throttling and brake of the host vehicle is controlled to match this of the slower vehicle.
In the future ACC systems will be extended to be operational at low speeds including
full-stop capability (also known as “stop-and-go ACC”). Systems currently on the market
monitor the scene using either long-range-radar or lidar (laser radar), future systems may
also use machine vision.
Lane-Keeping Assistance (LKA). It uses computer vision technology to detect the lane
in which the vehicle is traveling and adds torque to the steering wheel in order that the
vehicle stays on the lane.
Safety Systems Overview
Main safety systems can be classified into the following sub-groups [69], [13]:
Driver Perception Assistance
–Adaptive headlights: vehicle speed is taken into account to control illumination
pattern.
–Night vision: helps to see objects far behind the view of the vehicle lights; is realised
either with passive infrared camera or long range radar.
Crash Prevention
–Forward collision warning / mitigation / avoidance. Some European car manufac-
turers implement only ACC (marketed as a comfort feature), while some Japanese
manufacturers added an active brake assist for collision mitigation. Unlike the
smooth deceleration of ACC system, the active brake assist provides much higher
forces for deceleration. Thus comfort features of ACC are extended by the active
brake assist into the safety domain. Systems to prevent forward collisions rely on
long range radar or lidar sensing, sometimes augmented by machine vision.
–Lane departure warning and line change support. Machine vision techniques are
used to monitor the lateral position of the vehicle within its lane.
–Side object warning (or “blind spot monitoring” ). A short range radar is used to
monitor the rear left/right sectors obscured by the car’s carcass.
–Pedestrian recognition and warning. Sensing systems based on machine vision per-
form real-time processing to detect the pedestrians and asses the potential danger.
Pre-crash Sensing. Radar data can be combined with ABS data so if an imminent
accident is identified by sensors and/or car dynamics then the brakes are pre-charged,
the seat belt are pretensioned, airbags pre-fired, seat orientations will be adapted, sunroof
will be closed, etc.
3
Introduction
The aforementioned sensor technologies, such as infrared camera, video camera, ultrasound,
lidar have each their own specialized advantages [56], [69]. However, radar is the only sensor
that:
can measure both range and angle-of-arrival accurately of both moving and stationary
objects
is capable of directly providing velocity information
is not affected by weather conditions: it retains its performance in fog/rain/snow
can be mounted invisibly behind plastic fascia
This suggests radar as the most robust technology for a vehicular environment. Additionally,
radar can simultaneously integrate several automotive comfort and safety features.
1.2 Automotive Radar Applications – Brief History and Status
First experiments with automotive radar took place in the late 50ies [91]. Cadillac Cyclone
(Fig. 1.1), General Motors’ concept car from 1959, was a first car to feature a radar. Behind
the shiny black plastic cones (radomes) a modified airplane radar was installed. A proximity
warning device was supposed to prevent collisions but it was never tested in practice.
Figure 1.1: Cadillac Cyclone, General Motors, 1959
In the 70ies the development moved to microwave frequencies. From the early beginning the
key driver was collision avoidance. Due to progress both in semiconductor microwave sources,
such as Gunn diodes and GaAs MMICs and to quickly evolving micro-controllers and DSPs
the commercialization of automotive radar became feasible in the 90ies. in 1993 Greyhound
(USA) installed more than 1600 Radar collision warning systems in their bus lines [36] yielding
a reduction of accidents of 21 % (compared to the year before). The 24.125 GHz pulse-Doppler
4
Automotive Radar Applications – Brief History and Status
radars were developed by Vorad Safety Systems, San Diego and deployed a flat six-by-eight
inch phased-array antenna.
In 1999 Daimler introduced 1st commercial radar ACC “Distronic” [109], which operated at
76.5 GHz and used the pulse-Doppler principle. Other automotive manufacturers followed with
equipping their top-models with radars.
1.2.1 Automotive Short-, Mid- and Long-Range Radar
Automotive radar is classified according to covered ranges and azimuths (table 1.1). For Short
Range Radar (SRR), ranging accuracy and large field of view are more critical than for Long
Range Radar (LRR). These are addressed by higher bandwidth, multiple radar placement and
antenna design. As explained in chapter 2 the dynamic range of the receiver is very critical in
LRR case.
Table 1.1: Classification of Automotive Short-, Mid- and Long-Range Radar [67], [56]
Detection
Range
Ranging
Accuracy
Field of
View
Bandwidth
[m] [m] [◦] [GHz]
SRR 0−30 0.05 90 −180 4 −5
MRR 2−150 0.1 30 −60 0.5 −1
LRR 20 −250 0.5 5 −20 0.2 −1
1.2.2 Automotive Radar Frequency Band Regulation
25 −29 GHz: band allocated in North America for automotive ultra-wide band (UWB)
SRR systems
22 −26.65 GHz: allocated by EC (ETSI EN 302 288-1) to be deployed from 2005 till
2013 with penetration rate restricted to 7 % of all cars in each EC country (so that the
other services in vicinity of 24 GHz)
24.05 −24.25 GHz: license-free ISM band, can be used for CW radar (since it does not
have enough bandwidth for pulsed radar). Since lane change assistance does not require
highest range resolution, this band is deployed for MRR applications
76 −77 GHz: this band is standardized in Europe (ETSI EN 301 091) for LRR, is being
allocated for Intelligent Transport Services (ITS) in Europe, North America, Japan
77 −81 GHz: EU, Japan, North America allocated this band for UWB SRR and MRR.
In EU this band usage was permitted from 2005 onwards
5
Introduction
1.2.3 Multi-Channel Automotive Radar Front Ends
Multi-channel front ends are of great interest for current and future applications in vehicu-
lar and other fields. The receive channel diversity could be deployed to better exploit the
information contained in the received signals for the following purposes:
Angle-of-arrival estimation is required in LRR. Among other techniques this can be
achieved by antenna- and receiver-diversity [95] with conjunction with parameter esti-
mation methods, based on subspace techniques [31], [63].
The information available from several receive channels could be deployed as an electronic
beam former (also known as digital beam former), by steering the beam away from an
interferer towards the desired signal. Therefore the immunity to multi-path scattering
present in real-world conditions is increased [72], [109]. The electronic beam former is
an alternative to mechanically beam steering, which is sensitive in mechanical reliability
over lifetime and is limited with regard to miniaturization [91].
Coherent summation of the multi-receiver outputs improves signal-to-noise ratios thereby
improving the equivalent receiver sensitivity.
1.3 Thesis Objectives and Organization
The goal of this dissertation is to present circuit blocks to implement a 77 GHz multi-channel
receiver for automotive radar using SiGe technology. The emphasis is put on high linearity
and sensitivity of the receiver, for a very high dynamic range is crucial for such instrumental
applications.
Beside this:
development and exploration of alternative design methodologies suitable for designs at
the technology margins (fmax/3)
minimizing the power consumption by reducing both the circuit blocks’ supply voltages
and quiescent currents and selecting power-efficient circuit topologies
integration – reducing of the number of separate chips
The thesis is organized as follows:
In chapter 2 automotive FMCW LRR performance is assessed on system level. Two cases of
FMCW radar transceiver combining (quasi-bi-static and mono-static) are compared in presence
of several leakages and reflections.
Chapter 3 discusses the circuit environment. Additionally, models are developed for the pas-
sivated microstrip transmission line model and for the prober pads.
6
Thesis Objectives and Organization
Chapter 4 focuses on design of active and passive circuits, such as LNA, mixer, several balun
types. Various topologies and circuit- and system-level design trade-offs (especially linearity vs.
noise) were juxtaposed. The measured circuits are benchmarked with the published results.
Chapter 5 deals with the integration of the circuits from the previous chapter into 1- and 2-
channel receivers. For the 2-channel receiver an active LO splitter is designed and isolation
improvement techniques are discussed. The measured receivers are benchmarked with the
published results.
Chapter 6 wraps up this work with summary, contributions’ outline and possible future inves-
tigations’ suggestions.
7
2 Automotive LRR FMCW Radar – System
Level Approach
2.1 FMCW Radar Fundamentals
2.1.1 Waveform Derivation
Frequency Modulated Continuous Wave Radar is a technique for obtaining range information.
FMCW Radar has a long history [64], in the past its use was limited to specialized applications,
such as radio altimeters. Linear frequency modulation is very versatile when applied to an
optimal receiver (also known as correlation receiver) [79] and exists in nature: big brown
bat deploys dual linear frequency modulated ultrasonic radar to navigate and forage [48].
In a correlation receiver the transmitted signal is mixed with a delayed replica of itself –
this is also known as homodyne receiver. A frequency measurement must be performed to
obtain range from FMCW receiver. This is done in the digital domain using FFT (Fast
Fourier Transform). The main advantage of FMCW radar is its high time bandwidth product
(Tsw∆F) [23], [41], [94]. High sweep time values improve the overall sensitivity (noise filter
bank bandwidth is inverse proportional to sweep time) while the range resolution is inverse
proportional to sweep bandwidth.
Frequency modulation can be achieved in several ways. Here one the most common ways is
considered – sawtooth modulation of the carrier.
The instantaneous frequency of the transmitted signal is (Fig. 2.1a):
fTX =f1+∆Ft
Tsw
[Hz] (0 ≤t<Tsw) (2.1)
where f1is the start frequency (76.5 GHz, in this case), ∆F– the sweep bandwidth of the
radar (1 GHz) and Tsw is the sweep time duration (typically in the order of magnitude of 1 ms).
Therefore, the instantaneous phase of the transmitted signal is:
ϕTX(t) = 2π
t
Z
0
fTX(t)dt= 2πf1t+ 2π∆Ft2
2Tsw
+ϕT[rad] (0 ≤t<Tsw) (2.2)
where ϕTis the phase offset due to the integration. The instantaneous phase of the received
9
Automotive LRR FMCW Radar – System Level Approach
signal is:
ϕRX(t) = ϕTX(t−τ)=2π
t−τ
Z
0
fTX(t)dt= (2.3)
= 2πf1(t−τ)+2π∆F(t−τ)2
2Tsw
+ϕT+ϕR[rad] (τ≤t<τ+Tsw)
where ϕRis the phase offset added by the target and
τ= 2 d
c0
[s] (2.4)
is the delay of the signal occurring due to two-way propagation (the target is distanced d
meters from the radar). As it is apparent from equation 2.4 and previous considerations,
τTsw (2.5)
After mixing and low-pass filtering the Intermediate Frequency (IF) signal is obtained:
ϕIF(t) = |ϕRX −ϕTX|=
2π∆F
Tsw
τt + 2πf1τ−ϕR−π∆Fτ2
Tsw
[rad] (2.6)
In equation 2.6, the most important term is the first, since it represents the beat frequency,
proportional to the range. The second and third terms in equation 2.6 represent constant phase
offset added by target and the last, fourth term can be neglected, since equation 2.5 holds.
fbeat, static =wbeat, static
2π=∆F
Tsw
τ=∆F
Tsw
2d
c0
[Hz] (where dis the unknown range)
(2.7)
Therefore, equation 2.7 yields fbeat, static = 33. . . 1333 kHz for d= 5. . . 100 m.
The beat signal spectrum is:
Sbeat, static(f) =
Tsw
Z
0
cos(wbeatt)e−jwtdt= (2.8)
=sin((wbeat −w)Tsw
2)
wbeat −w·ejwbeat−w
2Tsw +sin((wbeat +w)Tsw
2)
wbeat +w·e−jwbeat+w
2Tsw
It must be added that since in time domain the signal is periodic with period Tsw, its’ Fourier
transform is sampled with frequency 1/Tsw.
This derivation was performed for static targets. For targets moving towards the radar with
radial velocity vr[95]:
fbeat, moving =fbeat, static −fDoppler [Hz] (2.9)
10
FMCW Radar Fundamentals
where:
fDoppler = 2vr
c0
fTX [Hz] (2.10)
Equation 2.10 is known as the Doppler effect: for an observer moving relative to the wave
source the frequency is changed.
Therefore the beat frequency contains a term proportional to the target’s distance and a term
proportional to target’s velocity. In order to estimate both targets’ properties two sweeps
(up- and down-, Fig. 2.1b) can be performed so 2 equations with 2 unknowns are formed.
In scenarios where a radar can be jammed by neighboring radar, especially such as SRR the
RX
sweep time [s]
RF [Hz]
TX
∆F
Tsw
τ
(a) TX and Corresponding RX Frequencies
sweep time [s]
IF [Hz]
Tsw
fr+fdoppler
τ
fr
fr-fdoppler
(b) Corresponding IF
Figure 2.1: FMCW: Frequencies Plane vs. Time for positive Doppler Target Frequency
CW radar can be modulated with predefined pseudo-noise sequences [21], [99], so the radar is
“blind” to other pseudo-noise signatures as well as clutter.
2.1.2 Two-way Radar Equation
The transmitted power is reflected by the target and returns to the receiver (it is assumed that
the transmitter and receiver are co-located, Fig. 2.2a and Fig. 2.2b). The received power can
11
Automotive LRR FMCW Radar – System Level Approach
be described by the following equation [94]:
PRX =PTXGTXGRX
σc02
(4π)3f2d2n[W] (2.11)
In the logarithmic form the two-way radar equation is:
PRX =PTX + 2G+ RCS + 20 log(c0)−10 log (4π)3f2−20nlog(d) [dBm] (2.12)
where:
PRX = +15 dBm
G=GTX =GRX is the TX and RX antenna gain, assumed to be 20 dB
RCS = 10 log σstands for “Radar Cross Section”. Similar to the receiving antenna,
a radar target also intercepts a portion of the power, but reflects it in the direction
of the radar. The amount of power reflected back toward the radar is determined by
RCS of the target. RCS is a characteristic of the target that represents its size as
seen by the radar. In the linear scale radar cross section σhas the dimensions of area.
Additionally, it has a strong dependence on the angle of incidence. For modern sedan
cars: RCS = +3. . . + 17 dBsm [89]. In the following calculations RCS = +3 dBsm is
assumed
n is the path loss exponent: for multi-path n= 2.5. . . 3; here LOS (line of sight) assumed
n= 2
Table 2.1: Relationship between PRX and Corresponding Target Distance
PRX [dBm] d [m]
−51 5
−115 200
2.2 Leakages and Reflections in FMCW Radar
In pulse radar a narrow pulse in time domain is transmitted and the range is estimated from the
time difference between the received (echo) signal and the transmitted signal (reference time
stamp). Therefore, the time instances of transmission and reception don’t coincide, so the RX
is inherently isolated from the TX. In contrast to pulse radar, FMCW radar’s major drawback
is linked to its correlative nature: simultaneously receive while transmitting so there is an
inherent RX sensitivity degradation due to TX leakage into the RX. Duplexers widely used
to separate TX and RX communication bands cannot be used since TX and RX frequencies
are essentially the same in FMCW radar. In this application (LRR) the transmitted signal
power is +15 dBm while the received signal from the furthest target is −115 dBm. Even
12
Leakages and Reflections in FMCW Radar
were the overall TX to RX isolation 40 dB (an optimistic estimation, regardless of antenna
arrangement) then the TX leakage signal is 90 dB above the desired RX signal. This would
mean, that ideally the front end has to accommodate such dynamics and still remain linear
enough. Otherwise, false targets’ indications due to spectral regrowth will appear. This strict
linearity requirement, simultaneously in conjunction with low noise figure specification (needed
to cover the maximal range) would require a very challenging front end. It also may explain why
pulse radar approach is historically more common than FMCW – due to inherent mutually-
exclusive TX-RX time-domain multiplexing.
2.2.1 Automotive Radar Classification According to TX-RX Separation, System
Architecture and Trends
TX
RX
(a) Quasi-Bi-static
TX RX/
(b) Mono-static
Figure 2.2: Quasi-bi- vs. Mono- Static Radar
when separate TX and RX antennas are deployed the arrangement is called quasi-
bi-static [36] (Fig. 2.2a). Quasi-bi-static radar arrangement avoids the most severe
mono-static radar leakages and reflections (Fig. 2.5).
The main drawback of quasi-bi-static arrangement is the space consumed by an addi-
tional antenna, which could be limiting factor in several automotive radar applications.
Hence, a compromise where TX and RX share same antenna, called mono-static radar
(Fig. 2.2b, 2.4). It is an attractive solution due to its compactness, despite leakages and
reflections (Fig. 2.6).
A multi-static radar system is one in which there are at least three components - for example,
one receiver and two transmitters, or two receivers and one transmitter, or multiple receivers
and multiple transmitters. By definition, it is a generalization of the quasi-bi-static radar
system, with one or more receivers processing returns from one or more separated transmitters.
This is the case in automotive LRR applications, where if angle measurement are crucial
13
Automotive LRR FMCW Radar – System Level Approach
multiple receivers with multiple antennas are deployed [95], [91]. Additionally, both at RX
and TX sides antenna count might be increased for digital beam-forming purposes.
In terms of commercial automotive radar systems there is a continuum of solutions [67]: from
low-end single antenna mono-static radars ICs (1 ×RXN7740) to high-end single TX antenna,
16 RX antennas (1 ×RTN7730, 4 ×RRN7740). Since the early 2000 the trend for the high-
end automotive radar sensors is in favor of multi-channel architecture, driven by the digital
beam-forming applications and advances in array signal processing theory [91], [72], [109].
2.2.2 Antenna-Transceiver Combining
Fig. 2.3 and Fig. 2.4 show the antenna-transceiver interfaces for the quasi-bi-static and mono-
static cases. The quasi-bi-static case (Fig. 2.3) is straightforward. The mono-static interfaces
can be further subdivided in 2 subgroups:
Circulator (Fig. 2.4a): conceptually a circulator (a passive ferromagnetic non-reciprocal
three port [15]) lends itself perfectly for the combiner: power entering any port is trans-
mitted to the next port in rotation, with the third port being isolated. The drawbacks
normally associated with circulators at such frequency are: performance (isolation, in-
sertion loss), availability, size, integration (it cannot be integrated on the IC).
Coupler (Fig. 2.4b): a 3 dB branch-line coupler divides the input signal between 2
outputs, therefore theoretically it is a less attractive option. In the TX mode only half
of TX signal reaches the antenna (the other half goes to the LO) and in the RX mode
only half of received signal reaches the LNA (the other half is dissipated on the PA
output impedance), therefore the theoretical SNR reduction (compared to the circulator
case) is 6 dB. Despite this limitation branch-line couplers can be integrated on chip, with
isolation up to 25 dB and insertion loss of circa 1 dB [43], therefore are preferred in
current mono-static LRR implementations.
LO Source PA
Front-End
Coupler
IFout
LO Buffers
LOin RFin
RX Antenna
TX Antenna
Figure 2.3: TX-RX Combining Approach: Quasi-Bi-static
14
Leakages and Reflections in FMCW Radar
LO Source PA
Front-End
Circulator Antenna
Coupler
IFout
LO Buffers
LOin RFin
(a) Circulator
LO Source PA
Front-End
Antenna
IFout
LO Buffers
Coupler
LOin
RFin
(b) Coupler
Figure 2.4: TX-RX Combining Approaches: Mono-static
2.2.3 FMCW Radar with System Non-idealities
The system non-idealities, such as leakages and reflections are shown at Fig. 2.5 and Fig. 2.6
for quasi-bi static and the mono-static cases, respectively. The mixer LO-RF leakage is shared
by both architectures. The quasi-bi-static case has only a single additional leakage source
of the TX antenna into the RX. In the mono-static case an additional coupler / circulator
leakage is added and also the reflections from all the discontinuities: Flip-Chip transition,
antenna, radome, bumper. In order to make the discussion more quantitative, the scenario of
leakages and reflections shown at table 2.2 is assumed. PLO is assumed to be +4 dBm and
PTX = +15 dBm. The quasi-bi-static non-idealities are of higher order as compared to the
mono-static case:
in the mono-static case the mixer isolation has a secondary effect on the overall system,
since the power applied to mixer LO is an order of magnitude less than the TX power
leaking through the coupler and reflected from 4 discontinuities
TX-RX antenna leakage doesn’t lend itself for easy modeling, since the leakage depends
on the specific antenna and radome realization, antenna radiation curve and side-lobes
suppression, antennas’ physical separation and the specific enclosure environment (the
15
Automotive LRR FMCW Radar – System Level Approach
reflections from bumper are also hard to model since they cannot be anymore approxi-
mated by a single reflection orthogonal to bumper plane).
Table 2.2: Fig. 2.6 Blockers’ Parameters
Contributors [dB] Delay [mm] IF [Hz]
Leakages (Isolation) Mixer (LO to RF) -30 0.1 0.67
Coupler / Isolator -30 0.3 2
Reflections (Return Loss)
Flip Chip -20 0.5 3.33
Antenna -20 10 66.67
Radome -20 50 333.33
Bumper -20 100 666.67
The blockers’ effects will be analyzed as applied to the mono-static case and the quasi-bi-
static case (which could be approximated as a private case of mono-static arrangement) will
be inferred from it.
LO Source PA
Front-End
Coupler
IFout
LO Buffers
LOin RFin
Mixer LO-RF TX-RX
TX Radome Bumper
Leakage
leak. Target
refl.
TX Antenna
RX Antenna
Antenna
RX Radome
Figure 2.5: Leakages and Reflections in Quasi-Bi-static Automotive FMCW Radar
Noise Floor with Blockers Present
The blockers in conjunction with realistic phase noise profile of the TX VCO introduce a
potential problem (Fig. 2.7). The leaking/reflected TX phase noise “skirt” is introduced,
obscuring the targets’ return signatures which are further away and/or having small RCS or,
at least, reducing the SNR.
Range Correlation Effect – IF Phase Noise Improvement In a presence of a blocker the
equivalent transfer function H(f) translates the transmitted phase noise spectral density to
16
Leakages and Reflections in FMCW Radar
LO Source PA
Front-End
Circulator
Coupler
IFout
LO Buffers
LOin RFin
Mixer LO-RF
Circulator
Flip-Chip
Antenna
Radome
Radome Bumper
refl.
refl.
refl. Bumper
refl.
leak.
leak.
Target
refl.
Figure 2.6: Leakages and Reflections in Mono-static Automotive FMCW Radar
RX Signal
Noise Floor
IF [Hz]
Power [dBm]
Blocker
Figure 2.7: Target Masking by Blocker Phase Noise Profile
IF:
SIF(f) = STX(f)H(f)
2[W/Hz] (2.13)
In logarithmic scale:
SIF(f) = STX(f) + 10 log H(f)
2[dBm
/Hz] (2.14)
STX(f) and SIF(f) are the transmitted and the resulting IF phase noise spectral densities,
respectively. For a single blocker, the transfer function reads:
H(f)=1−e−j2πfTdelay (2.15)
where dleakage / reflection path is the physical length of the reflection path and the equivalent
one-way length of the leakage path, respectively:
Tdelay =2dleakage / reflection path
c0
[s] (2.16)
H(f)
2= 21−cos(2πfTdelay)(2.17)
17
Automotive LRR FMCW Radar – System Level Approach
Substituting equation 2.17 in equation 2.14 yields
SIF(f) = STX(f) + 10 log 21−cos(2πfTdelay)[dBm
/Hz] (2.18)
Keeping in mind that:
sin2α
2=1
21−cos α(2.19)
The approximation in equation 2.20 holds for small αvalues, which is the case here (only the
first term of the Taylor series):
1−cos α= 2 sin2α
2≈2·α2
22=α2
2(2.20)
Further substitution of equation 2.20 in equation 2.18 yields
SIF(f)≈STX(f) + 20 log(2πfTdelay) [dBm
/Hz] (2.21)
The effect shown in equation 2.21 is called “Range Correlation”: for small 2πfTdelay there is a
significant suppression of TX phase noise sidebands at the IF. TX phase noise passes through
a high pass filter with a slope of +20dB
decade . The amount of correlation (and thus noise
filtering) depends upon the range of clutter being illuminated, i.e. the time delay between
the transmitted and received signal. Specifically, the correlation and amount of filtering is
large at short ranges and becomes smaller as the range increases [11]. This effect reduces the
detrimental effect of target masking shown at Fig. 2.7 and enables homodyne FMCW detection
using available signal sources in presence of front-end leakages and reflections. Amplitude
noise is significantly lower than phase noise [12] (more than 25 dB below) and therefore can
be neglected.
In order to numerically evaluate the resulting IF phase noise power density spectrum a TX
phase noise power density spectrum is needed. Reference [45] report on free-running and
phase-locked VCOs in 0.18 µm SiGe for 77 GHz automotive FMCW radar. The reported
phase noise at 100 kHz offset is −77 dBc
Hz and −102 dBc
Hz for the free-running and the locked
cases, respectively.1The phase-locked VCO phase noise, as expected, is better at frequencies
below PLL loop bandwidth (≈1 MHz), where the superior phase noise of the reference crystal
dominates.
Both phase noise characteristics from [45] and the resulting IF phase noise spectrum from
blockers (table 2.2, equation 2.21) are shown on Fig. 2.8 and 2.9. The free-running VCO phase
noise has slope of ≈ −20dB
decade (Fig. 2.8), after being converted to IF the free-running phase
noise profile flattens. In the phase-locked case the TX phase noise plateaus from 10 kHz until
1 MHz so at the IF (Fig. 2.9) the phase noise assumes the ≈+20dB
decade slope. Both figures
and equation 2.21 indicate that the TX phase noise is suppressed the most for the closest
blockers, while even for the furthest blockers (1.33 MHz) the phase noise improvement is circa
45 dB.
1[87] mention −75dBc
Hz at 100 kHz offset in a phase-locked state, which is product-oriented design accounting
also for temperature variation, process and voltage spread.
18
Leakages and Reflections in FMCW Radar
103104105106107
−240
−200
−160
−120
−80
−40
0
frequency offset [Hz]
Phase Noise hdBc
Hz i
TX
IF (mixer LO - RF leakage)
IF (coupler leakage)
IF (Flip Chip transition reflection)
IF (antenna reflection)
IF (radome reflection)
IF (bumper reflection)
Figure 2.8: IF Phase Noise: Range Correlation Effect on the Free-Running TX
103104105106107
−240
−200
−160
−120
−80
−40
frequency offset [Hz]
Phase Noise hdBc
Hz i
TX
IF (mixer LO - RF leakage)
IF (coupler leakage)
IF (Flip Chip transition reflection)
IF (antenna reflection)
IF (radome reflection)
IF (bumper reflection)
Figure 2.9: IF Phase Noise: Range Correlation Effect on the Phase Locked TX
Noise Floor Power Contributors’ Breakdown The thermal noise floor power at the IF reads
(logarithmic notation is more convenient and thus is preferred here):
Pthermal noise(f) = −174 + NFSSB + 10 log(1/Tsw) [dBm] (2.22)
The last term in equation 2.22 is the equivalent noise bandwidth due to sweep time in FMCW
radar. The longer is the sweep duration, the narrower is the noise bandwidth so less noise
power enters the receiver. For Tsw = 1 ms and NFSSB = 16 dB one obtains thermal noise floor
19
Automotive LRR FMCW Radar – System Level Approach
of −128 dBm. Blockers’ powers:
Pmixer leakage(f) = PLO + Isolationmixer +SIF(f) + 10 log(1/Tsw) [dBm] (2.23)
In all of the blocker equations the term SIF(f) assumes appropriate Tdelay. Unlike the rest of
the blocker cases in the mixer isolation case (equation 2.23) PLO is used.
Pcoupler leakage(f) = PTX + Isolationcoupler +SIF(f) + 10 log(1/Tsw) [dBm] (2.24)
Prefl(f) = PTX + RL + SIF(f) + 10 log(1/Tsw) [dBm] (2.25)
Equation 2.25 for the reflected scenario is applied to 4 cases: Flip-Chip, Antenna, Radome and
Bumper (RL stands for return loss).
Ideally, for the blockers not to affect the sensitivity of the front-end (limited by its NFSSB)
each of the blockers has to be significantly below the thermal noise floor (10 dB is taken as a
safety margin):
Pleakage / refl(f)≤Pthermal noise(f)−10 [dBm] (2.26)
As it is evident from Fig. 2.10 and Fig. 2.11 the condition in equation 2.26 is satisfied for all
blockers apart of radome and bumper reflections (in the phase locked case the blocker noise
floor rises with the frequency at 1 MHz offset due to the typical PLL phase noise hump around
the loop bandwidth). Therefore, in a mono-static arrangement the sensitivity is limited by
the blockers (and not by the front-end noise figure, as usual), despite the range-correlation
benefits. From practical point of view, Fig. 2.11 indicates that the mono-static system is still
applicable for targets up to 200 m, but range accuracy reading for maximal ranges will be
degraded (since it is a function of SNR), which is acceptable for distant targets. For targets
closer than 100 m as Fig. 2.11 shows the thermal noise dominates.
Analysis of Blockers Passing through a Non-linear Transfer Function
As explained in section 2.2 the multi-tone excitation, consisting of several blockers and the
target return is applied to a nonlinear front end, creating and enhancing the previously non-
existing frequency components, both in and out of the IF band of interest (0.033 . . . 1.333 MHz).
The same reflections/leakages scenario as outlined in subsection 2.2.3 is assumed, see Fig. 2.6.
The 3rd order intermodulation products resulting from 2 blockers alone could be calculated
using the common 2-tone Intermodulation Distortion (IMD) calculation [78], [55]:
iIPn = Pin +IMD
n−1[dBm] (2.27)
iIP3 = Pin +IMD
2[dBm]
(2.28)
20
Leakages and Reflections in FMCW Radar
103104105106107
−200
−180
−160
−140
−120
−100
frequency offset [Hz]
Power [dBm]
Thermal Noise
Mixer LO-RF Leakage Noise
Coupler Leakage Noise
Flip-Chip Transition Reflection Noise
Antenna Reflection Noise
Radome Reflection Noise
Bumper Reflection Noise
RX Signal
Figure 2.10: IF Noise Floor Contributors – Free-Running TX
103104105106107
−240
−220
−200
−180
−160
−140
−120
−100
frequency offset [Hz]
Power [dBm]
Thermal Noise
Mixer LO-RF Leakage Noise
Coupler Leakage Noise
Flip-Chip Transition Reflection Noise
Antenna Reflection Noise
Radome Reflection Noise
Bumper Reflection Noise
RX Signal
Figure 2.11: IF Noise Floor Contributors – Phase Locked TX
Thus, for an IP3 of 0 dBm and −5 dBm of input power one obtains IMD of 10 dB. This means
that the resulting IMD products will be 10 dB below the carrier, which is the −15 dBm leakage
in this case, or 100 dB above the weakest target return of −115 dBm. The spectral regrowth
is harsh despite state-of-the-art linearity of the front-end deployed (iP1dB= −10 [dBm]).1
The main goals of this part are:
numerically investigate several multi-tone blocker and signal combination scenarios for
1In this text it is assumed iIP3 ≈iP1dB + 10 [dBm], [78].
21
Automotive LRR FMCW Radar – System Level Approach
various front-end linearity values
assess the extent of applicability of either mono-static and/or quasi-bi-static architectures
in presence of blockers
Non-linear Transfer Function Description with System-Level Parameters Large signal sim-
ulation with a specific circuit-level implementation would yield results only at a certain linearity
parameters’ set values and will be valid only for that circuit implementation. In order not to
lose generality the large signal performance was investigated using a behavioral model. Two
assumptions are made for front-end behavioral modeling:
frequency conversion and RF-path non-linearity can be treated separately
frequency conversion can be approximated as an ideal conversion from the carrier fre-
quency to IF
(Both assumptions are valid for low-IF frequency converters, such as this case). Therefore
the front-end performance under multi-tone excitation, its harmonics and intermodulations
were simulated at IF frequency only [36] (as opposed to several combinations of RF and LO
frequencies, their harmonics and intermodulations). This results in faster simulation times and
lower memory requirements. A generic non-linearity was deployed to model the front-end by
explicitly specifying front-end IP2 and IP3 values as shown in Fig. 2.12.1
P = PTX+RLRADOME=-5 dBm
f = IFRADOME=333.33 Hz
P = PRX_no2=-115 dBm
f = IFRX_no2=1.333 MHz
P_1Tone
P_1Tone
Ideal
Passive
Power
Combiner 3 dB
Amp Front-End
TOI=iIP3
SOI=iIP2
G=1
NFSSB=16 dB
IF
Figure 2.12: Front-End Linearity Case Study
1 Set-Up: A Weak RX Signal in Presence of a
Single-Tone Jammer
In the small signal regime the front-end transfer function from RF to IF port can be approxi-
mated by a simple polynomial of 3rd order:
y≈a0+a1x1+a2x2+a3x3(2.29)
where xis the RF input voltage, y– the approximated IF output voltage, a0– the DC output
voltage (circa 0.8 V), a1= 1 is the voltage gain. Here a similar approach to noise 2-port
representation is taken: the front-end is represented as a cascade of non-linearity (with unity
1Amplifier2 and Mixer2, available in the ADS circuit simulator system library.
22
Leakages and Reflections in FMCW Radar
gain) and of linear gain stage with a proper gain value. The latter, linear gain stage adds no
information to this description, so is omitted; and the unity gain of the chosen representation
would ease comparison of the multi-tone input to “jammed” output. Evaluating 2.29, one can
show that [55]:
iIP2 = 20 log a1
a2[dB] (2.30)
iIP3 = 20 log r4a1
3a3[dB] (2.31)
Therefore, a normalized small-signal non-linearity can be approximated by 2 main linearity
specifications: IP2 and IP3. Harmonic balance simulation engine re-calculates the polynomial
coefficients as function of the input signal, since from certain drive level a1value would de-
crease due to compression.1Harmonic balance simulations were performed with the following
settings:
Order: the blockers were simulated up to 3rd order (large non-linearities) and the signals
were simulated up to 2nd order (weak non-linearities)
MaxOrder = 3: MaxOrder is the maximal order of the intermodulation terms assumed
in the simulation. The value of 3 accounts for both IP2- and IP3- related effects (2nd and
3rd intermodulation orders, respectively). Higher MaxOrder values were not considered
due to both exponential increase in simulation time and for avoiding unnecessary clutter
in the results
A multi-dimensional sweep of various setup and system parameters was performed:
2 different targets/blockers scenarios were considered
1. Single 200 m target, single −5 dBm blocker
2. Single 200 m target, two (−5 dBm each) blockers
front-end iIP3
1. upper bound from realization point of view (iIP3= +20 dBm)
2. high-linearity front-end (iIP3= 0 dBm)([97], this work)
3. low-linearity front-end (iIP3= −20 dBm) ([46], [106], [3], [73])
front-end iIP2
1. upper bound from realization point of view (iIP2= +60 dBm)
2. good (iIP2= +40 dBm)
3. low (iIP2= +20 dBm)
1This happens due to the spectral components caused by a3x3at the signal frequency.
23
Automotive LRR FMCW Radar – System Level Approach
IP3 Sweep
Case Study
1: A Weak RX Signal in Presence of a Single-Tone Jammer Simulation
setup is shown on Fig. 2.12: a single target at 200 m (1.333 MHz), single −5 dBm blocker
(333 Hz)
Fig. 2.13a shows the full IF signal spectrum, from DC to 8th harmonic of the fundamental
tone. The figure will be used to assess various front-ends’ responses to the blocker and its
harmonics:
102103104105106107
−160
−120
−80
−40
0
IF [Hz]
Power [dBm]
Blocker
RX Signal
iIP3 = +20 dBm
iIP3 = 0 dBm
iIP3 = −20 dBm
(a) 1 Target, 1 Blocker
102103104105106107
−160
−120
−80
−40
0
IF [Hz]
Power [dBm]
Blockers
RX Signal
iIP3 = +20 dBm
iIP3 = 0 dBm
iIP3 = −20 dBm
(b) 1 Target, 2 Blockers
Figure 2.13: Various Targets/Blockers Scenario: IP3 swept, iIP2 = +40 dBm
In theoretical case the fundamental is correctly registered; the higher harmonics are more
than 50 dBc down
In the high-linearity case the fundamental is compressed by 3 dBc; the 2nd harmonic is
49 dBc down (relative to fundamental) and the 3rd harmonic is 17 dBc down (relative to
fundamental)
In the low-linearity case the fundamental is compressed by 22 dBc; the 2nd harmonic is
89 dBc down (relative to fundamental), the 3rd harmonic is 10 dBc down (relative to
fundamental)
The theoretical and high-linearity front-ends are coping adequately with the blocker alone,
with the low-linearity front-end saturated already.
Since the blocker is between the DC and the IF band, it is possible to filter it out (and its
harmonics) using a band pass filter at IF (either in HW or SW).1The intermodulation products
of the weak signal (and its higher harmonics) with strong blocker fundamental (and its higher
harmonics) are within the IF BW.
1The blocker and its harmonics were investigated in order to gain fuller understanding of energy spectral
regrowth.
24
Leakages and Reflections in FMCW Radar
Fig. 2.14a shows an overview of the target signal in the IF band for various front-ends:
1.33 1.33 1.34 1.34 1.34
·106
−160
−140
−120
−100
−80
−60
−40
−20
0
20
IF [Hz]
Power [dBm]
Thermal Noise
RX Signal
iIP3 = +20 dBm
iIP3 = 0 dBm
iIP3 = −20 dBm
(a) 1 Target, 1 Blocker
1.33 1.33 1.34 1.34 1.34
·106
−160
−140
−120
−100
−80
−60
−40
−20
0
20
IF [Hz]
Power [dBm]
Thermal Noise
RX Signal
iIP3 = +20 dBm
iIP3 = 0 dBm
iIP3 = −20 dBm
(b) 1 Target, 2 Blockers
Figure 2.14: Various Targets/Blockers Scenario: IP3 swept, iIP2 = +40 dBm; Zoomed to IF
In the theoretical case: the signal is correctly registered (−115 dBm)
In the high-linearity case: the reading is enhanced by 39 dBc
In the low-linearity case: the reading is enhanced by 66 dBc
The intermodulation between the blocker, its harmonics and the signal is the source for the
spectral regrowth around the target. These intermodulations are present in the high linearity
case and are quite strong in low linearity case. The theoretical front-end has a performance
edge in this case (vs. high linearity front-end), while low linearity front-end has the worst
performance.
Case Study
2: A Weak RX Signal in Presence of Two Jammers Simulation setup is
shown in Fig. 2.15: a single target at 200 m (1.333 MHz), two −5 dBm blockers (at 333 Hz
and 667 Hz):
Fig. 2.13b shows an overview of the blocker and its harmonics: the situation is similar to
blocker in Case Studies
1. The main differences are that more frequency components
are present here due to intermodulations between the blockers and that the blockers here
are slightly more compressed. Additionally, the intermodulations worsen due to doubling of
blocker power. Fundamental blocker harmonic compression and intermodulations worsen with
front-end linearity decrease.
Fig. 2.14b shows an overview of the signal, its harmonics and its intermodulations with the
blockers in the IF band:
In the theoretical case: the dominating component in signal fundamental vicinity is
60 dBc up (relative to the original signal power); 2nd harmonic vicinity regrowth is below
the noise floor
25
Automotive LRR FMCW Radar – System Level Approach
P = PTX+RLRADOME=-5 dBm
f = IFRADOME=333.33 Hz
P_1Tone
P_1Tone
Ideal
Passive
Power
Combiner 4.77 dB
Amp Front-End
TOI=iIP3
SOI=iIP2
G=1
NFSSB=16 dB
IF
P = PRX_no2=-115 dBm
f = IFRX_no2=1.333 MHz
P_1Tone
P = PTX+RLBUMPER=-5 dBm
f = IFBUMPER=666.67 Hz
Figure 2.15: Front-End Linearity Case Study
3 Set-Up: Weak RX Signal in Presence of Two
Jammers
In the high-linearity case: the dominant component in signal fundamental vicinity is
91 dBc up relative to the original fundamental power, 2nd harmonic vicinity regrowth is
37 dBc down (relative to dominating component in fundamental vicinity)
In the low-linearity case: the dominant component in signal fundamental vicinity is
74 dBc up relative to the original fundamental power, 2nd harmonic vicinity regrowth is
33 dBc down (relative to dominant component in fundamental vicinity)
While the blocker situation here resembles the one predicted in Case Study
1, the situation
at higher frequencies is worse. Even the theoretical front-end is not sufficent – the intermodu-
lations are 60 dBc higher than the signal (the high-linearity front-end yields intermodulations
90 dBc above the signal). Interestingly, the low-linearity front end seems to be more linear
than the high-linearity front-end due to lower intermodulations around the signal. This is mis-
leading, since due to both blockers most of the energy is spread around the DC and thus there
is less power available in the vicinity of the signal. Additionally, the low-linearity front-end
is so deep into saturation that the intermodulations cannot grow with an additional blocker
anymore. As a result, the power is spread over a wider bandwidth (as compared to a single
blocker case, Fig. 2.13a).
IP2 Sweep It is useful to have a measure indicating which of the two mechanisms (IP2 or
IP3) limit the front-end performance in given blocking conditions [82]:
Pcorner blocker = 2iIP3−iIP2[dBm] (2.32)
below Pcorner blocker the front-end is IP2-limited and above Pcorner blocker – IP3-limited (Fig. 2.16).
The highest Pcorner blocker result from a front-end having high IP3 and low IP2: assuming
26
Leakages and Reflections in FMCW Radar
iIP3= 0 dBm and iIP2= +20 dBm Pcorner blocker of −40 dBm is obtained. This is still below
all of the blockers considered here, so according to the calculation the front-end is clearly IP3-
limited. Fig. 2.17 shows the most of the spectral components coincide regardless of system
adequate
IP
2in the mixer.
It is useful to determine bounds on the necessary values
of
IP
2and
IP
3in cognitive radios. A plausible approach
is to assume the intermodulation components resulting from
second-andthird-ordernonlinearityhaveequal magnitudesfor
a certain input level in a two-tone test [Fig. 5(a)]. Denoting
f
f
1
f
2
f
2−
f
1
f
2
f
1
+
P
int
P
IM
f
2−
f
1
2
f
−
f
212
P
∆
1
2
3
P
int
IP IP
Fundamental
IM
2
IM
3
P
in
32
P
IM
(a)
(b)
Fig. 5. (a) Input power level producing equal IM2and IM3products, (b)
illustration of IM2-limited and IM3-limited regions.
thislevel by
P
int
and expressing thequantitiesin dB and dBm,
we have ∆
P
=
P
int
,
P
IM
and
∆
P
+
P
int
=
IP
2(13)
∆
P
2
+
P
int
=
IP
3
:
(14)
Thus,
2
P
int
,
P
IM
=
IP
2(15)
3
P
int
,
P
IM
=
2
IP
3
:
(16)
That is,
P
int
=
2
IP
3
,
IP
2
:
(
17
)
For example, if
IP
3
=
,
5dBmand
IP
2
=+
30 dBm, then
P
int
=
,
40 dBm; i.e., the system tends to be
IM
2-limited
for interferers below this level and
IM
3-limited for interferers
above this level [Fig. 5(b)].
As with SDRs, the downconversion and upconversion mix-
ing in cognitive radios must deal with the LO harmonics. As
shown in Fig. 6(a) for the receivepath,the harmonics of theLO
canmixwithinterferers,corrupting thedownconverteddesired
signal. Unlike SDRs, however, the decades-wide bandwidth
of cognitive radios makes high-order LO harmonics still criti-
cal. For example, an SDR operating in the range of 900 MHz
to 5 GHz need deal with harmonics up to the fifth or sixth
order whereas a CR accommodating the range of 100 MHz to
10 GHz must handle harmonics up to the 100-th order!
Recent work on SDRs has focused on harmonic-rejection
mixers [9, 10] derived from the original concept in [11]. Il-
lustrated in Fig. 6(b), the idea is to mix the RF signal with
f
Desired
Channel
f
f
LO
f
LO
2
f
LO
3
Received
Spectrum
Spectrum
LO
(
(
t
1
g
(
(
tg
2
(
(
tg
3
(
(
tx
(
(
ty
2
t
(
(
t
1
g
(
tg
(
(
tg
3
(
2
−1
+1
(a)
(b)
Fig. 6. (a) Effect of LO harmonics in a broadband receiver, (b) harmonic-
rejection mixing.
multiple phases of the LO,
g
1
(
t
)
-
g
3
(
t
)
, and sum the results
with proper weighting so as to cancel the effect of the third
and fifth harmonics. It can be shown that if
x
(
t
)
g
2
(
t
)
is scaled
by a factor of
p
2 with respect to
x
(
t
)
g
1
(
t
)
and
x
(
t
)
g
3
(
t
)
,then
these harmonics are removed [11]. With typical mismatches,
the effect of the harmonics is reduced by 30 to 40 dB.
If applied to cognitive radios, harmonic-rejection mixing
faces several critical issues. First, even for third and fifth
harmonics, it requires the generation and distribution of eight
LO phases, a difficult task as the LO frequency reaches a
few gigahertz (the maximum LO frequency whose harmonics
prove troublesome). Second, harmonic mixing becomes very
complex if harmonics of seventh and higher orders must be
rejected. Third, this technique does not remove even LO har-
monics that result from random asymmetries in the mixers or
LO waveforms. Consider, for example, the single-balanced
mixer shown in Fig. 7(a), with
V
OS
modeling the
V
GS
mis-
match between
M
2and
M
3. As illustrated in Fig. 7(b), the
resulting vertical shift in the LO waveform equivalently dis-
torts the duty cycle of the switching of
M
2and
M
3. It can be
shown that the second LO harmonic arising from this effect
has a peak amplitude of
V
2
LO
V
LO
4
V
OS
V
LO
;
(
18
)
4
Figure 2.16: IP2 vs. IP3: the limiting Non-linearity Mechanism as Function of the Blocker
Power [82]
102103104105106107
−160
−120
−80
−40
0
IF [Hz]
Power [dBm]
Blocker
RX Signal
iIP2 = +60 dBm
iIP2 = +40 dBm
iIP2 = +20 dBm
(a) 1 Target, 1 Blocker
102103104105106107
−160
−120
−80
−40
0
IF [Hz]
Power [dBm]
Blockers
RX Signal
iIP2 = +60 dBm
iIP2 = +40 dBm
iIP2 = +20 dBm
(b) 1 Target, 2 Blockers
Figure 2.17: Various Targets/Blockers Scenario: IP2 swept, iIP3 = 0 dBm
IP2 rating (the performance differs at even mixing indices, where the intermodulation products
are lower than those at the odd indices). Therefore the simulations also support equation 2.32:
under given conditions IP3 (and not IP2) is the limiting parameter for FMCW operation with
blockers.
27
Automotive LRR FMCW Radar – System Level Approach
2.2.4 Conclusions
Sharing of the same antenna between radar RX and TX (the so-called mono-static arrange-
ment) is challenging due to the lack of RX-TX time domain multiplexing (inherent to FMCW
radar principles). Simulations for two blockers −5 dBm each show that a hypothetical front-
end (which is assumed to have linearity of 20 dB higher than state-of-the-art front ends) exhibit
artifacts masking the target by 60 dBc. Hence in the mono-static case front-end linearity im-
provements are offset by the effects of the blockers. However, the caused spectral regrowth
should allow a basic FMCW ranging functionality. The spectral regrowth range-domain indi-
cations are to be spaced up to 100 mm apart (worst case of the furthest reflection, table 2.2).
Even in case of harsh non-linearity, spectral regrowth amplitude coefficients gradually decrease
in value [66], so one can assume a spectral regrowth band limited to ≈10×the spacing between
the spectral components. This means that a range indication uncertainty would be around
1 m, still acceptable in automotive LRR application.
Additionally, the mono-static arrangement can be facilitated with one/several realizations of
leakage-/reflection- power reduction circuitry ([68], [52], [62], [6]). A combination of those
solutions addresses the drawbacks of the mono-static approach. Thus the aforementioned very
strict front-end requirements are shifted onto leakage-/reflection- reducing circuitry and/or
signal processing complexity.
The 77 GHz LRR front-ends, benchmarked in this work (table 5.4) could be also compared
from applicability to a mono-static case where no leakage cancellers are deployed. While the
low-linearity front-ends (such as [46], [106], [3], [73]) are compressed used in mono-static ar-
rangement, the high-linearity front-ends (such as [97], this work) allow reasonable performance
for targets distanced up to 200 meters, which is in-line with application’s requirements.
28
3 Circuit Environment
3.1 MMIC Process and Transistors
3.1.1 The Process of Choice: SG25H1 by IHP
Unlike other high performance processes, SG25H is a high performance BiCMOS technology
family that is simplified and lacks the technologically complex epitaxially-buried, highly-doped
sub-collectors and deep trench isolation [42]. The bipolar modules of SG25H are integrated into
a 0.25 µm RF CMOS platform that needs 19 lithographic mask steps (SGB25VD). The CMOS
platform offers 2.5 V MOS transistors for digital applications, an isolated NMOS device, an
accumulation-type MOS varactor, a junction varactor. SG25H1 being the highest performance
version of SG25H (the other two are complementary BiCMOS and high breakdown voltage
versions, respectively). The main features of SG25H1 bipolar module are (the cross-section is
shown in Fig. 3.1):
Five masks are needed for the HBT module.
The standard device has reduced dimensions and also lower parasitic capacitances than
the H3 version – a minimum drawn area of 0.18 ×0.84 µm2results in corresponding ft,
fmax values of 180 GHz, 220 GHz.
An ftimprovement compared to H3 version results from novel collector design, which
substantially reduces base-collector charging and transit times. The key device feature
is the formation of the whole HBT structure in one active area, which allows collector
resistance similar to the emitter resistance.
Shallow trench isolation only – the absence of deep trench isolation improves the heat
dissipation and reduces the thermal resistance.
3.1.2 HBT Modeling
The Process Design Kit (PDK) provided VBIC models of the active devices (the equivalent
circuit deployed in the VBIC model is shown in Fig. 3.2). VBIC is a bipolar junction transistor
(BJT) model that was developed as a public domain replacement for the SPICE Gummel-Poon
(SGP) model. VBIC is designed to be as similar as possible to the SGP model, yet overcomes
its major deficiencies. VBIC improvements over SGP are [7]:
Improved Early effect modeling
29
Circuit Environment
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2006 - All rights reserved
„High-Performance“ HBT: X-section
Features of
SG25H1 bipolar module
Only shallow trench
isolation (STI)
HBT integration after gate
module
Uniform active area
Combination of selective
and differential Si/SiGe:C/Si
epitaxy
Drawn emitter area:
0.21x0.84 µm² (npn200)
0.18x0.84 µm² (npn201)
STI
CoSi emitter contact
CoSi base contact
CoSi collector contact
p-Si substrate
30nm boron doped
Si0.8Ge0.2C0.002
poly crystalline SiGe:C
extrinsic base
SiO2
n doped poly
crystalline Si
emitter
SiO2
Trench
SiO2SIC n+
S/D n+
n doped Si collector
2 µm bipolar window
SIC: Selectively implanted collector
S/D: Source/drain implant
Figure 3.1: IHP SG25H1 High-Performance HBT Cross-Section [29]
Quasi-saturation modeling
Parasitic substrate transistor modeling
Parasitic fixed (oxide) capacitance modeling
Includes an avalanche multiplication model
Improved temperature modeling
Base current is decoupled from collector current
Electro-thermal modeling
Smooth, continuous model
3.2 Passive Elements
3.2.1 Stack
Nominal back-end option offers 3 thin metal (Al) layers, a MIM layer and a 2 µm thick metal
(Al) layer. An additional optional 2nd thick 3 µm Al metal layer is deployed – Fig. 3.3) Together
with a high dielectric stack this enables improved RF passive component performance.
30
Passive Elements
J.Berkner, Vers. 26.2.2002
European IC-CAP Device Modeling Workshop,
Berlin, March 7-8, 2002
4
Fig. 2 shows the large signal equivalent circuits and Table 1 compares their components.
SGP VBIC
SB
BI
I
BEI
I
T
Q
SBCI
Q
SBE
R
E
R
C
CI
EI
EC
Substrate
Emitter
Buried Layer
Isolation
R
BB
Base
Epitaxy
Q
DBE
Q
DBC
I
BEN
I
BCI
I
BCN
Q
SBCX
Q
SCS
Isolation
Q
BCO
R
BI
R
BP
SB
Q
BEO
BI I
BE
I
BC
I
T
Q
DBC
+
Q
BCI
Q
BCX
R
E
R
CX
CI
EI
I
RCI
CX
I
BEX
Q
SBEX
Q
SBCP
I
BCP
I
BEP
I
CCP
R
S
SI
Main
Transistor
Collector
Parasitic
Transistor
BX
Q
CSO
BP
EC
Substrate
Emitter
Sinker
Buried Layer
Ext. BE-Junction
Isolation
Isolation
R
BX
Q
XF
I
TZF
R
XF
GND
XF1
L
XF
XF2
Excess Phase
Network
Thermal
Network
Q
CTH
I
TH
R
TH
GND
DT
Epitaxy
Q
DBE
Base
Q
SBE
Q
SBC
Q
DBEP
Q
SBEP
HICUM MEXTRAM
R
TH
Q
TH
I
P
R
BI
SB
Q
EOX
B' I
JBEI
I
JBCI
I
T
Q
JCI
+
Q
DC
Q
RBI
Q
JEI
+
Q
DE
R
E
R
CX
C'
E'
I
JBEP
Q
JEP
Q
DS
I
JSC
I
JBCX
I
TS
R
SU
S'
Haupt-
transistor
Parasitic
Transistor
B*
EC
Substrate
Emitter
Sinker
Buried Layer
Peripheral
BE-Junction
Isolation
Isolation
R
BX
Thermisches Netzwerk
Base
Epitaxy
I
AVL
I
BET
Q
BCX
Q
B*CX
Q
SU
T
J
Q
JS
SB
B2
I
B1
+
I
B2
I
N
Q
EPI
Q
BC
Q
E
R
E
R
CC
C2
E1
I
C1C2
C1
I
B1S
Q
TES
I
SF
I
EX
+
I
B3
XI
SUB
Main
Transistor
Parasitic
Transistor
B1
EC
Substrate
Emitter
Buried Layer
External BE-
Junction
Isolation
R
BC
Thermal Network
Q
TH
I
DISS
R
TH
GND
DT
Base
Epitaxy
Q
BE
I
AVL
Q
TE
Q
TC
Q
B1B2
XI
EX
XQ
TEX
+
XQ
EX
I
SUB
Q
TEX
+
Q
EX
Q
TS
R
B1B2
Q
BEO
Q
BEO
Fig. 2: Large Signal Equivalent Circuits for SGP, VBIC, HICUM and MEXTRAM
Figure 3.2: Equivalent circuit deployed in the VBIC Model [7]
3.2.2 Resistors
The PDK offers 4 polysilicon resistor types with sheet resistances of 7 Ω/, 200 Ω/, 300 Ω/
and 1.6 kΩ/. Where the resistors are placed the M1 is removed and the resistor is interfaced
trough CO and LI layers (Fig. 3.4, CO stands for contact layer, LI – local interconnect layer).
3.2.3 Capacitors
The MIM (Metal-Insulator-Metal) capacitor has its own special layer 58 nm thick with di-
electric constant of εR= 7.3 [44]. MIM area capacitance is 1 fF/µm2. The capacitor model
in the IHP library does not include the parasitic capacitor formed between the bottom MIM
plane and the ground plane. In case of shunt capacitors this is not critical, since the parasitic
31
Circuit Environment
Figure 3.3: IHP SG25H1 Process Cross-Section [44]
capacitor can be lumped with the nominal capacitor value. However, in case a series capacitor
is used the model topology no longer holds. Consequently, large series capacitor values (for
DC de-coupling, for instance) should be used with care because of the large shunt capacitances
to the ground.
There are pros and contras for leaving the ground below series capacitors:
pro: the ground shields from the lossy substrate, so the losses are minimized
contra: the parasitic shunt capacitance between the lower capacitor plate and the ground
is higher than the parasitic shunt capacitance between the lower capacitor plate and the
conductive substrate
pro: more robust and predictable model from circuit designer point of view – no need
to deploy each time the EM simulator to see the effects of the substrate). What is more
important than the parasitics’ absolute value is model fidelity, repeatability, usability
and simplicity. While with the correct circuit design strategy the parasitics could be
deployed as part of the circuit and/or resonated out.
32
Passive Elements
Figure 3.4: IHP SG25H1 Process Cross-Section Detail below M1 [44]
Therefore it was decided not to remove the ground below series capacitors in general. The
Figure 3.5: Series MIM Capacitor Model
shunt capacitor is between M2 and the ground, so the plate distance is 900 nm (as opposed to
58 nm of the MIM), and the shunt capacitor’s dielectric constant is 4.1 (as opposed to 7.3 of
the MIM). Since the MIM and the parasitic capacitor have same area (fringing is neglected),
the shunt capacitor is a scaled version of the MIM:
Cshunt =C
900
58 ·7.3
4.1
=C
27.6[fF] (3.1)
3.2.4 Passivated Microstrip Transmission Line Model
The stack offered by IHP has passivation on top of the 2nd thick metal layer (Fig. 3.3). Due to
the passivation layer a classical microstrip transmission line (its cross section shown at Fig. 3.7)
can not be realized in this process. Deployment of a microstrip transmission line with a pas-
sivation on top (referred to as passivated microstrip transmission line) requires an accurate
model. One option would be developing either a closed-form analytical or empirical dedicated
33
Circuit Environment
physical modes for passivated transmission line. Such models of the classical microstrip trans-
mission line are published in [38], [32], [53], among other references. This dedicated modeling
of passivated line is linked with significant effort, so is not pursued here.
The Selected TL Modeling Approach
The selected option was to build on the mature and robust closed-form models available for the
classical microstrip. One could suggest an equivalent classical microstrip line per each given
passivated transmission line. More specifically, for each passivated line physical width (w) one
could find a parameter set for a classical microstrip that has an equivalent behavior (Fig. 3.7).
These parameters are were narrowed to microstrip width, dielectric constant, conductivity:
wequiv,εr, equiv,κequiv (Fig. 3.6).1Transmission lines of various widths were simulated in a
h=9.16 µm
0.48 µm
passivated line
physical width
3 µm
200 nm
400 nm
1.5 µm
1.5 µm
400 nm
κ=3.3e7 S/m
κ=2.1e7 S/m
εr=4.1
εr=5passivation
SiOx
tan δ = 0.01
Figure 3.6: Passivated Transmission Line Cross-Section
3D EM simulator (CST) and the resulting S-Parameters were fitted by a standard ADS mi-
crostrip model (MLIN). Two fitting approaches were investigated : polynomial and fractional.
Numerical software packages such as MATLAB and Origin were deployed. The models (EM
simulation fitting results) of the 3 parameters and their derivative show monotonic behavior
(Fig. 3.8), which is good indicator when a robust model is needed. For larger w values a clas-
sical microstrip of the same properties is a reasonable fit to the passivated line.2For smaller
w, a narrower, more dielectric and conductive equivalent microstrip represents the passivated
line best.
1εr, equiv and κequiv are functions of the propagation constant γ.
2The microstrip equivalent dielectric constant is an average between stack oxide and the passivation dielectric
constants.
34
Passive Elements
h=9.16 µm
0.48 µm
3 µmκequiv=f(w)
κ=2.1e7 S/m
SiOx
tan δ = 0.01
wequiv=f(w)
εr,equiv=f(w)
Figure 3.7: Equivalent Microstrip Model Cross-Section
Excellent fit of the all 3 parameters allowed a straightforward realization of circuit-level passi-
vated line model kit.
3.2.5 Prober Pads Models
In order to be eventually subtracted the prober pads had to be characterized. For this purpose
3 identical through transmission line sections terminated on both ends by pads (Fig. 3.9)
were measured. The “hot” signal pad has a ground opening at M1 to reduce the shunting
capacitance (so lossy and capacitive substrate and the capacitive oxide are not screened).
The pads were assigned with physical models, which were fitted so that the overall simulated
arrangement agrees with the measurements. The transmission line was modeled using the
developed passivated microstrip library and for the pads 2 physical models are proposed.
Pad Model
1 – RC
An RC pad model was investigated:
Cplumps two capacitors into one: oxide layer capacitor and Si substrate capacitance
Rprepresents Si substrate losses
As the results show (dotted curves on Fig. 3.12), the pad model with the obtained RC values
(table 3.1) predicts the magnitude relatively accurately. The phase accumulation, however, is
not adequately modeled, as it is obvious from Fig. 3.12d. Hence it was concluded that the
suggested RC model topology needs to be amended.
35
Circuit Environment
0 5 10 15 20 25 30 35 40 45 50
0.7
0.75
0.8
0.85
0.9
0.95
Passivated Line Physical Width [µm]
Width Transformation Ratio
model
polynomial fit
fractional fit
(a) Width
0 5 10 15 20 25 30 35 40 45 50
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
Passivated Line Physical Width [µm]
Equivalent Microstrip εr
model
polynomial fit
fractional fit
(b) Dielectric Constant
0 5 10 15 20 25 30 35 40 45 50
3
3.2
3.4
3.6
3.8
4·107
Passivated Line Physical Width [µm]
Eqv. µ-strip Conductivity hSiemens
mi
model
polynomial fit
fractional fit
(c) Conductivity
Figure 3.8: The Equivalent Microstrip Model Parameters as Function of Passivated Line Phys-
ical Width
Table 3.1: RC Pad Model – Values
CpRp
14 fF 366 Ω
Pad Model
2 – RLC
Pad model
1 is a lumped RC model that does not take into account the inductance con-
tributed by the pad. In pad model
2 a more descriptive and distributed approach is taken:
the physical pad center is taken as a reference point for the probing needle placement. The
36
Passive Elements
G
S
G
G
S
G
16.2 µm50 µm
100 µm
100 µm 120 µm
Figure 3.9: Layout Arrangement of 2 Pads and a Through Line
Port 1 Port 2
Cp
Rp
Cp
Rp
120 µm long
16.5 µm wide
Figure 3.10: Pad Model
1 (RC) Schematics
Port 1 Port 2
Cp
Rp
120 µm long
16.5 µm wide
Cshunt
Lseries Lseries
Cp
Rp
Cshunt
Figure 3.11: Pad Model
2 (RLC) Schematics
pad is conceptually divided into 2 halves:
From the center towards the transmission line. Lseries represents the inductive effect of
this pad section
From the center to the pad edge. This pad section is modeled as an additional shunt
cap Cshunt since it is floating (the parasitic shunt capacitances of Lseries are absorbed in
37
Circuit Environment
Cshunt)
All the complex S-Parameters are accurately predicted until 110 GHz by the slightly more
complicated pad model
2, including the phase accumulation (Lseries is mostly responsible for
that). Cpand Rpare kept as in pad model
1, and they are complemented by a commensurate
Cshunt with Cp(table 3.2).
Table 3.2: RLC Pad Model – Values
Cshunt CpRpLseries
10 fF 14 fF 366 Ω 29 pH
(a) Return Loss, amplitude (b) Reflection, degrees
(c) Transmission Loss, amplitude (d) Transmission, degrees
Figure 3.12: Validation of the 2 Pads’ Models Deploying Through Line Measurements
38
4 Design of Circuits
4.1 LNA
The standard low-frequency (fcenter <fmax
10 ) receiver design approach is designing the LNA
to have low noise figure and high gain (circa 15 dB and above). Thus the noise contribu-
tions of the following mixer and IF stages would be suppressed. At lower frequencies the
overall linearity would still be acceptable because at lower frequencies the nominal linearity is
higher. At high frequencies the active device maximal achievable gain, NFmin and achievable
linearity deteriorate. Therefore the approach to LNA design at high frequencies should be
reconsidered.
4.1.1 Main Requirements imposed on the LNA
Noise Figure. According to Friis [78]:
Ftotal =F1+F2−1
G1
+F3−1
G1·G2
+··· (4.1)
so the 1st front-end noise block contribution is the most critical, since it is not scaled by
the gain of the preceding stages. Therefore NF of the LNA should be minimized.
Gain. One one hand, as equation 4.1 shows, the high LNA gain would better suppress
the noise contributions from the mixer and IF circuitry. On the other hand, high gain
is linked to LNA iP1dB penalty. Therefore a certain optimum in gain is to be found,
per given technology, operating frequency, overall front-end linearity, gain and sensitivity
specifications. Additionally, since the overall front-end gain cannot be high (otherwise
the analog-to-digital converter might be saturated) the LNA with low-mid gain could be
a fitting candidate in this challenging case.
Linearity. The LNA linearity should be sufficiently high not to degrade the RX linearity
directly in the first stage.
Other LNA requirements include the required passband bandwidth:
1 GHz /77 GHz = 1.3 % is translated into a stricter requirement of 15 dB-return-loss BW
higher than 15 % to allow for robustness in terms of design centering, process variations,
etc.
39
Design of Circuits
4.1.2 Transistor Sizing
As it was shown in chapter 2, RX linearity is of importance when it comes to blocking perfor-
mance. The linearity improves with transistor size, while a too big transistor could introduce
parasitics which, in their turn, could theoretically reduce the gain. Practically speaking, latter
applies to a power amplifier, which is normally biased at higher current densities and has a
significantly larger area (compared to an LNA). Therefore, the largest transistor available in
the design kit (npn201 8) was used. For layout simplicity and lower risk no multiple transistor-
combining structures were used.
4.1.3 LNA Topology Selection
The LNA various topologies were evaluated both qualitatively and quantitatively with sup-
porting circuit simulations for each using the foundry-supplied PDK (Fig. 4.5, 4.6, 4.7). The
following topology solution space for an HBT LNA at fmax
2.6was checked:
1. Single cascode stage (Fig. 4.1):
IN Q1
OUT
Q2
Vcc
Vref
Figure 4.1: Cascode LNA
good gain (due to deployment of more than one stage and to common emitter stage
Miller effect mitigation [81])
high noise figure (due to additional NF contribution of common base stage and only
circa 5 dB gain of the preceding common emitter stage (equation 4.1)
mediocre linearity (due to transistor stacking)
good input match (wide enough in terms of fractional bandwidth)
narrow-band out match (due to high output resistance typical for common base
topology) [34]
40
LNA
good isolation (due to reduction of the detrimental effect caused by common-emitter
Miller capacitance by the low input impedance common base stage) [81]
2. Single common emitter (CE) stage (Fig. 4.2):
IN
OUT
Q1
Vcc
Figure 4.2: Common-Emitter LNA
low-to-mediocre gain. At the aforementioned operational frequencies the common
emitter MSG (Maximal Stable Gain, [33]) at current density corresponding to fmax
is (using dominant pole approximation):
20 log fmax
foperation != 20 log 200 GHz
77 GHz = 8.3 dB (4.2)
At the selected current density, which is traded-off for noise, the MSG would be
circa 2 dB lower and subtracting the 1 dB losses per IO matching networks one
ends up with circa 4 dB of gain)
noise figure – better than cascode (a single active device has less noise then two
active devices)
good linearity.
good input/output match (wide enough in terms of fractional bandwidth)
acceptable isolation (due to the undesired feedback caused by the Cbc capacitance)
3. Single common base stage (Fig. 4.3):
good gain, better than in a single common emitter stage (in [80] it is shown that MSG
of the common-base configuration is superior to common-emitter for operational
frequencies in the following range: fmax
10 < f < fmax
best noise figure among the presented variants
low linearity
good input match (wide enough in terms of fractional bandwidth)
narrow-band out match (due to high output resistance typical for common base
topology)
41
Design of Circuits
IN OUT
Q1
Vcc
Vref
Figure 4.3: Common-Base LNA
isolation slightly higher than in CE case (since the dominant capacitor Cbc is no
longer in the feedback but shunts the output, so can be resonated out by output
matching network)
4. Cascade of 2 common emitter stages [19] (Fig. 4.3):
IN Q1
Vcc
OUT
Q2
Vcc
Figure 4.4: 2 Common-Emitter Cascade LNA
good gain (roughly doubling of single CE stage gain)
noise figure – similar to cascode
linearity – 2nd best after single CE stage (if for both of the CE stages are biased at
same current density roughly equal to single CE stage linearity minus its gain)
good input/output match (wide enough in terms of fractional bandwidth)
good isolation (better than in a single stage case)
Any of the fore-mentioned solutions can be complemented by positive feedback, for example
in the common-base case an inductor can be added to the base. This increases the MAG
42
LNA
(Maximal Available Gain, [33]) at the expense of the stability. Due to the risk involved, it
was decided to drop this approach. Both cascode and cascade of 2 CE have worse NF than
0 10 20 30 40 50 60 70 80 90 100110
−50
−40
−30
−20
−10
0
frequency [GHz]
S11 [dB]
CE-CB
CE
CB
CE-CE
(a)
0 10 20 30 40 50 60 70 80 90 100110
−50
−40
−30
−20
−10
0
frequency [GHz]
S22 [dB]
CE-CB
CE
CB
CE-CE
(b)
Figure 4.5: LNA Topologies Overview: In- and Out- Return Loss
40 50 60 70 80 90 100 110
−6
−4
−2
0
2
4
6
8
10
12
frequency [GHz]
S21 [dB]
(a)
0 10 20 30 40 50 60 70 80 90 100110
−80
−70
−60
−50
−40
−30
−20
−10
0
frequency [GHz]
S12 [dB]
CE-CB
CE
CB
CE-CE
(b)
Figure 4.6: LNA Topologies Overview: Gain and Isolation
single-stage solutions.
It is not easy comparing CB and CE noise figure alone: since they have different gains, so not
only their noise figures are weighted by different factors in a system noise figure / temperature
cascade calculation but also the following mixer NF is of importance. Nevertheless, the CE
NF is 2nd best, so it seems like an acceptable design tradeoff. In terms of I/O return-loss
bandwidth CE is the optimal topology (for the I/O impedance transformation ratio is not
high).
Despite an attractive NF, the CB arrangement has worse linearity (compared to CE) so it was
decided not to employ it as the LNA. Gain-wise the CE stage is in-line with the requirements.
Hence a single common emitter stage topology was adopted.
43
Design of Circuits
0 10 20 30 40 50 60 70 80 90 100110
0
2
4
6
8
10
12
14
16
18
20
frequency [GHz]
Noise Figure [dB]
CE-CB
CE
CB
CE-CE
(a)
0 10 20 30 40 50 60 70 80 90 100110
100
101
102
frequency [GHz]
Rollett Factor
CE-CB
CE
CB
CE-CE
(b)
Figure 4.7: LNA Topologies Overview: Noise Figure and Stability
When a differential LNA is deployed conceptually a Miller compensation (also known as neu-
tralization or unilaterization) [58], [37] is possible. Due to the differential arrangement if the
anti-phase voltage is sampled and fed to the in-phase base deploying an external capacitor
CNequal to the Miller capacitance Cbc then by symmetry there is no net feedback from the
base to the collector and thus it is theoretically possible to improve the MAG. This approach
was not deployed since CNhas to match Cbc precisely. In HBTs, unfortunately Cbc is volt-
age dependent, so imperfect neutralization is to be expected (vacuum tubes were much better
candidates for use with this technique with their constant capacitances).
4.1.4 Bias Point Selection
For every active device a certain quiescent current (Ice,q) at a certain operating voltage (Vcc)
have to be set.
Vcc value selection
The voltage limit is dictated by avalanche multiplication, which is represented by a parasitic
current source from base to collector [85]. For simplicity avalanche multiplication current is
combined with the intrinsic base collector current; together they are denoted as Ibc in the
VBIC model (Fig. 3.2). In terms of breakdown voltage BVceo (collector-emitter breakdown
voltage while the base is held open) is the worst case. In CE forced Ibe case the effective
external resistance (rb, ext) seen from the base is high so the positive feedback to the avalanche
multiplication case is equivalent to open base case for which BVceo is defined. In this process
BVceo= 1.85 V. The Vcc is chosen to be slightly below BVceo, so Vcc= 1.6 V.
44
LNA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
4
5
6
7
8
Ice [mA]
[dB]
MAG
NFmin
LNA bias
Figure 4.8: Maximal Available Gain and NFmin vs. Bias Current for CE Topology
Ice,q value selection
In Fig. 4.8 the NFmin and MAG of a CE single stage HBT is presented. No inductive / resistive
degeneration was attempted due to having no gain / NF margin for this purpose. The global
minimum of the NF occurs at ≈1.5 mA but the MAG at this bias point is low and, besides,
the MAG slope is too steep. On the other hand, while at high currents (Ice >12 mA) the
MAG asymptotically approaches the value analytically calculated from fmax in Eq. 4.2 the
noise figure is excessive. As a reasonable trade-off between noise and gain the transistor was
biased at Ice,q = 3.6 mA.1
4.1.5 Low-Frequency On-Chip Bias Circuitry
Gain excess at low frequencies is typical for high fmax technologies. This could endanger the
stability of the active circuitry deploying these devices. In order to improve supply-related
stability as good design practice power-dissipating elements (resistors) are added to the supply
circuitry: 20 Ω at base current supply, and 5 Ω at collector supply (Fig. 4.9). RF performance
will not be affected by these resistors, since each of them is followed by a 4 pF shunt capacitor
(having an impedance of 0.5 Ω at 77 GHz thus being a good RF-ground). The additional DC
voltage drop is only due to collector resistor and is 3.6 mA ·5 Ω = 18 mV, so the resulting DC
power dissipation in the resistor is negligible compared to nominal DC consumption.
1To achieve the values of MAG and NFmin different ZMATCH, IN are required. In this case, as subsection 4.1.6
shows, the LNA was matched for optimal return loss. This results in NF degradation of 0.5 dB, as compared
to NFmin in Fig. 4.8.
45
Design of Circuits
4.1.6 Matching Circuitry
Ibb Vcc
RFin RFout
570 µm long,
45 µm wide
150 fF
4 pF 4 pF
20 Ω5 Ω
(26.5 Ω, 95°)
611 µm long,
3.6 µm wide
(95 Ω, 86°) 268 µm long,
16 µm wide
(50 Ω, 43°)
118 µm long,
16.2 µm wide
(50 Ω, 19°)
120 fF
npn201_8
Zin=14.2-j*9.6 Ω
Zout=57.2-j*31.6 Ω
ZMATCH,IN ZMATCH,OUT
120 fF
Figure 4.9: Detailed LNA Schematics
Generally the impedances of an active device for minimal NF and best input return loss differ.
Hence, the most fundamental LNA design trade-off is between input match fidelity and the NF.
Sometimes the trade-off is avoided by deploying sizing of the device to improve matching [83].
This approach could not be deployed in this work, since the devices were sized with linearity
considerations in mind. Another option to avoid the trade-off is using inductive degeneration
so the impedances for optimum NF and RL are brought both together [33]. Unfortunately,
degeneration reduces MAG and the low MAG (Fig. 4.8) does not allow any headroom margin.
In this work the transistor was matched for return loss and not NFmin for the following rea-
sons:
simulations showed that match for S11 resulted in a NF degradation of 0.5 dB compared
to the NFmin matching
lack of full confidence in validity of the noise models at 77 GHz (the noise models were
extracted until 24 GHz and this was the author’s 1st design in this technology)
The unmatched transistor In and Out impedances under the selected biasing conditions are:
14.2−j9.6 Ω and 57.2−j31.6 Ω (in grey on Fig. 4.9), respectively.
RF Input Match
At the LNA input a λ/4 line is used for base bias supply. An additional series λ/4 line
transforms the real part of Zin to 50 Ω and the series capacitor (additionally to being a DC
46
LNA
block) resonates out the remaining imaginary part. After fine-tuning using a simulator the
following component values are obtained:
RF choke: 611 µm long and 3.6 µm wide (95 Ω, 86 ◦)
series λ/4: 570 µm long and 45 µm wide (26.5 Ω, 95 ◦)
series capacitor: 150 fF, square form factor, 11.3 µm each side
The impedance shown to the transistor by the resulting input matching network ZMATCH, IN
was evaluated in several ways:
1. Hand-calculation (assuming both lines as ideal λ/4):
ZMATCH, IN, calculation =26.52
50 + 1
j·2·π·77e9·150e−15
= 13 + j3.6 Ω (4.3)
2. Smith chart: inclusion of the ideal transmission lines exact electric length, ideal capacitor:
ZMATCH, IN, Smith Chart = 14 + j9 Ω (4.4)
So calculation predicts accurately enough the real part, but the imaginary part accuracy
suffers due to ideal λ/4 approximation.
3. ADS simulation with the passivated lines’ models (subsection 3.2.4) and kit 150 fF ca-
pacitor:
ZMATCH, IN, ADS: passivated TL model = 16 + j6 Ω (4.5)
The inclusion of passivated line model slightly affects the impedance
4. ADS simulation with the passivated lines’ models (subsection 3.2.4) and EM-simulated
150 fF capacitor (subsection 4.1.6):
ZMATCH, IN, ADS: passivated TL model + capacitor EM model = 17 + j8 Ω (4.6)
The inclusion of capacitor EM model also has a moderate effect on the impedance
ZMATCH, IN.
Series 150 fF Capacitor EM Model in order to reduce unwanted shunt capacitance (sec-
tion 3.2.3) the ground below the capacitor was removed in this case (since any additional
losses directly affect the NF at the LNA’s input). To have a trustable model a full EM simu-
lation in CST Microwave Studio was carried out. The resulting S-Parameters were fitted with
a lumped model with an expected parasitics topology. The resulting model from this fitting
is shown at figure 4.10. Since an optimizer was used the contribution of some elements is
negligible (they are colored grey).
47
Design of Circuits
2 fF 3.6 pF
2013 Ω
140.5 fF 1.8 pH
3.3 pF
280 kΩ
6 fF
6 pH0.9 Ω
IN
OUT
Figure 4.10: Series 150 fF Capacitor Fitted Lumped Model
RF Output Match
The LNA output impedance is higher than 50 Ω – in case LC match is desired 1st element
has to be in shunt in order to transform the impedance down to 50 Ω. Therefore the shunt
L component can be reused for collector DC biasing. The capacitor comes in series in this
case and also functions as DC block. After fine-tuning in a simulator the following component
values are obtained:
shunt inductive TL: 268 µm long and 16 µm wide (50 Ω, 43 ◦)
series capacitor: 60 fF. For tolerance reasons it was realized by 2 series capacitors 120 fF
each in square form factor, 10.3 µm each side. Also in this case the ground below each
capacitor was removed.
The impedance shown to the transistor by the resulting output matching network ZMATCH, OUT
was evaluated in several ways:
1. Smith chart, ideal transmission lines and capacitor:
ZMATCH, OUT, Smith Chart = 41 + j36.6 Ω (4.7)
2. ADS simulation with the passivated lines’ models (subsection 3.2.4) and two kit 120 fF
capacitors in series:
ZMATCH, OUT, ADS: passivated TL model = 46 + j32 Ω (4.8)
The inclusion of passivated line model also here slightly affects the impedance.
3. ADS simulation with the passivated lines’ models (subsection 3.2.4) and two series EM-
simulated 150 fF capacitors’ models (subsection 4.1.6):
ZMATCH, OUT, ADS: passivated TL model + capacitors EM model = 54 + j25 Ω (4.9)
The 120 fF capacitors were not EM simulated – for comparison purposes the 150 fF
lumped EM model was used (subsection 4.1.6). This explains the deviation from the
desired conjugate of Zout due to capacitor value discrepancy of circa 20 %.
48
LNA
Stability
A convenient way of expressing the necessary and sufficient conditions for an unconditional
stability is [33]:
K > 1 (4.10)
and
B1>0 (4.11)
where Kand B1are the Rollett stability factor and stability measure [84], respectively, that
can be defined for any 2-port in the following fashion:
K≡1−|S11|2−|S22|2+|S11S22 −S12S21|2
2|S12S21|(4.12)
and
B1≡1 + |S11|2−|S22|2−|S11S22 −S12S21|2(4.13)
RF Stability Fig 4.11 shows that simulated LNA Rollett stability factor Kis higher than
unity with a standard margin (K > 1.5) from DC beyond 100 GHz. The stability measure is
positive so the amplifier is unconditionally stable in this case.
0 10 20 30 40 50 60 70 80 90 100 110
100
101
102
frequency [GHz]
K, Rollett Stability Factor
Figure 4.11: LNA RF In-Out Stability Factor
Despite being unconditionally stable the LNA oscillated during measurements. It manifested
itself in fluctuations in collector current supply readings and spectral regrowth while the spec-
trum analyzer is in MAX HOLD mode. Supply-related stability test sheds additional light
onto the global stability.
49
Design of Circuits
Supply-related Stability A single ended RF amplifier is often viewed as a single-input single-
output system. While this holds regarding RF excitation, this is not sufficient for global
stability examination. The DC supplies can be also viewed as terminals for external and inter-
nal excitations, so effectively the LNA becomes a multi-port. To evaluate the supply-related
stability the ports can be applied to the RF-decoupled supply interface nodes (Fig. 4.12) [18].
The RF input and output ports are terminated by 50 Ω resistors. In order not to alter the DC
operating conditions the ports must be AC-coupled. Proper supply filtering is instrumental in
IN
OUT
Q1
Vcc
Port 1 Port 2
50 Ω
50 Ω
DC Block DC Block
Cstab
Rstab
Figure 4.12: Supply-related Stability Evaluation Setup
ensuring optimal supply-related stability conditions for a given amplifier. Specifically, a DC
voltage source is better suited for base biasing. The DC voltage source input impedance is low
for all frequencies so the potential low-frequency oscillations would be shorted. Unfortunately,
voltage base biasing is not advised in BJT / HBT based devices, due to the exponential de-
pendence of ICE on VBE. The deployed DC current source is high-ohmic so the low-frequency
oscillations are not damped at the supplies. To achieve supply filtering of voltage source in
a practical circuit several decoupling capacitors are placed close to the supplies. In board
designs capacitor banks with capacitors’ representation from each decade in order provide a
better grounding over wider frequency band.
Indeed, the LNA low-frequency oscillations were counteracted by soldering directly on the
needle-holder at base supply with a shunt configuration of Cstab = 10 nF (0603) capacitor
in series with Rstab = 5 Ω. Fig. 4.13 shows the simulated supply-referenced stability factor
with and without the external stabilizing network and some values in-between. In the case
without the stabilizing network the simulated supply-referenced K factor is dangerously close
to unity around 200 MHz. Simulation also predict that the off-chip network solves the stability
problem.
50
LNA
1031041051061071081091010 1011
100
101
102
103
104
105
frequency [Hz]
K, Rollett Stability Factor
no Rstab
Rstab = 5 kΩ
Rstab = 500 Ω
Rstab = 50 Ω
Rstab = 5 Ω
Figure 4.13: LNA Supply-related Stability Factor as Function of Shunting Resistor
4.1.7 Realized LNA
Fig. 4.14 shows the layouted LNA. The main area contributor is the 570 µm long input trans-
mission line. To reduce the risk, the sensitive RF input path was not bended. the λ/4 gate
biasing line was bended to save in lateral dimension. To reduce coupling effects from the mi-
crostrip to neighboring line parts grounded electric “walls” were added. The walls were placed
at least 30 µm from the line, to avoid altering of the line properties by a nearby ground strip.
Figure 4.14: LNA Layout
51
Design of Circuits
4.1.8 S-Parameters
Standard on-chip S-parameters measurements deploying 2-port network analyzer were carried
out. On-chip broadband (DC – 110 GHz) calibration with very high fidelity was performed
prior to the measurements. The calibration fidelity could be judged by:
the transmission phase errors at the low frequencies, which is acceptable in the light of
high attenuation that reaches −65 dBm (Fig. 4.17, 4.18)
agreement in the magnitude of Sii notches – better than 30 dB at high frequencies,
without any visible ripple (Fig. 4.16, 4.20)
Simulated vs. Measured S-Parameters
The LNA was simulated mimicking the layout and the pads were subtracted from the measure-
ments using the pad model
2 (RLC) (section 3.2.5) and “negative image modeling” [66] as
shown on Fig. 4.15. Due to HBT emitter design changes the foundry provided a “new” HBT
model, additionally to the “old” model. The new model differs from the old in better ICE fit
for higher VBE values, forward emission coefficient reduction (due to new emitter process) and
better CBE agreement. The simulations of thee LNA using both models are compared with 3
LNA on-chip measured samples.
Cp
Rp
Cshunt
Lseries
-Cp
-Rp
-Cshunt
-Lseries
Figure 4.15: Pad Subtraction Approach
Input reflection (Fig. 4.16). A notch is seen both in the magnitude and the phase re-
sponses around 15 GHz. Both models and the 3 samples fully agree below 60 GHz. Above
60 GHz the phase of the old model accumulates a certain error. In terms of magnitude
the old model predicts the notch at 75 GHz better than the new model, whose notch is
slightly higher in frequency (circa 80 GHz).
Reverse isolation (Fig. 4.17). There is a fairly good agreement between the both models
and 3 measured samples (apart from sample
3, which seems to be defective).
52
LNA
Figure 4.16: LNA’s S11
Figure 4.17: LNA’s S12
Forward transmission (Fig. 4.18). Here also the models and the measurements agree
quite well (apart of sample
3, which shows an unexpected notch circa one octave
below band of interest). The zoomed transmission in the frequency of interest (Fig. 4.19)
shows that the old model predicts higher gain (4 dB) than the new model (2.8 dB).
Output reflection (Fig. 4.20). Also here a good agreement exists between the both models
and samples
1 and 2. Sample
3 has an additional notch one octave below band of
interest.
53
Design of Circuits
Figure 4.18: LNA’s S21
Figure 4.19: LNA’s S21 Zoomed
4.1.9 Noise Figure
Noise Figure Measurement Setup
On Fig. 4.21 the noise measurement setup for the LNA is shown (without DC biasing arrange-
ments). A 77 GHz spectrum analyzer was not available during the measurements. In order to
enable deployment of a standard low-frequency spectrum analyzer (HP41800A, which covers
input frequencies until 500 MHz) frequency-extension was used as part of measurement set-up.
The LNA’s 77 GHz output signal was down-converted using an external sixth-harmonic mixer.
Accordingly, the harmonic mixer’s LO reference was approximately at 12.8 GHz (so that the
54
LNA
Figure 4.20: LNA’s S22
down-converted signal falls within spectrum analyzer’s passband). The advantages of using
a higher order harmonic mixer are twofold: it allows the deployment of a lower frequency
source and the high conversion loss of the mixer prevents the spectrum analyzer from entering
compression. NF and linearity measurement setup included a narrow-band Gunn Oscillator
(as the LO source) so these measurements are available at 77 GHz only.
The Y-Factor method, also known as “hot-cold” method was used to evaluate NF. This method
allows determination of internal DUT NF as opposed to overall system NF (that includes
noise contributions from the measuring instrument itself). 2 measurements are performed
under different noise temperatures (therefore “hot” and “cold”), i.e. 2 unknowns (NFDUT and
NFmeasuring instrument) can be found from 2 equations. The accuracy of this method depends
on “hot-cold” source calibration fidelity [1].
Figure 4.21: LNA Noise Figure Measurement Set-Up
55
Design of Circuits
LNA NF Measurements vs. Simulations
There is a good NF measurement-simulation agreement for 3 operating points (table 4.1).
Table 4.1: A Summary of LNA’s Performance for 3 Bias Currents
Ice,q [mA] Gain [dB] iP1dB [dBm] oP1dB [dBm] NF [dB]
sim. meas. sim. meas. sim. meas. sim. meas.
3.6 4 3.4 -7.5 -2.4 -4.5 0 6.1 5.7
5 4.7 3.8 -5.5 -0.2 -1.8 2.6 6.2 5.8
10 5.6 4 -0.5 4.5 4.1 7.5 6.9 6.7
In order to get a better insight concerning critical noise contributors in the LNA the major
contributors to output noise are shown at table 4.2. Among the HBT contributors collector
shot noise is the dominant, and base thermal noise is the 2nd in importance. RFin port noise
contribution (which is commensurate with HBT noise contribution) is greater than of RFout
port (since the input noise is amplified). The input series 570 µm transmission line noise is
not significant, since it is lower than RFout port noise.
Table 4.2: LNA’s Output Major Noise Contributions’ Breakdown – bias of 3.6 mA
Contributors hnV
√Hz i
HBT
itzf (Collector Shot) 0.9
rbx (Thermal Base Extrinsic Resistor) 0.47
rbi (Thermal Base Intrinsic Resistor) 0.39
re (Thermal Emitter Resistor) 0.24
rbp (Thermal Parasitic Base Resistor) 0.19
ibe (Shot Base) 0.14
rcx (Thermal Collector Extrinsic Resistor) 0.06
flicker ibe 0.03
total (HBT) 1.15
RFin Port 0.69
RFout Port 0.44
Input Series TL 0.25
Output Shunt TL 0.12
Input Series 150 fF Capacitor: 2013 Ω Shunt Resistor 0.11
Total 1.45
56
LNA
4.1.10 Linearity
Linearity Measurement Setup
LNA linearity measurement setup (Fig. 4.22) is similar to the NF setup, whilst the noise source
is replaced by a Gunn Oscillator. To allow input power sweep a variable attenuator is inserted
after the RF Gunn source.
Figure 4.22: LNA Linearity Measurement Set-Up
Simulated vs. Measured Gain Compression
The LNA gain compression curves for 3 bias points are shown at Fig. 4.23.
Figure 4.23: LNA Gain Compression for 3 Bias Currents
57
Design of Circuits
4.1.11 Measurements vs. Simulations: Gain, Linearity, NF
The LNA’s main performance merits are presented in table 4.1 for 3 bias points. NF agrees
with the preliminary analysis (subsection 4.1.3), small deviations (up to 0.4 dB) between
simulations and measurements are found. However, both simulated gain and linearity differ
from the measured values. Discrepancies in gain values (0.6 dB, 0.9 dB and 1.6 dB) grow for
increasing bias current values. Such behavior normally indicates setup calibration inaccuracies,
which are still within acceptable limit considering high frequency and error accumulation. The
linearity measurement-simulation discrepancy is circa 5 dB in the worst case. But the most
probable reason for the discrepancy in linearity performance is the large signal HBT model.
As confirmed by the foundry, the model was optimized with emphasis on small-signal and
noise behavior, so large-signal accuracy is compromised. Nevertheless, the measured iPdB is
−2.4 dBm, which is high enough above front-end target linearity of −10 dBm. So the LNA
will not be the limiting block in the front-end linearity cascade. This result justifies the chosen
strategy of designing the LNA for high linearity. Subsections 4.3.8 and 5.1.2 examine the
influence of the LNA’s measured gain and NF on the overall mixer and front-end NF.
4.1.12 Benchmarks and Discussion
Table 4.3: Comparison of standalone single-ended LNAs operating above fmax
4
GaAs InP SiGe CMOS
This
[27] [92] [88] Work [19] [30] [25] [14] [61] [60]
Node Size [nm] 150 70 80 250 350 120 130 90 90 65
Active Device HEMT HBT FET
ft[GHz] >80 293 380 180 200 205 70 100 100 140
fmax [GHz] >170 337 283 220 275 290 135 150 130 220
fcenter [GHz] 77 90 87 77 77 77 60 60 60 77
fmax
fcenter 2.2 3.7 3.3 2.9 3.6 3.8 2.3 2.5 2.2 2.9
NF [dB] 4 3 3.5 5.7 5.5 5.6a8.8 4.4 8 7.4
S11 [dB] -7 -12 -25 -20 -26 -10 -16 -15 -16 –
S22 [dB] -7 -15 -10 -12 -19 -21 -18 -17 -21 –
S21 [dB] 10 19 18 3.5 8 15 12 15 13 17.5
S12 [dB] -33 -30 -35 -14 -33 -40 -45 <-25 – –
iP1dB [dBm] – -10 -22 -2.4 -3 -17 -9 -18 -4 -22
Vcc [V] 3 1.5 3 1.6 5.5 1.8 1.5 1.3 1.2 1.2
Icc [mA] 30 24 4 3.6 22 8 36 3.1 35 25
Area [mm2]b1.34 3 0.41 0.25 0.20 – 1.2 0.04 0.3 0.4
aSimulated value.
bWithout pads.
Table 4.3 shows a comparison between III-V, SiGe and CMOS published LNAs at low fmax
fcenter .
58
LNA
As expected, the III-V LNAs all have superior noise performance to Si designs due to better
technology properties. Since higher gain is easier achieved in III-V, these LNAs have mediocre
linearity, which is not sufficient for the application. Additionally, the III-V LNAs shown in the
table occupy relatively large area. The shown SiGe LNAs have similar NF, their gains vary
and the area is shrunken (as compared to III-V).
Among the CMOS LNAs [14] stands out: a 3-stage common-source topology was chosen with
very small transistor sizing. It minimizes the parasitics and loosens the requirements on the
matching network and subsequently minimizes the losses introduced by the matching network.
Therefore, among other advantages this design has best NF in Si, which approaches actually
performance of III-V designs. This design is complemented by [61], which has very high
linearity (best in CMOS) and obviously its NF was traded-off for that.
Compared to other state-of-the-art LNAs in various semiconductor processes with different
feature size the LNA presented in this work has one of the best reported linearity properties,
average noise figure and lowest gain. A single stage common-emitter design having the largest
transistor results in high linearity, which inevitably comes at the expense of the gain. Therefore,
unlike the vast majority of RF designs, where a multistage LNA suppresses noise contributions
of further stages (at the price of overall linearity) here the presence of an LNA stage does not
compromise the linearity while the overall NF is still improved (subsections 4.3.8 and 5.1.2).
Thus a different design approach at high frequencies is suggested: while traditionally front-end
designs are classified as either highly-linear or low-noise, here a smoother trade-off between the
two performance criteria is enabled, allowing finer tuning of the front-end performance. The
fine-tuning ability is a welcome feature in this application (ACC LRR), where both linearity
and noise are important (chapter 2).
59
Design of Circuits
4.2 Balun
A balun (balanced-to-unbalanced converter) converts a single-ended excitation (referenced
to the ground) into a differential mode (referred to also as odd mode) most efficiently, while
suppressing the residual common mode (also known as even mode). This definition applies
when the single-ended terminal is assumed to be the input and the differential – the output.
4.2.1 Main Requirements imposed on the Balun
Imbalance fidelity. A perfect balun has perfect amplitude balance (0 dB) and 180 ◦phase
balance. To facilitate the evaluation of balun composite phase and amplitude imbalance
a figure of merit called CMRR is deployed. CMRR (stands for Common-Mode-Rejection-
Ratio) is defined as the diff.-mode gain normalized by the common-mode gain [8]:
CMRR ,20 log bdm
bcm ≈20 log 2+∆
√∆2+θ2(4.14)
The approximation in equation 4.14 is valid for small values of amplitude and phase
imbalance (∆ and θ, respectively). The CMRR can be also expressed as function of the
measured S-parameters [9]:
CMRR = 20 log S21 −S31
S21 +S31 (4.15)
Noise Figure/Loss. For RF path the balun NF strongly affects sensitivity of the receiver.
Isolation between the differential outputs.
Bandwidth. The aforementioned performance criteria have to be met over bandwidth
required by application.
DC consumption.
Layout area. Since baluns at mm-wave frequencies could involve transmission line com-
mensurate with λ/4 this could lead to large real estate consumption. In a circuit such as
double-balanced mixer, requiring 2 baluns the area requirements become more critical.
4.2.2 Balun Performance Evaluation Setups in Simulation and Measurement
Two kinds of setup were used in the synthesis, optimization and evaluation of baluns:
Setup
1 – used for: transmission per each branch, even-mode input RL, imbalance.
Setup
2 – used for: total conversion from even to odd mode (IL), even mode input
return loss (RL), odd mode output RL.
60
Balun
IN
OUT+
OUT-
50 Ω
50 Ω
DUT = BALUN
Port 1 Port 2
50 Ω
Port 3
v1
v2
v3
i2
i1
i3
a3
b3
b2
a2
b1
a1
Figure 4.24: BALUN Measurement Setup
1: Two Independent Output Ports
IN
OUT+
OUT-
50 Ω
100 Ω
DUT = BALUN
Port 1
Port 2
Figure 4.25: Balun Measurement Setup
2: A Differential Output Port
4.2.3 Active Balun
Functionality
An active balun relates to a circuit family performing signal mode conversion with active
elements. It originates from lower frequency analog circuit design, where the transistors have
better performance in terms of gain, NF and the parasitics are not pronounced. At mm-
wave frequencies the standard analog techniques face difficulties. The parasitics worsen the
amplitude and the phase balance, so standard analog circuit design techniques need to be
complemented by high-frequency design techniques. Due to deployment of active devices at
mm-wave frequencies the active balun suffers from relatively high noise figure as compared to
his passive counterparts, so its deployment in the RF path is less attractive. Still, it could be
still deployed as the LO interface (noise in the LO inputs is of little importance to the overall
mixer noise. LO excitation is large signal and the signal over most of the period is distanced
from zero-crossings, where noise could corrupt the switching nature of the mixer). Additionally,
an active balun could include a benefit concerning LO interface (subsection 4.3.5), such as low
output impedance buffering.
61
Design of Circuits
Overview of Existing Topologies
Single-ended driven differential pair ([107], [76]). This option is shown on Fig. 4.26a; it
is the classical low-frequency analog approach to baluns. Its advantages are the broad
bandwidth of balancing that starts from DC, compact layout size, well-known topol-
ogy. Its obvious drawback is an inherent lack of symmetry, since the unexcited input is
grounded (from RF perspective). At high frequencies this would translate to imbalance.
Common-base/common emitter (common-gate/common-source in CMOS case: [100],
[86]) balun (Fig. 4.26b). Here a different attempt to obtain anti-phase signals is taken.
A common emitter (source) amplifier inverts input signal’s polarity, while common base
(gate) keeps the polarity of the input. This could yield better balancing at mm-wave
frequencies than a straightforward single-ended driven differential pair. Still this is not
an optimal approach to balancing: difference in sizing of CE and CB stages, their I/O
impedances and capacitances would still imbalance the structure, more so in large signal
operating region (critical for LO buffer).
Single-ended driven differential pair followed by imbalanced emitter followers ([103], [104],
[102]). As Fig. 4.26c shows this solution is based on the single ended differential pair. The
imbalance caused is removed in subsequent buffer stage, which is imbalanced with the
opposite sign so the composite solution is balanced. It is acknowledged that the current
sink of the differential stage (shunted by its own capacitance) cannot provide the high
common mode impedance that could suppress the common mode. The transmission line
(or an inductor) at the emitter followers collectors in tandem with the different ohmic
loads creates a nearly optimal distributed common mode impedance needed for overall
balancing. Therefore this solution was selected.
Performance
The active balun is matched and balanced over more than 30 % of relative bandwidth (Fig. 4.27).
The phase and amplitude imbalance contributions are shown on Fig. 4.28. The gain slope is
close to 20 dB per decade (Fig. 4.29) – a validation that the inductive transmission line at the
buffer supply path affects mostly the common mode. The gain is 1.8 dB per branch at the
working frequency. NF was not optimized in this design, so is too high for the active balun de-
ployment in the RF path. The oP1dB (per each output) is circa 0 dBm (Fig. 4.30), which is the
power a SiGe mixer would need at the LO inputs. To ensure higher safety margins regarding
linearity the quiescent current of the differential and buffer stages can be increased.
62
Balun
Q1 Q2
Vcc
Match
Input
IN
SE
OUT+
OUT-
RF
short
(a) SE-driven Differential Pair
Q1
Q2
Vcc
Match
Input
IN
SE
OUT+
OUT-
Vcc
Vcc
(b) CB – CE pair
Q1 Q2
5.5 V
IN
SE OUT+
OUT-
Q3
Q4
20 mA 2 pF
34 fF
230 µm long
5.4 µm wide
1 pF
20 mA 180 µm long
3 µm wide
1 pF
1 pF
245 Ω400 Ω
200 Ω200 Ω
1 pF
1 pF
(c) SE-driven Differential Pair Followed by Imbalanced CC Buffers
Figure 4.26: 3 Active Balun Approaches
4.2.4 Passive Balun
1 – Rat Race Coupler
Classical Rat Race Coupler Operation Principle
The so called “rat-race” coupler design approach utilizes classical microwave concepts of mul-
tiple impedance inversion. A λ/4 offset between 2 adjacent ports isolates between the ports,
aλ/2 offset between two ports inverts the signal polarity. Therefore the classical rat-race
coupler (depicted on Fig. 4.31) the OUT+ port is 3λ/4 from the input, so has the opposite
polarity and isolated from the input; OUT−port is isolated from the input and has the same
polarity. There are 2 paths to the ISOL port from the input: λand λ/2 so the signals arrive
in anti-phase and cancel each other [78]. The advantages of the classical rate-race coupler are:
passivity, low insertion loss, all ports are matched (without additional matching networks that
could add to insertion loss), excellent isolation between all ports. The disadvantages are the
size (due to multiple λ/4 sections), relative bandwidth limitation due to use of λ/4 lines (they
63
Design of Circuits
0 10 20 30 40 50 60 70 80 90 100110
−40
−30
−20
−10
0
frequency [GHz]
Reflection [dB]
simulated
(a)
0 10 20 30 40 50 60 70 80 90 100110
0
5
10
15
20
25
30
35
40
45
50
frequency [GHz]
[dB]
simulated CMRR
simulated Isolation
(b)
Figure 4.27: Active Balun Input Return Loss, CMRR and Isolation
0 10 20 30 40 50 60 70 80 90 100110
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
frequency [GHz]
Imbalance [dB]
simulated
(a)
0 10 20 30 40 50 60 70 80 90 100110
−185
−180
−175
−170
−165
−160
frequency [GHz]
Imbalance [◦]
(b)
Figure 4.28: Active Balun Imbalance
0 10 20 30 40 50 60 70 80 90 100110
−10
−5
0
5
10
15
20
25
frequency [GHz]
Transmission [dB]
simulated
(a)
0 10 20 30 40 50 60 70 80 90 100110
0
4
8
12
16
frequency [GHz]
Noise Figure [dB]
simulated
(b)
Figure 4.29: Active BALUN Insertion Gain and Noise Figure
64
Balun
−30 −25 −20 −15 −10 −5 0 5
−3
−2
−1
0
1
2
3
Input Power [dBm]
Gain [dB]
simulated
(a)
−30 −25 −20 −15 −10 −5 0 5
−30
−25
−20
−15
−10
−5
0
5
Input Power [dBm]
Output Power [dBm]
simulated
(b)
Figure 4.30: Active Balun Output Power and Gain vs. Input Power
retain their impedance inverting properties approximately till 25 % of BW).
λ/4 λ/4
λ/4
λ/4 λ/4
IN, 50 ΩOUT+, 50 Ω
OUT-, 50 ΩISOL, 50 Ω
70.7 Ω70.7 Ω
70.7 Ω70.7 Ω
70.7 Ω
λ/4
70.7 Ω
Figure 4.31: Classical Transmission Line Rat Race Coupler Schematics
Reduced-Length Rat Race Coupler Design
In microstrip realization each of λ/4 sections would be circa 600 µm long, which translates
into an overall area exceeding 1 mm2. A reduced length rat race coupler proposed by [43]
is adopted in this work. There are 2 main sections to a classical rat-race coupler: λ/4 and
3λ/4.
Equivalent Shortened λ/4Transmission Line Segment with Capacitive Compensation The
λ/4 can be represented with a physically shorter line. In order to keep the inductance the same
65
Design of Circuits
new line has to be narrower (or of higher impedance). The missing area capacitance can be
compensated by shunt lumped capacitors at both line ends (Fig. 4.32). There is a practical
lower limit on the line width (or maximal characteristic impedance). Therefore the λ/4 line
was shortened to λ/8 (the resulting line width is circa 3 µm). Comparing Y (admittance)
matrices for λ/4 line with capacively compensated line [78] one obtains that characteristic
impedance of the shortened line should be 100 Ω. The compensation capacitor at both line
ends is 1
2πfZ0cos π
4= 20.7fF.
λ/4, Z0 = 70.7 Ω
λ/8, Z = 100 Ω
C=20.7 fF C=20.7 fF
Figure 4.32: Equivalent Shortened Transmission Line Segment with Capacitive Compensation
3λ
4Equivalent Transmission Line Segment [75] shows that a TL segment can be represented
either as a low/high pass lumped πnetwork (Fig. 4.33). A high pass network is preferred, since
3λ/4, Z0=70.7Ω
29 fF
146 pH 146 pH
Figure 4.33: πNetwork Equivalent to 3λ
4Transmission Line Segment
it has a series capacitor (which corresponds to a shorter length compared to series inductor of
the low pass equivalent circuit). Comparing ABCD matrices of a lossless TL segment of 3λ/4
to that of a πequivalent circuit shown on Fig. 4.33 two equations are formed [78]:
cos β(3λ/4) jZ0sin β(3λ/4)
jY0sin β(3λ/4) cos β(3λ/4) =1 + Y1/Y21/Y2
2Y1+Y12/Y21 + Y1/Y2(4.16)
Their solution yields the πequivalent network values: L= 146 nH and C= 29.2 fF.
The overall equivalent schematic is shown on Fig. 4.34. The LC sections shown in gray resonate
at 91.6 GHz, which is close enough to the operating frequency so both could be omitted from
the final equivalent schematics.
66
Balun
λ/8
IN, 50 ΩOUT+, 50 Ω
OUT-, 50 ΩISOL, 50 Ω
100 Ω
λ/8
100 Ω
λ/8
100 Ω
146 pH146 pH
29 fF 20.7 fF20.7 fF
20.7 fF 20.7 fF
20.7 fF 20.7 fF
Figure 4.34: Reduced-Length Transmission Line Rat Race Coupler Schematics
Realized Reduced-Length Rat Race Coupler
The length and the width of λ/8 TL as well as the series and shunt capacitors of circuit
of Fig. 4.34 were fined-tuned in circuit simulation using the PDK models so the CMRR is
maximized. The following set of the component values was obtained:
TL: 321 µm long (vs. the calculated 327 µm) and 2.4 µm wide (vs. the calculated 3 µm).
In electrical terms it means 105 Ω, 44 ◦(vs. theoretical 100 Ω, 45 ◦). Interestingly the
change in the width is due to passivation inclusion (3µ·0.77 = 2.31µ, Fig. 3.8a)
shunt capacitor: 52.3 fF (vs. the calculated 41.4 fF) (there are 2 shunt capacitors of the
same value at nodes OUT−and ISOL, so both were lumped together)
series capacitor: 28.5 fF (vs. the calculated 29.2 fF). In order to avoid increased spread
typical for small capacitance values it was decided to realize the series capacitor as 2
series capacitors 57 fF each.
The second order effects caused by omission of the LC sections were compensated for by
fine-tuning the rest of the components’ values. The same solution set was obtained when the
optimization criterion was minimization of transmission from the single-ended input to isolated
termination. All the λ/8 lines were bended to save area (Fig. 4.35 and 4.36)
Characterization Approach for mm-Wave Baluns
As Fig. 4.24 and 4.25 indicate, a 3- (or a 4-) port network analyzer is required to characterize
a balun. At 77 GHz the availability of multi-port network analyzers is still limited, a 2-port
network analyzer was available. Since circuit design and layout were done deploying high
67
Design of Circuits
Figure 4.35: Reduced-Length Transmission Line Rat Race Coupler Layout (BAL 1 2)
Figure 4.36: Reduced-Length Transmission Line Rat Race Coupler Layout (BAL 1 3)
frequency techniques and due to high repeatability of the BiCMOS process, a low spread
between 2 different balun circuits was assumed. A suggestion was made to measure the balun
as a 2 port only, but in two configurations. In case of BAL 1 2 ports IN and OUT+ were probed
while port OUT−terminated on chip with 50 Ω load (Fig. 4.37) and in case of BAL 1 3 ports
IN and OUT−were probed while port OUT+ terminated on chip with 50 Ω load (Fig. 4.38). In
S-parameter post processing the pads’ effects were removed according to Fig. 4.15. Input return
loss and gain are available directly from and single BAL 1 i measurement, while imbalance,
CMRR could be evaluated in post-processing deploying measurements from both baluns. To
probe balun output odd mode return loss a special set-up was constructed in post-processing
(Fig. 4.39). The isolation between the 2 outputs could not be characterized with such set-up,
so was only simulated.
68
Balun
50 Ω
50 Ω
Port 1
Port 2Pads
Substracted
Pads
Substracted
IN
OUT+
OUT-
DUT = BALUN+ 50 Ω
On-chip
(BAL_1_2)
Figure 4.37: BAL 1 2 Measurement Set-Up
IN
OUT+
OUT-
DUT = BALUN-
50 Ω
On-chip
50 Ω
Port 1
Pads
Substracted
50 Ω
Port 2
Pads
Substracted
(BAL_1_3)
Figure 4.38: BAL 1 3 Measurement Set-Up
IN
OUT+
OUT-
50 Ω
100 Ω
DUT = BALUN-
Port 1
Port 2
Pads
Substracted IN
OUT+
OUT-
DUT = BALUN+ 50 Ω
On-chip
50 Ω
On-chip
Pads
Substracted
Pads
Substracted
Pads
Substracted
Figure 4.39: BALUN Output Odd-Mode Impedance Probing Setup
69
Design of Circuits
Reduced-Length Rat Race Coupler Measurements vs. Simulations
The input return loss notch in simulations and measurements is around 65 GHz since the rat
race was designed using standard transmission line model. However, the input match is quite
wide-band (Fig. 4.40, 4.42), therefore in-band performance was good (−17 dB). The in-band
Figure 4.40: BAL 1 2 Even-mode Complex Input Reflection Coefficient
insertion loss is −4.5 dB (1.5 dB worse than the theoretical). BAL 1 2 and BAL 1 3 insertion
losses have different frequency responses – ascending and descending at higher frequencies,
respectively (Fig. 4.41 and 4.43). This is due to the asymmetry caused out-of-band due to de-
ployment of the narrow-band high-pass lumped πapproximation to 3λ/4 line. The amplitude
Figure 4.41: BAL 1 2 Insertion Loss: Input Even-Mode to Output Odd-Mode
imbalance (Fig. 4.44) has clear frequency dependence, so despite accurate simulation, modeling
and layout the amplitude imbalance is up to 1 dB (worst case). The phase imbalance (7 ◦)
characteristics show more broadband characteristics. The simulation agrees with the measure-
ments for both baluns over 3 samples each, so the CMRR was simulated only (Fig. 4.45). As a
70
Balun
Figure 4.42: BAL 1 3 Even-mode Complex Input Reflection Coefficient
Figure 4.43: BAL 1 3 Insertion Loss: Input Even-Mode to Output Odd-Mode
result of amplitude imbalance frequency dependence the CMRR is frequency-selective: it peaks
with 55 dB and exceeds 25 dB over 25 GHz. The isolation is very good in the rat-race case
(due to the presence of a dedicated isolation termination): it exceeds 20 dB over 25 GHz. The
odd-mode output return loss (Fig. 4.46) was extracted with hybrid simulation-measurement
approach as shown on Fig. 4.39. There is a good simulation-measurement agreement, while it
is worse than in single-ended input case (Fig. 4.40) as a result of error propagation from both
measurements.
71
Design of Circuits
Figure 4.44: Rat-race Imbalance
Figure 4.45: Rat-race Simulated CMRR and Isolation
Figure 4.46: Output Odd-Mode Reflection Extracted from 2 Measured Baluns
72
Balun
4.2.5 Passive Balun
2 – Transformer
The realised reduced-length rat-race length is 0.5 mm, almost two-fold improvement compared
to a classical rat-race realization. The objective of designing a transformer was to further
cut down real estate requirements. For frequencies above 40 GHz transformer-based baluns
offer size advantages over rat-race baluns (and other mm-wave coupled line baluns, such as
Marchand [28]).
Transformer Background
A transformer balun [10], [4] consists of the core, coupling the energy from one winding to
another and the matching circuitry at input and outputs (that turn the transformer into a
mm-wave balun).
General Transformer Core Design Guidelines – Circuit Level Approach
Width: An inductor should be deployed at frequencies below its SRF (self-resonance
frequency) so the shunting capacitance is low enough and the effective inductance is
frequency independent. In this design, reliability concerns due to DC electro-migration
effects set the lower limit on line-width [24].
Turn-to-turn spacing. A one-to-one transformer is designed (single loop primary and a
single secondary loop) for better SRF.
Losses vs. SRF considerations: in order to minimize the shunting parasitic capacitance
the M1 ground below the windings was removed (at the price of slightly increased trans-
mission losses due to unshielded conducting substrate).
Mutual inductance enhancement. The primary turn (single-ended input) was placed
at TM1 (2nd topmost metal) and the secondary turn (differential output) – on TM2
(topmost metal).
Each core winding was layouted in a square shape so two parameters had to be optimized: the
winding length and its width. The transformer core optimization strategy was minimizing the
achievable transformer core insertion loss. The insertion loss, however, depends additionally
on input and output transformer matching networks, which should be included at a later
stage. In order to decouple the effects of matching networks it was decided to maximize the
maximal available gain (MAG) [33].1The CST optimization yielded MAG= −0.8 dB for the
square windings structure with the following dimensions: each outer side is 70 µm long, 7.5µm
wide.2
73
Design of Circuits
1:1
65 pH65 pH500 Ω
k = 0.66
10 fF
10 fF
1 Ω1 Ω
38 fF 16 fF
IN OUT+
OUT-
Figure 4.47: Transformer Core Fitted Lumped Model Schematics
Transformer Core – Fitted Lumped Model An accurate lumped model is preferable to
a frequency domain s-parameter set: it contains physical information, is valid in the wider
frequency range, filters out EM simulator numerical noise and the representation is more
compact. After the transformer core size was fixed, a lumped model was fitted manually to
the simulated S-parameter set. A simple narrow-band transformer equivalent circuit topology
was assumed [4]. The core is a magnetically coupled 2 identical coils (each with a resistive
losses), a capacitive coupling is assumed both between the turns and between each turn and
the common mode (ground). Shunt resistive losses are added at the input. The fitting was
carried out using a differential 100 Ω output port (Fig. 4.25). The component values obtained
from fitting are shown on the schematics (Fig. 4.47). Despite using lumped approximations
the fit is very good in a wide bandwidth for input return loss magnitude and phase (Fig. 4.48),
insertion loss magnitude and phase (Fig. 4.49) and output differential return loss magnitude
(Fig. 4.50). The fit of output differential return loss phase is good, the slight discrepancy
(12 ◦, worst case) is the toll of deploying a lumped narrow-band approximation – if better fit is
desired a distributed model is needed with more degrees of freedom. The analytical calculation
of each winding’s inductance using modified Wheeler equation [110] yields 90 pH (as opposed
to fitted value of 65 pH). For the calculation of the capacitance between the windings and the
substrate Van de Meijs’ and Fokkema’s empirical expression was used [101]. For the primary
turn the shunt capacitance of 33 fF was calculated (in line with the fitted value of 38 fF). Same
empirical formula yields 14 fF shunt to the ground for each half of the secondary winding.
Transformer Balun Synthesis Flow – System level Approach
As soon as the core of the transformer is fixed, the input- and output- matching networks are
added, in a way that:
1Here the MAG concept is extended onto a passive network design, where the MAG inevitably would have a
negative sign.
2MAG was measured by probing the 3-Port core S-Parameter file available from EM simulator as suggested in
balun measurement setup
2: using a differential output port (Fig. 4.25).
74
Balun
10 20 30 40 50 60 70 80 90 100
−10
−8
−6
−4
−2
0
frequency [GHz]
Reflection Loss [dB]
full EM simulation (CST)
fitted
(a)
10 20 30 40 50 60 70 80 90 100
−60
−20
20
60
100
140
180
frequency [GHz]
Reflection [◦]
(b)
Figure 4.48: Transformer Core Even-mode Complex Input Reflection Coefficient
10 20 30 40 50 60 70 80 90 100
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
frequency [GHz]
Insertion Loss [dB]
full EM simulation (CST)
fitted
(a)
10 20 30 40 50 60 70 80 90 100
−80
−60
−40
−20
0
20
40
60
80
frequency [GHz]
Insertion [◦]
(b)
Figure 4.49: Transformer Core Insertion Loss: Input Even-Mode to Output Odd-Mode
input match (for the single-ended excitation) and output match (for odd-mode excitation)
is achieved;
CMRR is improved (since the parasitics are resonated out) so the transformer is a true
balun;
the insertion loss is minimized and approaches the MAG (with the exception of the losses
introduced by the matching networks).
The matched transformer core (Fig. 4.51) is probed as shown in balun measurement setup
2
using a differential output port (Fig. 4.25). The 2-port probing setup allows deployment of
small-signal amplifier design techniques for transformer balun synthesis.
Input Matching Circuit The realized input matching network presents the core input with
an impedance ZS= 56 + j16 Ω
75
Design of Circuits
10 20 30 40 50 60 70 80 90 100
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
frequency [GHz]
Reflection Loss [dB]
full EM simulation (CST)
fitted
(a)
10 20 30 40 50 60 70 80 90 100
120
130
140
150
160
170
180
frequency [GHz]
Reflection [◦]
(b)
Figure 4.50: Transformer Core Odd-mode Complex Output Reflection Coefficient
IN
OUT+
OUT-
80 fF
80 fF
80 fF
80 fF
80 fF
250 µm long,
5 µm wide,
(86 Ω, 36°)
62 µm long,
9 µm wide,
(69 Ω, 9°)
62 µm long,
9 µm wide,
(69 Ω, 9°)
Transformer Core
Input Match Output Match
ZS
ZL
IN
OUT+
OUT-
Figure 4.51: Transformer Balun Detailed Schematics
Output Matching Circuit The realized output matching network presents each core output
with an impedance ZL/2 = 25 −j24 Ω. The 40 fF shunt capacitor was realized by 2 series
80 fF capacitors in order to lessen impact of process spread.
Realized Transformer
The shorted stub of the input matching network was bended to save space as shown in Fig. 4.52.
In the transformer case same approach is deployed to characterization as in the rat-race case
(subsection 4.2.4), so two 2-Port transformer layout configurations were layouted. The EM
76
Balun
simulations show no performance change if the physical ground is present at the center tap
of the secondary tap thanks to symmetry-enforced virtual ground. Nevertheless, to be on the
safe side, the center tap of the secondary tap was explicitly grounded.
Figure 4.52: Transformer Layout
Transformer Measurements vs. Simulations
Two simulation approaches were deployed in transformer simulation at different design stages:
Hybrid simulation approach – synthesis. First EM simulators (CST, Sonnet) were de-
ployed to fix the core dimensions and then a circuit simulator (ADS) was used to syn-
thesize the matching networks.
EM simulation approach – validation. The whole transformer balun structure was EM
simulated (CST) to validate the overall design and to include couplings and other EM
interactions not accounted for by a circuit simulator.
The input return loss for the “Up” and “Down” transformer on Fig. 4.52 are presented on
Fig. 4.53 and 4.55. Hybrid simulation using CST yields most accurate results for both “Up”
and “Down” cases, while the input return loss notch is slightly shifted towards higher fre-
quencies in hybrid Sonnet case. The notch in the full EM CST simulation case is slightly
shifted towards lower frequencies. The discrepancies in input return phase are due to phase
“wrapping” – multiples of 360◦are added or subtracted. The input return loss phase is more
prone to error for high return loss values. The insertion loss for both transformers’ configu-
rations is 4.5 dB (Fig. 4.54 and 4.56). There is no visible spread between 3 samples of each
77
Design of Circuits
Figure 4.53: Xformer-Up Even-mode Complex Input Reflection Coefficient
transformer arrangement. Also in this case the hybrid CST simulation is in best agreement
with the measurements, while the worst case discrepancy in the amplitude case is 1.5 dB out-
of-band (hybrid Sonnet). In case of insertion loss phase: 10◦phase discrepancy correspond to
length offset of 50 µm which is attributed to the uncertainty in probing needle placement (pad
length is 100 µm). The transformer balancing (Fig. 4.57), both amplitude and phase is very
Figure 4.54: Xformer-Up Insertion Loss: Input Even-Mode to Output Odd-Mode
broadband. The simulated and measured imbalance agree, while the worst case discrepancy
is below 1 dB out-of-band in hybrid Sonnet case. The hybrid Sonnet simulation (considered
to be least accurate so far) is the only simulation that predicts 1.7 dB measured imbalance
around 23 GHz. For same reasoning applied to rat-race coupler the CMRR and isolation are
simulated only (Fig. 4.58). The CMRR curve re-confirms the high and broadband balancing
seen already at Fig. 4.57. Since the transformer is a 3 port the isolation is low: circa 7.5 dB
at the center frequency. The odd-mode output return loss (Fig. 4.59) was extracted with
hybrid simulation-measurement approach as shown on Fig. 4.39. There is a good simulation-
78
Balun
Figure 4.55: Xformer-Down Even-mode Complex Input Reflection Coefficient
Figure 4.56: Xformer-Down Insertion Loss: Input Even-Mode to Output Odd-Mode
measurement agreement with worst-case simulation-measurement discrepancy of 2 dB.
Transformer Insertion Loss Contributors Breakdown Several Full CST simulations were run
to quantify insertion loss contributors:
Simulation “as is” yields insertion loss of 4.9 dB.
Simulation with the metal replaced by perfect electric conductor (PEC) yields insertion
loss of 3.8 dB (i.e. no conductor losses included).
Simulation with open/magnetic boundary yields insertion loss of 3.5 dB (i.e. no substrate
losses, since the field doesn’t penetrate into substrate due to the enforced boundary
condition).
The simulations’ results are summarized for convenience in table 4.4.
79
Design of Circuits
Figure 4.57: Transformer Imbalance
Figure 4.58: Transformer Simulated CMRR and Isolation
Table 4.4: Transformer Balun Insertion Loss Contributions Breakdown – EM Simulation with
CST
Contributor [dB]
Ideal Power Division 3
Metal (Conductor) 1.1
Dielectric (Substrate) 0.3
Radiation, other 0.5
Total 4.9
80
Balun
Figure 4.59: Output Odd-Mode Reflection Extracted from 2 Measured Transformers
Transformer Simulation Overview
Hybrid Sonnet: this is the fastest EM simulation (the recommended Sonnet coarse mesh-
ing and fine edge meshing setting was selected as a reasonable trade-off between accuracy
and run-time). In most cases the results using this approach are slightly less accurate
relative to the both CST approaches, however the absolute discrepancy is not large (up
to 1.5 dB – worst case, out-of-band).
Hybrid CST: quite accurate results were obtained in this case, while being more resource-
demanding simulation than Sonnet (it is a full 3D simulation opposed to 2.5D of Sonnet).
Full CST: the accuracy is often best in this case, while being by far the most resource-
demanding simulation. The full 3Dmeshing of the whole transformer core with the
matching networks seriously increases the numerical complexity of the problem (which
at the end penalizes accuracy when limiting run-time bounds).
All of the approaches yield good agreements with measurements. Leveraging the effort between
EM and circuit simulators seems optimal: the circuit simulator is most efficient while dealing
with PDK models of transmission lines, capacitors, etc., while EM simulation (either of them)
lends itself well for such EM problems as transformer core.
4.2.6 Balun Overview and Discussion
Traditional active balun’s biggest drawback is the inherent topology asymmetry at high oper-
ating frequencies that directly translates into amplitude and phase imbalance, or poor CMRR
(table 4.5). As shown here, the inherent imbalance of a singly-ended driven differential stage
can be compensated in a following custom-designed buffer stage. This results in a wide-band
balancing, peaking at the frequency of interest. The noise figure of the active balun presented
is circa 4 dB higher than of its passive counterparts (due to noise contributions from several
active devices), so its deployment in the RF path is not recommended.
81
Design of Circuits
The oP1dB in the presented design is sufficient to keep the mixer properly operating. The lim-
ited headroom (caused by emitter-follower buffer inclusion) can be compensated by increasing
the bias current. As any other active circuit it suffers from relative design complexity due to
multiple active devices, and power dissipation.
Table 4.5: Balun Comparison Table
ActiveaRat-Race Transformer
Amplitude Imbalance [dB] 0.1 1.1 -0.25
1-dB Amplitude Imbalance BW [GHz] 20 6 73
Phase Imbalance [◦] 2 7 -5
5◦Phase Imbalance BW [GHz] 37 8 60
NF [dB] 8.7 4.5 4.5
Gain [dB] 1.8 -4.5 -4.5
Isolation [dB] 12 28 7.5
oP1dB [dBm] -0.2 – –
PDC [mW] 220 – –
Chip Size [µm2] 678 x 390 500 x 350 170 x 230
aThe active balun performance is simulated only.
The passive approach yields moderate, close to theoretical loss (corresponding to low noise
figure) and, most importantly, excellent CMRR, which is the balun’s most important quality.
At the same time, if designed properly, an excellent match can be achieved. Rat race has
the advantage of excellent isolation between the outputs (due to an additional, 4th terminal).
The balancing of the rat race is less broadband than of the other two baluns because of use of
resonator-like elements. The reduced-length rat race offers area reduction compared to classical
rat race as explained in detail.
The transformer balun occupies smallest area among the three and still possesses the excellent
balancing, while being the most wide-band structure (compared to the other 2 options). A
synthesis procedure that decouples between transformer magnetic coupling factor optimization,
losses and CMRR has been deployed. The transformer has a drawback of output isolation
of only 7.5 dB. All the advantages of transformer based balun outweigh its’ drawback and
therefore, it is the most attractive solution for the deployment in mixer, 1- and 2- channel
receivers. Since the rat-race baluns were characterized first it was decided to deploy them
instead for risk-management reasons.
82
Mixer
4.3 Mixer
A mixer translates the signal from one frequency to another. For the first time a mixer was
used by Armstrong in 1918 in his invention of super-heterodyne receiver [2]. A direction finding
received signal was normally amplified and processed at the RF. This was problematic, since
the early vacuum tube triodes of that era had low gains at operational frequencies of 1.6 MHz.
Hence Armstrong suggested that the signal was down-converted to low frequencies, where the
gain was abundant.
In a down-converter mixing application a difference frequency (also known as the Intermediate
Frequency – IF) between RF and local oscillator is produced (LO):
fIF =|fRF −fLO|(4.17)
Proper mixing operation is achieved by appropriate deployment of circuit (time-varying) non-
linearities. There are several ways to realize a mixer and the most common are:
additive mixing. A 2-port (such as diode) is assumed here as the nonlinear device: the
RF and LO excitations are applied in series to a input port of the non-linearity while at
the output port the IF is extracted
multiplicative mixing. Here a 3 port is needed, such as transistor. RF, LO and IF then
can be assigned to a separate port each
4.3.1 Main Requirements Imposed on Mixer
Noise Figure. The LNA according to section 4.1 has low gain, therefore mixer noise
contributions become more critical (compared to low frequency case). There is a high
emphasis on low noise design of the mixer in this work.
Conversion Gain (CG). One of the most fundamental metrics of the mixer is how well it
translates power from the RF port (excited at RF frequency) to the IF port:
CG = 10 log PIF
PRF (4.18)
Like in the LNA case, section 4.1, on one hand the mixer CG should be high to reduce the
IF stage and ADC noise contributions. On the other hand, also here gain and linearity
come at each other’s expense.
Linearity. An amplified signal after the LNA should not saturate the mixer. The linearity
cascade (equation 4.19 [105]) shows that in order to have equal contributions the linearity
of each subsequent case must be scaled by the preceding stages voltage conversion gain:
1
(iIP3total)2=1
iIP32
1
+G1
iIP32
2
+G1·G2
iIP32
3
+··· (4.19)
so the mixer linearity requirements are stricter than the linearity of the LNA.
83
Design of Circuits
Isolation. For a proper function of a mixer RF, LO and IF ports must be sufficiently iso-
lated from each other. This is especially critical for the LO excitation, which is constant
large-signal excitation and also for the RF, which can be operated in the large-signal
region. The multiplicative mixing type is generally preferable to additive mixing since
RF, LO signal and IF can be coupled to different ports of the transistors, and hence are
physically isolated.
Other mixer design considerations will be outlined in the following subsections. In the PDK
used the Schottky diodes were not recommended by the foundry. Therefore a diode mixer was
not considered and the focus was on active HBT-based mixers.
4.3.2 Mixer Balancing Approaches
All the mixer circuits in Fig. 4.60 consist of 2 main circuit parts:
an RF path amplifier, called transconductor (TRC) – translates input voltage excitation
into current
transistor (or pair or quartet) where the actual mixing takes place, called mixer core
3 main balancing schemes are considered:
Unbalanced (Fig. 4.60a). The unbalanced topology was historically used in discrete de-
signs mainly due to unavailability of multi-transistor packages (having matched devices).
The main drawback of the unbalanced configuration is the coupling between all ports.
The advantage of the unbalanced arrangement is lower DC consumption. Only a half of
a duty cycle is used for the LO and the RF inputs each, thus it possesses worse perfor-
mance metrics of gain and linearity. The noise figure of the unbalanced active mixer is
the worst due to strong common node [65]. Therefore in the vast majority of the designs
balancing is used.
Single-Balanced (Fig. 4.60b). Here the IF is isolated from RF due to the balancing. As
a result, the core’s common mode noise conversion from RF to IF is canceled out. As it
can be shown for a differential amplifier and a single-balanced mixer [83]:
iIF ,iIF+ −iIF- =I0tanh vLO
2VT+gm TRC vRF tanh vLO
2VT(4.20)
where I0
2is the quiescent bias current flowing through each core transistor, gm TRC is
the transconductance of transistor Q3 (the transconductance stage itself), vRF and vLO
are the input RF and LO voltages and VT=KT
qis the thermal voltage. The first term
is an undesired LO leakage to IF and the second term is the desired mixing product.
Compared to the unbalanced case the linearity is doubled and so is the DC consumption.
The advantage of single-balanced topology compared to double balanced are half the
current consumption and half the TRC stage noise contribution to the output (due to a
presence of a single TRC only).
84
Mixer
Double-Balanced (Fig. 4.60c). All ports are mutually isolated. In this case it can be
shown [83]:
iIF = 2gm TRC vRF tanh vLO
2VT(4.21)
So the LO feed-through to IF is eliminated and thus the LO-related amplitude and
common mode noise are rejected. Compared to the single-balanced case the linearity is
doubled and so is the DC consumption. Therefore the double balanced topology for the
active mixer is selected. The additional bias current (for additional branch) seems like a
reasonable price to pay for noise and linearity performance improvements.
IF
Q1
Vcc
LO
RF Q2
(a) Unbal-
anced
IF+
Q1
Vcc
LO+
IF-
Q2
Vcc
LO-
RF Q3
(b) Single-Balanced
IF+
Q1
Vcc
LO+ Q2
LO-
RF+ Q5
Q3
IF-
Q4
Vcc
RF-Q6
LO+
(c) Double-Balanced
Figure 4.60: 3 Basic Active Mixer Balancing Approaches
4.3.3 Transconductance Stage
Topology Selection
Since mixer core noise performance is very critical, the transconductance is an amplification
stage in attempt to suppress the noise contribution of the mixer core. Additionally, the TRC
stage contributes to isolation of the mixer core from the LNA. Therefore similar considerations
as in LNA topology choice apply here also. As a logical consequence, it was decided to have
85
Design of Circuits
a replica of the LNA as the transconductance stage. This design decision had an additional
advantage of design confidence (since the LNA was already characterized at the stage of mixer
design).
Common Mode Suppression Techniques Overview
As mentioned in previous subsection, the proper balancing is crucial when noise optimization
is performed. The following common-mode termination variants were considered for the TRC
stage:
Current Source (Fig. 4.61a). This is the traditional common mode termination for a low-
frequency differential stage: the high impedance provided by the current source improves
the stage’s CMRR. The current source normally deploys large transistor sizing to reduce
its voltage headroom drop. At high frequencies the current source is shunted by the
parasitic capacitance thus reducing the potential CMRR improvement benefits.
Resonator (Fig. 4.61b). Resonator seems like a more appropriate CMRR improvement
structure at high frequencies. The high impedance of the common-mode is provided
directly at high frequencies (and the coil serves as ground DC return path). The draw-
back of this approach is the added area (a double-balanced mixer would need 2 such
resonators).
Ground (Fig. 4.61c). This provides the simplest ground DC return path realization. No
TRC CMRR improvement steps are made by grounding the common-mode. However,
the baluns presented in section 4.2 have excellent CMRR performance, which need not
to be improved further. This termination was selected for the common-mode.
Q1 Q2
RF+ RF-
to mixer core
(a) Current Source
Q1 Q2
RF+ RF-
to mixer core
(b) Resonator
Q1 Q2
RF+ RF-
to mixer core
(c) Ground
Figure 4.61: Various Differential Pair Common Mode Terminations
4.3.4 Mixer Transconductance-to-Core Interface
Analog and high frequency design offer several methodologies for coupling TRC to the core:
86
Mixer
Gilbert cell (Fig. 4.62a). One drawback of the Gilbert cell is that the current sink,
transconductance, the switching stage and the load resistors are stacked. This directly
limits the linearity of the overall mixer, since the available voltage headroom to the mixer
core is a fraction of the Vcc. The other drawback of the traditional Gilbert cell stems from
DC-coupling between the transconductors and the core stage. This enforces that each
mixing-core transistor is biased at half bias current of the transconductor transistor.
Ideally, the bias of the core and the transconductance should be able to be adjusted
separately, i.e. having a degree of freedom in choosing the bias points (and sizings) of
different functional blocks could be of benefit. Namely, the transconductance should be
biased and sized for low noise (low current density) and the core – for linearity (higher
current), while still trying to reduce the noise (since the transconductance doesn’t have
much gain at high frequencies).
Folding (Fig. 4.62b, 4.62c). This approach offers the TRC the full voltage swing (exclud-
ing the drop on the current sources) independently from other stages and leave higher
headroom for the mixer core and the IF loads. The NPN CE transconductance interfaces
the PNP-based switching stage. An additional benefit is that TRC and core operation
points can be set separately. Unfortunately, due to poor PNP devices performance at
77 GHz it was not a viable approach in this frequency range.
Current boosting (or current “bleeding”) (Fig. 4.63a, 4.63b). In this case the design
approach where the switches are designed to be smaller than the transconductors is
adopted. To reduce the flicker noise of the core their collector current is reduced. Current
boosting is an elegant solution that solves this by routing the unused DC from the
transconductors through external current source / sources. These current sources can
be applied to both transconductors collectors as shown in Fig. 4.63a, in this case the
additional capacitances (typical to DC current sources) load the core input. This parasitic
capacitance is screened by the virtual ground by exploiting the differential nature of the
circuit and feeding a single boosting current source to the middle tap of the inductor
as shown on figure 4.63b. In this case the noise contribution of the boosting current
source is common mode and canceled at the differential IF interface (unlike the case of
fig. 4.63a, where the 2 branch noise sources are uncorrelated and add up).
AC-Coupling. Here a different solution was adopted – a capacitive AC-coupling between
transconductance and the core (Fig. 4.63c). This approach also offers the TRC and the
mixer core with the IF loads the full voltage swing each. Another realization of the
AC coupling would be transformer-coupled stages (Fig. 4.63d) [73]. This option has the
advantage of using the center of the primary turnings (a virtual ground node for the RF
excitation) to provide the supply biasing for the transconductance stages.
87
Design of Circuits
IF+
Q1
Vcc
LO+ Q2
LO-
RF+ Q5
Q3
IF-
Q4
Vcc
RF-Q6
LO+
(a) Gilbert Cell
Q1
Vcc
LO+ Q2
LO-
RF+ Q5 Q3
IF-
Q4 RF-Q6LO+
IF+
(b) Folding – Current Sources
Q1
Vcc
LO+ Q2
LO-
RF+ Q5 Q3
IF-
Q4 RF-Q6LO+
IF+
(c) Folding – Resonator
Figure 4.62: Various Transconductance-to-Core Interfaces
4.3.5 Mixer Core
Core Transistors’ Sizing
Due to AC coupling of mixer core its sizing and biasing can be decoupled from the TRC.
Therefore the core was optimized stand alone with 50 Ω input termination. A λ/4 line and a
series 2 pF were used as ground DC return path and the AC coupling, respectively. The base
current was supplied through 1 kΩ resistors in order not to load the bases of the core. Since
these resistors are in shunt, their contribution to overall noise figure is negligible.
88
Mixer
IF+
Q1LO+
IF-
Q2
Vcc
LO-
RF Q3
(a) Current Boosting – for
each Transconductance
IF+
Q1
Vcc
LO+ Q2
LO-
RF+ Q5
Q3
IF-
Q4
Vcc
RF-Q6
LO+
Vcc1
(b) Current Boosting – at Virtual Ground
IF+
Q1
Vcc
LO+ Q2
LO-
RF+ Q5
Q3
IF-
Q4
Vcc
RF-Q6
LO+
Vcc
(c) Capacitive Coupling
IF+
Q1
Vcc
LO+ Q2
LO-
RF+ Q5
Q3
IF-
Q4
Vcc
RF-Q6
LO+
Vcc
(d) Transformer Coupling
Figure 4.63: Various Transconductance-to-Core Interfaces - cont.
Core transistor sizing is analyzed in bottom-to-top fashion. First, various noise contributors
for each mixer core transistor are shown in table 4.6 over various core size and bias values. The
contributors are displayed in dynamic range of 30 dB. The noise contributions are referenced to
the input since this allows the comparison between various cases (by taking out the dependence
on conversion gain). Several observations can be made:
“Sanity check”: the various inter-transistor noise contributors are independent and in-
deed add up to the total noise value:
1.252u0.812+ 0.552+ 0.492+ 0.482+ 0.312+ 0.212(4.22)
1.252u1.569 (4.23)
(the check was performed for the 8-cell sizing, 14.4 mA overall core bias current).
The current density for all sizings was retained the same. In general, the different con-
tributors for all sizings are quite balanced, which is a sign of an optimal design.
89
Design of Circuits
The transistors have lowest noise contributions for 4-cell sizing, while 8-cell and 2-cell
core are comparable noise-wise.
All the contributors are similar apart from the 8-cell, 14.4 mA case, where due to tran-
sistor size and higher bias the collector shot contribution is higher.
The smallest devices were not considered for the core since process spread could contribute to
imbalance and eventually, to performance degradation.
Table 4.6: Core Transistors’ Input-referenced Major Noise Contributions’ Breakdown
Cells
Bias Each itzf flicker rbi rbx re ibe
Transistor (Collector, ibe (Thermal, (Thermal, (Thermal, (Shot
Total Shot) Base Base Emitter Base)
Noise Intrinsic Extrinsic Resistor)
Resistor) Resistor)
[mA] hnV
√Hz i hnV
√Hz i hnV
√Hz i hnV
√Hz i hnV
√Hz i hnV
√Hz i hnV
√Hz i
8
14.4 1.25 0.81 0.55 0.49 0.48 0.31 0.21
10.5 1.10 0.76 0.47 0.41 0.41 0.26 0.18
6.2 0.96 0.7 0.36 0.33 0.32 0.22 0.15
4
7.1 1.03 0.64 0.56 0.37 0.38 0.25 0.19
5.2 0.98 0.62 0.47 0.36 0.36 0.23 0.16
3.1 0.87 0.60 0.33 0.33 0.34 0.22 0.12
2
3.57 1.20 0.64 0.68 0.45 0.47 0.31 0.20
2.62 1.15 0.65 0.58 0.46 0.47 0.31 0.17
1.57 1.02 0.65 0.42 0.45 0.44 0.30 0.13
Secondly, it was crucial to see how the core transistors’ noise compare with the other noise
sources, such as input port and load noise (table 4.7). Several observations can be made here
as well:
“Sanity check”: the core noise contributors are independent and indeed add up to the
total noise value:
2.72u4·1.252+ 0.812+ 0.592(4.24)
2.72u7.254 (4.25)
(the check was performed for the 8-cell sizing, 14.4 mA overall core bias current).
The core consists of 4 independent transistors, so the overall transistors noise contribution
is larger than the ports’ noise contributions.
Due to increase of gain with the transistor sizing the load noise contribution related to
the input goes down.
90
Mixer
The change of input port noise contribution indicates change of mixer input impedance
with the transistor size and bias sweep. This is due to lack of additional matching circuit
between the core and the TRC. This change is not significant, though.
Table 4.7: Core Input-referenced Major Noise Contributions’ Breakdown
Cells
Bias Gvoltage Total Each Input RLOAD
Noise Transistor Port
Total
Noise
[mA] [ ] hnV
√Hz i hnV
√Hz i hnV
√Hz i hnV
√Hz i
8
14.4 2.12 2.7 1.25 0.81 0.59
10.5 2.02 2.42 1.11 0.82 0.62
6.2 1.86 2.19 0.96 0.81 0.67
4
7.1 1.74 2.43 1.03 0.88 0.72
5.2 1.63 2.34 0.98 0.88 0.77
3.1 1.48 2.22 0.87 0.84 0.84
2
3.57 1.32 2.73 1.20 0.89 0.95
2.62 1.21 2.70 1.15 0.88 1.03
1.57 1.08 2.61 1.02 0.81 1.16
Thirdly, mixer core linearity and gain performance is shown alongside core noise performance
as function of core sizing and bias (table 4.8). Unlike the noise figure, the gain and linearity
monotonically increase with bias and core up-sizing. The NF of the 8-cell core at the highest
bias current is 2 dB worse compared to the minimum NF case, however the 8-cell core has
7.5 dB higher linearity, and 3 dB higher power gain. The benefit of having much higher linearity
out-weighted the noise optimization. Therefore the core was realized with 8-cell devices to be
operated at higher bias. Mixer NF is improved by having the transconductance stage in front
of the core. An optimization of DC return path (chosen as λ/4) and the AC-coupling capacitor
(2 pF) could have yielded better performance, for example a shorter microstrip line would act
like an inductor and resonate out some of the switches’ capacitance. Due to limited time, this
optimization did not take place.
LO Interface
Switching the mixer with sufficient LO power is crucial for proper mixing operation with
regard to all performance criteria [65], [83]. Two main different approaches to mixer LO port
interfacing were identified:
Active, buffered interface [34], [81] – common collector (CC) stages preceding the core
bases. A typical CC stage is presented on Fig. 4.64 (the current sources can be replaced
by resistors or resonators). The CC stage has:
91
Design of Circuits
–high input impedance so it could properly load a differential amplifier, which could
be used either as active balun or an amplifying stage;
–low output impedance, being effectively a LO voltage source driving the core bases
(an HBT ideally is a voltage controlled current source).
Vcc
IN
OUT
Vcc
Q1
Q2
(from LO
BALUN)
(to mixer
LO interface)
Figure 4.64: LO Common-Collector Buffer
LO matching [65], [51], [57], [54]. The previous approach originates in analog design,
where parasitics are less explicit. At higher millimeter-wave frequencies parasitic capac-
itances come into play. In case of CC this would mean shunting (reduction) of input
impedance and an additional imaginary output impedance part, limiting the voltage
swing. The core transistors also have parasitics, further lowering the voltage swing by
introducing an additional complex part to its input impedance. This solution comes to
solve it with traditional RF means of resonating out all the complex impedance parts.
The fundamental difference to the previous case is that here LO voltage is divided be-
Table 4.8: Simulated Core Performance vs. Size and Bias Sweep
Cells Bias NFSSB iP1dB Power Gain
[mA] [dB] [dBm] [dB]
8
14.4 13.5 1 3.5
10.8 12.4 -1.5 3.1
7.5 11.7 -3.6 2.4
4
7.15 11.87 -3.3 1.8
5.38 11.5 -4.5 1.25
3.75 11.4 -6.5 0.4
2
3.57 12.8 -6 -0.6
2.7 12.75 -7.5 -1.3
1.9 13 -9.5 -2.3
1
1.8 15.1 -9.3 -3.6
1.35 15.4 -11.5 -4.4
0.96 16 -12 -5.5
1 6.14a17.6 -2 -1.3
aHere the 4 core transistors are biased close to the maximal allowable current 1.8 mA per cell.
92
Mixer
tween the LO source and the core LO input while in the previous, CC case ideally all
the available LO voltage is applied to the core. (As explained, in the high-frequency case
there is voltage drop due to Op-Amp, buffer and core transistors’ parasitics).
Since this mixer is a basic building block and the end goal is the 2-channel receiver, none of
these approaches were used. LO CMRR is being taken care of by a balun, that feeds directly
the core bases. The balun has 50 Ohm interfaces and no additional impedance matching for
either maximal power transfer or maximal voltage on the core transistors’ bases took place.
The mixer was characterized with LO of circa 4 dBm and no significant performance change
was observed in the vicinity of this LO power so it was concluded that LO-wise the switches
are saturated enough. Deploying matching approach the needed LO power could have been
reduced by circa 1.5...2 dB but LO power optimization was not the objective of this design.
4.3.6 Mixer IF Interface
IF – Post-Mixer Buffering
On-chip IF active buffering could lead to being the source for the overall linearity degradation
(since the buffers are the last stage in the chain from conversion gain point of view). The
main reason behind IF buffering is the IF-RF and, to a lesser extent, IF-LO isolation specs –
so that a disturbance from the IF side does not appear at the RF/LO ports and corrupts the
performance. Good IF-RF and IF-LO isolation is achieved due to availability of good baluns
at the LO and RF ports (section 4.2), respectively and due to good frequency separation
(IF<300 MHz; RF, LO= 77 GHz). Therefore like in [20], [98], [40] the on-chip IF buffering
was omitted in order not to limit linearity. For the measurement purposes to allow a proper full
3 port differential operation of the double-balanced mixer an external IF Op-Amp was deployed
as part of the measurement setup (Fig. 4.69, 4.73). In subsection 4.3.8 the importance of IF
balun is elaborated.
Mixer IF Interfaces Overview [49]
A typical voltage mode IF interface is an RC network, also being a first filtering stage
for baseband (Fig. 4.65a). The pole improves mixer’s out-of-band blocking performance
and reduces out-of-band blocking requirements on the following baseband chain. As any
resistive load, it suffers from headroom limitation problem – not the full Vcc is available
to the mixer core, but Vcc −Ibias ·Rload. This headroom problem is especially pronounced
for high voltage gain mixers, where Rload is high, so the resulting linearity suffers. Mixers
with high bias current with voltage mode RC load suffer from a similar problem, as well.
The high bias current and / or high load vs. low headroom trade-off can be avoided using
direct current source interface. The DC current sources set quiescent operation point to
the mixer (with headroom available to the mixer limited by current source voltage drop)
and the load resistors setting the AC gain (Fig. 4.65b). The linearity of analog to digital
converter (ADC) limits the load resistor value.
93
Design of Circuits
The mixer can be deployed in current mode: keeping in mind that the core primary output
is RF current, so the voltage swing there is very small. Mixer outputs can be connected to
the Op-Amp virtual grounds and the voltage is formed on the Op-Amp feedback resistors
(Fig. 4.65c). Such current mode approach especially suits high linearity and low-voltage
applications, because there is little voltage swing at the mixer output.
Approaches deploying dedicated current sources suffer from its noise coupling directly to
mixer’s output. Therefore straightforward passive RC load approach was adopted (Fig. 4.65a).
Vcc
C R R C
from mixer core collectors
−
+
off-chip
IF+
IF-
OpAmp
ADC
(a) Voltage Mode: RC load
Vcc
R R
from mixer core collectors
−
+
off-chip
IF+
IF-
OpAmp
ADC
(b) Voltage Mode: R and Current Source load
Vcc
from mixer core collectors
−
+
off-chip
IF+
IF- OpAmp ADC
R
R
(c) Current-Mode: using an Op-Amp
Figure 4.65: Various Mixer IF Load Interfaces
Mixer IF Interface Design
The IF load to the mixer offered by the RC network is:
ZIF =R
1 + j2πfRC =R
1 + jf
fcutoff
(4.26)
The chosen values are: R= 100 Ω, C= 800 fF, so the resulting fcutoff = 2 GHz. This RC
choice allows for sufficiently wide IF bandwidth. The RF frequency is more than 5 octaves
above the cutoff frequency, so circa 30 dB of RF suppression can be expected at the IF. The
transistor parasitics are much smaller than C so can be absorbed in it and don’t affect the IF
load calculations.
94
Mixer
4.3.7 Realized Mixer
The schematics of the realised mixer is shown at Fig. 4.66. An RF balun converts the single-
ended signal into differential, it is amplified by a differential TRC stage. For proper differential
operation both bases and collectors supplies are tied together (so common mode is canceled in
both cases). The differential TRC stage is AC-coupled to a double-balanced mixer core stage,
whose base and collector supplies are also tied together. The LO feeds the core bases through
a LO balun. The I/O in the mixer layout (Fig. 4.67) are as follows: single-ended RFin is in
the east, LOin – in the west, DC comb – in the north and in south there are the differential IF
outputs. λ/4 DC return path of the core was bended in order to save area. Several shunting
1 pF capacitors are dispersed in the DC distribution path. The main area contributors are the
RF and LO rat-race baluns and the series input match of the TRC stages.
Ibb_TRC
Ibb_core
Vcc_core
RFin
IF+
IF-
LO
Vcc_TRC
20 Ω
4 pF 4 pF
4 pF4 pF
2 pF
2 pF
6 pF 4 pF
4 pF
0.8 pF
0.8 pF
6 pF
5 Ω
20 Ω5 Ω
1k Ω
1k Ω
100 Ω
100 Ω
λ/4
λ/4
Q1
Q2
Q3
Q4
Q5
Q6
Mix Transconductance Mix Core
Figure 4.66: Detailed Mixer Schematics
4.3.8 Noise Figure
To analyze system performance each component must be treated as “black box”, described
by its external parameters (such as gain, noise) and not as a circuit. For this end what is
important is how much noise the circuit generates and less what is the nature of the noise.
The noise power a resistor generates is KTB. A physical quantity that is proportional to
amount of noise power the resistor generates is called noise temperature. Noise temperature
95
Design of Circuits
Figure 4.67: Mixer Layout
can be used to specify the noise generated in any two- (or multi-) port component. In case of
mixers the responses at different frequencies can be treated as separate ports.
Often a noisy two-port is represented as a noiseless 2 port with an equivalent noise source at
the input (with noise temperature of TN) (Fig. 4.68):
TL=GT·(TS+TN) (4.27)
where TLis the output noise temperature, TSis the input noise (either from a termination or
a previous stage) and GTis the two-port gain. A handy method of characterizing component
TS
TN
Input Noise
Two-Port Noise
Noiseless
Two-Port
GT
TL
Output Noise
Figure 4.68: Noisy 2-Port as Noiseless 2-Port with an Additive Noise Source [65]
noise is the concept of a noise figure (NF) or a noise factor (F) [65], [78]. Noise factor was
96
Mixer
originally conceived as the input signal-to-noise ration divided by the output signal-to-noise
ratio. This definition of noise factor is not unique unless the input noise level is defined.
The alternative definition is the total input noise temperature divided by the input noise
temperature due to the input noise source while it is fixed at temperature of T0(290 K).
F=TN+T0
T0
=TN
T0
+ 1 T0,290 K (4.28)
Equation 4.28 assumes TS=T0= 290 K.
Noise Figure is the logarithmic representation of the noise factor:
NF = 10 log(F) (4.29)
DSB vs. SSB Noise Figure Definitions
In most receivers (apart from zero-IF) two different frequencies are converted to IF: the RF
frequency and the so-called image frequency. Without loss of generality, in case of high-side
injection (where the LO is higher than the RF, fLO =fRF +fIF) the image frequency is
fimage =fRF + 2fIF. This non-linear effect is not included in linear definition of the noise
figure (equation 4.28) so this enables several possible noise figure sub-definitions. Two of them
are:
Double Sideband Noise Figure (NFDSB): It is assumed that both the RF and the image
frequencies contain useful signal and noise. The DSB definition apply, for example, in
radiometry, noise measurements and double-sideband amplitude modulated cases.
Single Sideband Noise Figure (NFSSB): while the noise (like in DSB case) covers the RF
and image frequencies, the signal is assumed to be only at the RF. For spectral efficiency
reason SSB definition directly applies to FM receivers in general, and to this automotive
RADAR receiver in particular. Since in low IF, high RF case both RF and the image
channels have very similar conversion gain, in the DSB case the signal power is twice of
the SSB case:
NFSSB = NFDSB + 3 [dB] (4.30)
Noise Figure Measurement Setup
As presented in Fig. 4.69 the NF is measured fully differentially regarding all the 3 terminals
(RF and LO have on-chip baluns and there is an external IF active balun in the measurement
setup). NF can be measured in a single-ended fashion (regarding the IF) by grounding one
of the active balun inputs. DC biasing of the mixer is omitted for clarity. In the presented
measurement configuration a NFDSB is measured since the noise source (used as RF input)
is broadband enough to cover the image channel and there is no dedicated image-reject filter
(either off- or on-chip). Like in the LNA case, NF and linearity measurement setup included
a narrow-band Gunn Oscillator (as the LO source) so these measurements are available at
77 GHz only.
97
Design of Circuits
LO
RF IF+
IF-
LO Source
Variable
Attenuator
Noise
Source
IF Amp
Differential-in
SE-out
−
+
Spectrum
Analyzer
DUT
Figure 4.69: Mixer/Down-converter Noise Figure Measurement Set-Up
Noise Figure: Single-Ended vs. Differential
The mixer noise figure was measured both in single-ended and differential configurations (re-
lated to IF). In a single ended case the NF was circa 20 dB worse then the differential and this
observation prompted a detailed investigation.
The DC path return λ/4 lines must be reconsidered (Fig. 4.66). They retain their impedance-
inverting properties only at RF, being high ohmic loads while at low frequencies they are
essentially low ohmic. Therefore, λ/4 lines are RF chokes only (and not IF chokes). This
would cause an undesirable behavior of the mixer to LO-port excitation at IF frequencies. For
such an excitation the core no longer retains the characteristics of a differential amplifier, since
the LO common node is shorted. This hypothesis lead to a series of simulations. In simulation
it was relatively easy to provide a high common mode impedance for the DC current return
path at the core emitters. Ideal chokes of 1 kH were deployed in simulation, being both RF
and IF chokes. The dominant noise contributors were analyzed for 4 cases: the RF-choke and
λ/4 LO common terminations in single-ended and differential IF coupling each (table 4.9).
Here is a comparison of a different output noise voltages contributors:
TRC: is same in all cases. The TRC noise contribution to the output in differential cases
doubles (compared to SE case), but so does the signal. It is important to mention that in
all the cases the TRC common mode noise is suppressed due to good RF and LO baluns’
performance.
Core: the λ/4, SE case each core contribution is significantly higher than the rest of
cases. This is due to 2 main contributors: base flicker and shot noises, which are also
significantly higher than in the other cases. Those are both LO-input related common-
mode noises that are not rejected due to poor common-mode suppression at IF.
Resistors: LO 1 kΩ and LO input 50 Ω – also much higher in the λ/4, SE case. Their
odd-mode IF thermal noise is converted into common-mode at IF (due to poor balance
98
Mixer
Table 4.9: Mixer’s Output Port Major Noise Contributions’ Breakdown – DIFF vs. SE, choke
vs. λ
4for core bias of 14.4 mA
Contributorsaλ
4, SE λ
4, DIFF 1 kH, SE 1 kH, DIFF
TRC
itzf (collector shot) 1.5 2.8 1.4 2.82
ibe (base shot) –b1.7 0.85 1.69
rbx (base thermal, extrinsic) – 1.5 0.76 1.51
rbi (base thermal, intrinsic) – 1.2 0.61 1.23
re (emitter thermal) – 0.7 0.39 0.77
rbp (PNP base thermal) – 0.7 0.34 0.68
flicker ibe – 0.3 0.2 0.29
total (each TRC) 2.1 4 2 4
Core
itzf (collector shot) 3.6 2.75 0.83 1.61
ibe (base shot) 6.3 1.4 0.7 0.47
rbx (base thermal, extrinsic) 1.8 1.1 0.53 1.04
rbi (base thermal, intrinsic) 1.9 0.9 0.53 1.0
re (emitter thermal) – 0.6 0.34 0.68
rbp (PNP base thermal) – 0.64 – –
flicker ibe 20.1 0.3 2.2 1.24
total (each Core) 21.6 3.55 2.57 2.65
RFin Port – 2.7 1.37 2.73
LO Port 5.6 – – –
LO 1kΩ Resistors 7.2 – – –
RLOAD – 1.24 1.23 1.25
Total 47.5 8.46 5.65 8.35
aAll noise contributors share the hnV
√Hz iunits.
bSince dynamic range of shown noise contributors was set to 30 dB, these contributors are smaller than the
minimal value per column.
99
Design of Circuits
at IF) and also contributes to output composite noise.
5 10 15 20 25 30
10
15
20
25
30
35
40
45
50
Core Bias [mA]
NFSSB [dB]
DIFF, λ
4
SE, λ
4
DIFF, 1 kH
SE, 1 kH
Figure 4.70: Mixer NFSSB – DIFF vs. SE, choke vs. λ
4, Bias Swept
The mixer simulated NFSSB for the 4 fore-mentioned cases is shown at Fig. 4.70 vs. the core
bias values. Both differential cases almost coincide, proving the effectiveness of the double-
balanced approach in LO common-mode cancellation. The choke SE case NF is slightly higher
than the differential cases due to coherent addition of IF signal vs. the sum-of-squares of the
noise. The λ/4 SE case is the worst.
This investigation stresses the importance of well-balanced baluns at RF, LO and IF for best
double-balance mixer performance.
Total Noise Temperature Derivation and Analysis
As it has been described in subsection 4.3.7 from a system point of view, the realized mixer
consists of two blocks: a transconductance stage (which is a replica of the LNA) and a core
(Fig. 4.66). A contribution of each of those blocks to the overall mixer’s noise is of relevance.
The ambiguity in noise figure definition (subsection 4.3.8) while describing up-/down-mixing
of noise could suggest resorting to such physical quantities as noise temperature.
The noise analysis procedure of the mixer was set as follows:
de-embedding the mixer core noise figure from mixer and TRC measurements;
estimation of the potential benefits of image-rejection to core and mixer noise perfor-
mance;
deployment of the 1-channel receiver noise figure measurements to validate the core noise
figure estimation.
100
Mixer
The mixer output noise temperature is calculated in 2 ways:
by cascading noise temperature contributions from the TRC and the core. The core NF
could not be directly measured (since core alone was not manufactured). Therefore in this
case the overall mixer output noise is represented as function of core noise temperature;
by direct calculation based on measured mixer NF.
From these two equations the core noise temperature can be calculated.
Table 4.10 shows measured noise figure value for the mixer and one of its’ sub-blocks – the
TRC (LNA replica).
Table 4.10: Mixer and its Components’ Noise Figure Summary (Measured Values)
Gain NFDSB NFSSB
[dB] ratio [dB] ratio [dB] ratio
TRC / LNA 3.4 2.19 5.7 3.72 - -
Core 4.7 2.96 NFSSB,CORE-3 FSSB,CORE
2NFSSB,CORE FSSB,CORE
MIX (TRC+Core) 8.1 6.5 9.8 9.55 12.8 19.06
To
TN,TRC
GTRC
TRC TL,TRC
TSSB, CORE
TL,CORE
CGRF,CORE
CGIMAGE,CORE
MIX
CORE
TRC
Figure 4.71: Mixer: Transconductance Stage and Core Noise Temperatures
Total Noise Temperature Derivation: Mixer Transconductance Stage and Core The noise
temperature at the TRC output is (equation 4.27):
TL,TRC =GTRC ·(T0+TN,LNA) = T0·GTRC ·FTRC = 290 ·2.19 ·3.72 = 2362.6 K (4.31)
101
Design of Circuits
since the IF frequency is very low, the conversion gain for the RF channel would be equal to
that of the image channel:
CGRF,CORE = CGIMAGE,CORE (4.32)
TRC load noise temperature is the input noise for the core. The noise is present in both
RF and image frequencies, while the SSB noise temperature has to be accounted for only RF
sideband (subsection 4.3.8)
TL,CORE = (TL,TRC +TSSB,CORE)·CGRF,CORE +TL,TRC ·CGIMAGE,CORE (4.33)
= (2362.6 + TSSB,CORE)·2.96 + 2362.6·2.96 = 2.96 ·TSSB,CORE + 13986.6 K
Total Noise Temperature Derivation: Mixer Fig. 4.72 suggests direct computation of mixer
noise temperature from the measured NF:
To
TSSB, MIX
TL,MIX
CGRF,MIX
CGIMAGE,MIX
MIX
Figure 4.72: Mixer Noise Temperature
TSSB,MIX = (FSSB,MIX −1) ·T0= (19.06 −1) ·290 = 5237.4 K (4.34)
TL,MIX = (T0+TSSB,MIX)·CGRF,MIX +T0·CGIMAGE,MIX (4.35)
= (290 + 5237.4) ·6.5 + 290 ·6.5 = 37813.1 K
De-embedding of Mixer Core Noise Temperature and Noise Figure the noise temperatures
of the core and the mixer load are equivalent (equation (4.33) and equation (4.35) are equal):
2.96 ·TSSB,CORE + 13986.6 = 37813.1 (4.36)
⇒TSSB,CORE = 8049.5 K (4.37)
102
Mixer
therefore, from de-embedded core noise temperature one can compute the core noise figure:
NFSSB,CORE = 10 ·log TSSB,CORE
T0
+ 1= 10 ·log 8049.5
290 + 1= 14.6 dB (4.38)
So here the benefit of having a low-noise stage preceding the core, even one with low gain is
apparent: the addition of the low noise TRC stage allows reduction of the overall NF from
14.6 dB to 12.8 dB.
Passive on-chip realization of image rejection (such as band-stop filter) is not feasible due to
low on chip quality factors. Several active image reject architectures are feasible, the most
common are Weaver [108], Hartley [39]. The use of active image reject approaches is linked
with high circuit level complexity, therefore first the theoretical benefits of image rejection are
to be investigated.
Case Study
1: Image Rejection – before the Mixer In this case, by definition:
CGIMAGE,MIX = 0 (4.39)
⇒NFSSB,MIX, no image = NFSSB,MIX + 10 ·log TL,MIX, no image
TL,MIX
(4.40)
= 12.8 + 10 ·log (290 + 5237.4) ·6.5 + 290 ·0
(290 + 5237.4) ·6.5 + 290 ·6.5
= 12.8 + 10 ·log 35928.1+0
35928.1 + 1885
= 12.8−0.2 = 12.6 dB
The ambient noise is much lower than the mixer noise, so there is no benefit in placing the
image rejection before the mixer.
Case Study
2: Mixer Image Rejection after TRC, before Core In this case, by definition:
CGIMAGE,CORE = 0 (4.41)
so:
TL,CORE, no image = (TL,TRC +TSSB,CORE)·CGRF,CORE +TL,TRC ·CGIM,CORE (4.42)
= (2362.6 + 8049.5) ·2.96 + 2362.6·0 = 30820 K
103
Design of Circuits
⇒NFSSB,MIX, no image = NFSSB,MIX + 10 ·log TL,CORE, no image
TL,CORE
(4.43)
= 12.8 + 10 ·log (2362.6 + 8049.5) ·2.96 + 2362.6·0
(2362.6 + 8049.5) ·2.96 + 2362.6·2.96
= 12.8 + 10 ·log 30820 + 2362.6·0
30820 + 2362.6·2.96
= 12.8−0.89 = 11.9 dB
so NFMIX could have been improved by circa 0.9 dB were the image rejection deployed before
the core. The ambient noise (that is equally present in the RF and the image channels)
amplified by the transconductance stage, so the noise at the image band is 4.3 times lower
than the RF band noise. Therefore there is small benefit in placing the image rejection before
the core. For this reason no image rejection was deployed in the mixer case.
4.3.9 Linearity
Linearity Measurement Setup
Mixer linearity measurement setup (Fig. 4.73) is similar to the noise figure setup on Fig. 4.69.
RF source differs – instead of noise source there is an narrow-band Gunn oscillator. The
amplitude of signal available from the oscillator was controlled with adjustable attenuator.
LO
RF IF+
IF-
LO Source
Variable
Attenuator
IF Amp
Differential-in
SE-out
−
+
Spectrum
Analyzer
DUT
Variable
Attenuator
Frequency
Source
Figure 4.73: Mixer/Down-converter Linearity Measurement Set-Up
Simulated vs. Measured Conversion Gain Compression
There is a reasonable agreement between measured and simulated conversion gain values for
3 biases (Fig. 4.74). For lower input powers the discrepancy is up to 1.5 dB, which can be
104
Mixer
Figure 4.74: Mixer Conversion Gain Compression for 3 Bias Currents
attributed to superposition of several calibration uncertainties due to systematic shift (all
measured CG values are higher than the simulated).
Mixer’s oP1dB under 14.4 mA bias is 0 dBm, according to simulation (while the measured
value is 1 dB lower). The measured curves for mid- and high- bias point coincide, which might
be an indication that the linearity is slightly limited by the setup itself. The spectrum analyzer
(HP 41800A) could be the limiting block – its iP1dB= +3 dBm, which is close to the mixer
output power of 0 dBm (ideally instrumental linearity should be at least 10 dB higher than of
DUT).
4.3.10 Measurements vs. Simulations: Conv. Gain, Linearity, NF
Main mixer performance criteria vs. core bias are summarized in table 4.11. NF and conversion
gain have good measurement-simulation agreement. The linearity measurement-simulation
discrepancy is circa 4 dB in the worst case. Like in the LNA case, the most probable reason
for linearity performance discrepancy is the large signal HBT model.
Table 4.11: A Summary of Mixer’s Performance vs. Core Bias
Conversion Gain [dB] iP1dB [dBm] NFSSB [dB]
Ice,q [mA] simulated measured simulated measured simulated measured
7.5 6.14 7.1 -8 -12.3 12 12.5
10.8 6.7 8.4 -6 -9 12.32 12.6
14.4 7 8.1 -6 -8.3 12.8 12.8
105
Design of Circuits
An important observation would be that, per fixed supply voltage (Vcc= 1.6 V, as in this case),
while the current bias of the core is increased the available current headroom of the core also
increases. The available voltage headroom drops with current bias increase due to resistive
load stacking. For very low core bias currents there would be a negligible DC voltage drop on
the load.
At core bias of 14.4 mA on the load drops 0.7 V and at the transistor – 0.9 V . This voltage
headroom reduction is the reason why there is no linearity increase at higher bias currents per
fixed core voltage supply.
An obvious solution would be to increase Vcc at higher core currents. Setting the Vcc= 2.3 V
would allow 1.6 V voltage on the core. Such a biasing would have yielded a better linearity
without operating mixer transistors close to the breakdown region.
4.3.11 Benchmarks and Discussion
The mixer is benchmarked against the published 77 GHz (or similar frequency) mixers, both
SiGe as well as their III-V counterparts (table 4.12).
The III-V mixers shown in the table are passive and despite having different fmax
fcenter all have
similar performance. Conversion loss is circa 10 dB and so is NFSSB (in [93] the IF frequency
is 1 MHz, where flicker noise still dominates, so the NF is higher). A small area is achievable
due to little, if any balancing structures.
The SiGe table entries are all active HBT double-balanced mixers. This work has 1.6 dB worse
NF than the best published result. Conversion gain of 8 dB is the second lowest, since it was
traded-off for linearity. Interestingly, the design with comparable gain [106] uses the same
process as this design. The design with the highest gain [77] has worst linearity, as expected.
Here good linearity is achieved, despite 3 times lower supply voltage (1.6 V) and two-to-three
fold bias current reduction (22 mA) as compared to other designs. In order to allow comparison
under same LO conditions, circa 25 mW should be added to DC consumption of this design.
Nevertheless, the proposed mixer offers significant DC power reduction. It was achieved due
to: AC coupling between TRC and the core (which halved the TRC current consumption
compared to traditional Gilbert cell and loosened headroom limitation), deployment of passive
baluns for both RF and LO inputs. An obvious drawback of this design is the area, which is
mostly consumed by the long LNA input matching lines, use of 2 passive baluns (as opposed
to 1, usually), and size of each rat-race baluns.
106
Mixer
Table 4.12: Comparison of Standalone Mixers operating above fmax
5
GaAs OtheraInP SiGe
[93] [111] [5] This Work [106] [77] [20] [98] [40]
Node Size [µm] 0.13 0.15 0.1 0.25 0.13 0.35 0.13
ft[GHz] 90 381 150 180 210 200 225
fmax [GHz] >200 n.a. n.a. 220 280 275 330
fcenter [GHz] 77 77 94 77
fmax
fcenter 3>5>1.5 2.9 3.6 4.3
Mixer Type Resistive Diode Resistive Active
BalancingbNo Single No Double
Active Device HEMT pHEMT HEMT HBT
NFSSB [dB] 21 10 11 12.8 18.4 12 16.5 11.2 16
Conv. Gain [dB] -10 -7 -8 8.1 7 20 11 15 15.5
LO Power [dBm] +2 +12 +6 +3.8 +2 -2 -3 -3 -3
IF [MHz] 1 1000 11000 180 100 2000 10 10 10
iP1dB [dBm] n.a. n.a. 4 -8.3 -12 -26 -0.3 +2.5 -3
Vcc [V] – – – 1.6 4.5 5 5.5 5.5 5.5
Icc [mA] 0 0 0 21.6 39 13.4 75 61 34
Area [mm2]c0.3 0.3 1.05 1.86 0.28 0.6 0.63 0.68 0.5
aInGaAs/AlGaAs/GaAs
bMixers with single-ended RF and LO interfaces are benchmarked, i.e. with RF and LO on-chip baluns (where
applicable).
cWithout pads.
107
5 Receiver Integration
5.1 1-Channel Receiver
The NF of the mixer alone is generally too high to meet receiver’s (RX) sensitivity requirements.
Therefore a receiver normally includes an LNA before the mixer.
5.1.1 Realized 1-Channel Receiver
Receiver design involves a trade-off between linearity and sensitivity, like in LNA and mixer
designs. In the receiver case the trade-off is more severe due to cascading of the LNA and the
mixer. In this design each of the receiver sub-blocks: the LNA and the mixer were designed with
the system integration in mind (sections 4.1 and 4.3). The overall 1-channel RX schematics
are shown on Fig. 5.1.
Ibb_TRC
Ibb_core
Vcc_core
RFin
IF+
IF-
LO
Vcc_TRC
20 Ω
4 pF 4 pF
4 pF4 pF
2 pF
2 pF
6 pF 4 pF
4 pF
0.8 pF
0.8 pF
6 pF
5 Ω
20 Ω5 Ω
1k Ω
1k Ω
100 Ω
100 Ω
λ/4
λ/4
Q1
Q2
Q3
Q4
Q5
Q6
Mix Transconductance Mix Core
4 pF 4 pF
Q2
Ibb_LNA
20 Ω
Vcc_LNA
5 Ω
LNA
Figure 5.1: Detailed 1-Channel Receiver Schematics
Fig. 5.2 shows the 1-channel RX layout. Here different pads were used due to packaging require-
ments [90]. The receiver SiGe IC was flip-chipped onto standard thick-film processed LTCC.
The standard sub-mount processing minimal strip width and spacing is typically 100 µm.
109
Receiver Integration
Therefore all pads dimensions were 100 µm (as opposed to the pads previously deployed,
Fig. 3.9).
Figure 5.2: 1-Channel Receiver Layout
The low-gain, high-linearity of the LNA could offer an additional flexibility in the receiver
design. Namely, a single as well as multistage LNA realization is enabled. This is instrumental
in examining effectiveness of different degrees of mixer noise suppression.
5.1.2 Noise Figure
A mixer is a private case of a receiver so the receiver NF is analyzed in similar fashion to the
mixer NF (section 4.3.8). Also for receiver NF characterization the same mixer NF measure-
ment setup is deployed (Fig. 4.69).
Total Noise Temperature Derivation and Analysis
Due to difference in gain preceding the mixer core between the receiver and mixer cases the
total noise temperature analysis is repeated in the RX case.
The 1-channel receiver NF will be analytically derived using 2 approaches:
cascading LNA and the mixer noise figures;
cascading the LNA, TRC and the mixer core noise figures.
The analytically derived NF will be compared with the measurements. Additionally, the
potential benefits of image-rejection at various locations in the RX chain will be evaluated.
The measured conversion gain and NF are summarized in table 5.1.
110
1-Channel Receiver
To
TN,LNA
GLNA
LNA TL,LNA
TSSB, MIX
TL,MIX
CGRF,MIX
CGIMAGE,MIX
RX
LNA
MIX
Figure 5.3: 1-Channel Receiver: LNA Stage and Mixer Noise Temperatures
Approach 1: Total Noise Temperature Derivation: LNA and the Mixer
TL,LNA =GLNA ·(T0+TN,LNA) = T0·GLNA ·FLNA = 290 ·2.19 ·3.72 = 2362.6 K (5.1)
TL,MIX = (TL,LNA +TSSB,MIX)·CGRF,MIX +TL,LNA ·CGIMAGE,MIX (5.2)
= (2362.6 + 5237.4) ·6.5 + 2362.6·6.5 = 64756.9 K
on the other hand:
TL,RX =T0·GRX ·FRX ⇒FRX =TL,MIX/T0/GRX = 64756.9/290/10 = 22.32 (5.3)
NFRX = 10 ·log(FRX) = 10 ·log(22.32) = 13.49 dB (5.4)
which is close to the measured 12.5 dB (1 dB discrepancy). This is another confirmation for:
Table 5.1: 1-Channel Receiver and its Components’ Noise Figure Summary
Gain NFDSB NFSSB
[dB] ratio [dB] ratio [dB] ratio
LNA (TRC) 3.4 2.19 5.7 3.72 – –
Core 4.7 2.96 11.6 14.45 14.6 28.84
MIX (TRC+Core) 8.1 6.5 9.8 9.55 12.8 19.06
RX (LNA+TRC+Core) 10 10 9.6 9.12 12.6 18.2
111
Receiver Integration
the validity of LNA, mixer and the 1-channel receiver noise figure measurements;
applicability of the system noise analysis method (that considers image-channel noise
contributions).
TN,TRC
GTRC
TRC TL,TRC
TSSB, CORE
TL,CORE
CGRF,CORE
CGIMAGE,CORE
RX
TRC CORE
To
TN,LNA
GLNA
LNA TL,LNA
LNA
Figure 5.4: 1-Channel Receiver: LNA, Transconductance and Core Noise Temperatures
Approach 2: Total Noise Temperature Derivation: LNA, TRC and the Mixer Core
TL,LNA = 2362.6 K (5.5)
TL,TRC =GTRC ·(TL,LNA +TN,TRC) = GTRC ·(TL,LNA + (FLNA −1) ·T0) (5.6)
= 2.19 ·(2362.6 + (3.72 −1) ·290) = 6901.6 K
TL,CORE = (TL,TRC +TSSB,CORE)·CGRF,CORE +TL,TRC ·CGIMAGE,CORE (5.7)
= (6901.6 + 8049.5) ·2.96 + 8049.5·2.96 = 68081.8 K
The obtained results in equations (5.2) and (5.7) are virtually equal. This would be an exper-
imental confirmation of the following:
both approaches for the receiver overall noise figure calculation are equally valid (super-
position applies in the linear case);
the NFCORE was de-embedded correctly since an additional measurement involving transcon-
ductances (LNAs) and core was taken.
112
1-Channel Receiver
Case Study
1: 1-Channel Receiver Image Rejection after the LNA, before the Mixer
⇒∆NFdue to image rejection = 10 ·log TL,MIX, no image
TL,MIX
(5.8)
= 10 ·log (2362.6 + 5237.4) ·6.5 + 2362.6·0
(2362.6 + 5237.4) ·6.5 + 2362.6·6.5=−1.18 dB
Here the ambient noise is amplified by the LNA and is equivalent to that in section 4.3.8 while
the mixer noise is lower than the core noise in section 4.3.8. Therefore image rejection in this
case would be more effective than in section 4.3.8.
Case Study
2: 1-Channel Receiver Image Rejection after the TRC, before the Core
⇒∆NFdue to image rejection = 10 ·log TL,MIX, no image
TL,MIX
(5.9)
= 10 ·log (6901.6 + 8049.5) ·2.96 + 8049.5·0
(6901.6 + 8049.5) ·2.96 + 8049.5·2.96 =−1.87 dB
In this case the ambient noise amplified by 2 cascaded LNAs is approximately equal to the
core noise, which explain the circa 2 dB of improvement suggested by image rejection. This
theoretical benefit of image rejection is outweighed by the complexity of active image rejection
solutions so image rejection has not been used in the receiver case, too.
Case Study
3: an additional LNA before the RX – with Image Rejection before the Core
So far the noise figure was calculated for 3 main scenarios:
core stand-alone (de-embedding of the core noise figure, eq. 4.38)
mixer (TRC, core)
1-channel receiver (LNA, TRC, core)
For the sake of completeness a 4th scenario is suggested: the case where 1-channel receiver is
preceded by an LNA (so the new chain is: LNA, LNA, TRC, core). First a case without image
rejection will be considered and it will be complemented by the benefits offered by the image
rejection.
TL,TRC =GTRC ·(TL,LNA2 +TN,TRC) = GTRC ·(TL,LNA2 + (FLNA −1) ·T0) (5.10)
= 2.19 ·(6901.6 + (3.72 −1) ·290) = 16842 K
TL,CORE = (TL,TRC +TSSB,CORE)·CGRF,CORE +TL,TRC ·CGIMAGE,CORE (5.11)
= (16842 + 8049.5) ·2.96 + 16842 ·2.96 = 123531 K
113
Receiver Integration
FRX =TL,CORE
T0·G3
LNA ·GCORE
= 123531/290/2.193/2.96 = 13.7 (5.12)
NFRX = 10 ·log(FRX) = 10 ·log(13.7) = 11.4 dB (5.13)
so the overall noise figure of LNA+RX improves by circa 2 dB compared to the overall noise
figure of the RX (equation (5.4)). Despite of the 2 dB NF improvement an additional LNA
was not used before the RX since it would saturate both the TRC and the core. In case of
image rejection before the core:
∆NFdue to image rejection = 10 ·log TL,MIX, no image
TL,MIX
(5.14)
= 10 ·log (16842 + 8049.5) ·2.96 + 16842 ·0
(16842 + 8049.5) ·2.96 + 16842 ·2.96 =−2.24 dB
The tendency is clear – the more amplification is added, the more the ambient noise is amplified
and the additive noise of the core has less impact. In the limiting case (when the amplified
ambient noise is much higher than the additive noise of the core) the image rejection would
yield 3 dB improvement in the overall noise figure.
5.1.3 Linearity
Linearity Measurement Setup
The 1-channel RX linearity measurement setup is identical to mixer linearity measurement
setup (Fig. 4.73).
5.1.4 1-Channel RX Measurements
Conversion Gain and NF vs. Core Bias
Fig. 5.5 shows 1-channel RX gain and NF vs. core bias under the following conditions:
fLO = 77 GHz, PLO = 3.8 dBm, fRF = 76.82 GHz (so fIF = 180 MHz)
LNA stage bias: Vcc = 1.6 V, Ic, LNA = 3.6 mA
Differential transconductance stage bias: Vcc = 1.6 V, Ic, TRC = 7.2 mA
Mixer core stage bias: Vcc = 1.6 V
The measurement setup included the LTCC–Flip-Chip transitions and off-chip IF amplifier.
Transition and LTCC loss was circa 2 dB [90], the off-chip IF amplifier gain was circa 40 dB
and its noise contribution 1.6 dB. A quick subtraction of the transition and the IF amplifier
yields circa 12 dB of gain and NFDSB of circa 10.5 dB in the vicinity of the bias point of interest
(around 14.4 mA).
114
1-Channel Receiver
0 4 8 12 16 20
0
5
10
15
20
25
30
35
40
45
50
55
Core Bias [mA]
[dB]
Conversion Gain
NFDSB
Figure 5.5: 1-Channel RX Measured Conversion Gain and NF vs. Core Bias
Conversion Gain, Linearity, NF
Table 5.2 shows the 1-channel RX performance for 2 chip samples. The measurements were
done under similar conditions to Fig. 5.5, albeit the mixer core stage bias was fixed at 14.4 mA.
Table 5.2: 1-Channel RX Measurements for 2 Chip Samples
Chip Sample Gain iP1dB NFSSB
[dB] [dBm] [dB]
1 8.5 -10.4 12.6
2 9.8 -9.3 11.5
115
Receiver Integration
5.2 2-Channel Receiver
5.2.1 System Architecture
Multi-channel front ends are of great interest for current and future applications in vehicular,
wireless communications, sensors and military markets. The receive channel diversity could be
deployed to better exploit the information contained in the received signals for the following
purposes:
Angle-of-arrival estimation is required in LRR. Among other techniques this can be
achieved by antenna- and receiver-diversity with conjunction with parameter estimation
methods, based on subspace techniques [31], [63]
The information available from several receive channels could be deployed as an elec-
tronic beam former, by steering the beam away from an interferer towards the desired
signal. Therefore the immunity to multi-path scattering present in real-world conditions
is increased
Coherent summation of the multi-receiver outputs improves signal-to-noise ratios thereby
improving the equivalent receiver sensitivity
In FMCW radar the ranging information is in phase-frequency domain at the IF. Besides,
the amplitude information can be used to provide an estimate on the signal return power.1
Therefore ideally the FMCW radar down-converter should provide an I/Q output for the
IF circuitry. In any practical I/Q demodulator there is a mismatch between the channels,
which causes false targets to appear. The false targets appear at negatives of the true targets’
frequencies, with an amplitude reduction, which is a function of the I/Q mismatch. The 1-
channel case is a limiting case, where the magnitude of the image frequency is equal to the target
frequency. The negative close-frequency targets’ side-lobes can obscure far-target indications.
In this automotive case for the closest 2 meter target case the sidebands of sin(wbeat−w)Tsw/2
(wbeat−w)Tsw/2
are 45 dBc below the carrier and in conjunction with frequency-domain windowing in DSP the
required side-lobe level can be met.2The best trade-off between the suppression of sidebands
and the width of the main lobe is offered by Kaiser window. Therefore in this particular case
(given fcenter, ∆F,Tsw) no explicit I/Q demodulation is necessary – a single I channel with
appropriate processing is sufficient.
The 2-channel receiver realized in this work is a step in the direction of a multi-receiver IC: it
is an integration of two same, I-channel receivers into one IC.
1Which can be deployed for coarse ranging estimate and in MIMO systems – to reduce effects of multi-path
fading.
2The frequency windowing is an important condition if I channel is to be transformed into Q by a linear
operation of filtering, known as Hilbert transform [70].
116
2-Channel Receiver
5.2.2 LO Splitter
Functionality
While the 2-channel receiver has 2 separate single-ended RF inputs and 2 separate differential
IF outputs the same LO is shared between the channels. A so-called “LO Splitter” circuit is
responsible for the following:
Splitting the common LO reference into two separate signals, needed to drive mixers of
each channel receivers. Without limitation of generality an in-phase output division is
adopted.
Amplifying and buffering the LO power. This means an active solution, being deployed
close to saturation.
Providing sufficient power to drive each mixer – circa 4 dBm single-ended at each receiver
LO input (before the LO balun), measured on 50 Ω.
Providing isolation between the 2 LO outputs, so an unwanted excitation at one of the
LO outputs is sufficiently attenuated at the second LO output.
In conjunction with the requirements a 3 common-emitter transistor topology is suggested as
depicted in the schematics on Fig. 5.6. In this way 2 transistors contribute to isolation. Each
LO chain consists of 2 common-emitter cascaded stages, when biased for fmax should provide
circa 8 dBs of gain.
Realized LO Splitter
Unlike the the LNA, which had a low Ohmic (wide) series λ/4 transmission line, here an
emphasis was put on the compactness on the layout. Therefore, a narrow-band πnetwork of
2 inductive lines with a series capacitor was used for the input match (Fig. 5.6). Interstage
matching network involved open shunt (capacitive) stub with an additional, tuning capacitor.
It was designed to peak around 90 GHz in order to suppress the otherwise peaking gain at
65 GHz. Therefore the in-band gain was sacrificed for stability. The interstage matching
involved a series capacitor to allow AC-decoupling between the common-emitter so their bias
can be set separately. A LC section was deployed for output match. The DC supplies of the 2
in-phase output stages were tied together with several decoupling capacitors in between. Due
to symmetry of the in-phase structure, no imbalance was expected. Therefore only 1 output
was probed, with the second terminated by on-chip 50 Ω termination (Fig. 5.7).
RF Stability The Rollett stability analysis cannot be directly applied to multi-stage designs
[33]. Therefore the circuit was treated as a cascade of 2 single transistor amplifiers: 1st stage
– from the input until the splitting point and the 2nd stage – from the splitting point until
the output (the other output stage was terminated by a 50 Ω). The Rollett analysis was
applied to the 2 stages (Fig. 5.8). For both stages the stability factor is higher than 1.5 over
all frequencies, so the design is unconditionally stable for an RF excitation at I/O.
117
Receiver Integration
4 pF
4 pF
4 pF
2 kΩ4 pF
4 pF
4 pF
4 pF
I2
I1 V1
V2
LO_in
LO_out_1
LO_out_2
2 kΩ
4 pF
4 pF
4 pF
4 pF
4 pF 170 µm
6.5 µm
x
300 µm
5 µm
x
110 fF
125 µm
5 µm
x100 µm
5 µm
x
100 fF
120 µm
14 µm
x54 µm
14 µm
x
200 fF
32 µm
14 µm
x
185 µm
5.5 µm
x
70 fF
70 fF
185 µm
5.5 µm
x
32 µm
14 µm
x
npn201_8
npn201_8
npn201_8
Q1
Q2
Q3
Figure 5.6: LO Splitter Schematics
Supply Stability Like in the LNA case, stability problems (such as spectral regrowth and
supply modulation) were seen during LO-splitter measurements. They were solved similarly
to the LNA case: at the 1st stage base same RC circuit as shown on Fig. 4.12 was soldered on
the needle-holder. The deployed elements’ values were: Cstab = 10 nF, Rstab = 50 Ω. Fig. 5.9
shows the supply-related stability for several Rstab. Without the stabilizing RC network the
simulated stability factor is as low as 0.3. With the stabilizing RC network the simulated
stability factor is above 1.8.
Large Signal Measurements vs. Simulation
The LO Splitter output may not be linear, or low noise – it just has to provide a large power
signal at the LO frequency so proper mixing operation takes place 4.3.5. So unlike other active
circuits presented in this work, the LO Splitter is to be operated in a single drive point, in
close proximity to 1 dB compression point or, possibly, even beyond. Therefore the large signal
measurements would be most informative in this case. The same setup was used as in the LNA
case (Fig. 4.22).
118
2-Channel Receiver
Figure 5.7: LO Splitter Layout
The measurements were taken under the following DC conditions:
1st stage bias: ICE,q= 11.7 mA, VCE= 1.6 V
2nd stage bias: ICE,q= 20 mA, VCE= 1.6 V
Here also in the small-signal region there is a good simulation-measurement agreement, while
above P1dB point 1.5 dB of discrepancy is observed. The LO Splitter oP1dB (per each output)
is +4 dBm (Fig. 5.10), which is enough to satisfy the LO drive requirement of +4 dBm per
mixer. If higher LO power drive is required, the LO Splitter can be preceded by an additional
gain stage and be operated in the region closer to its’ Psat= +6 dBm.
5.2.3 Isolation
Since the 2 channels are independent, both should be maximally isolated from each other. The
interaction sources between the channels are:
EM-coupling between RF paths
power supply planes (includes ground plane) coupling
119
Receiver Integration
0 10 20 30 40 50 60 70 80 90 100 110
100
101
102
frequency [GHz]
K, Rollett Stability Factor
1st stage
2nd stage
Figure 5.8: RF Stability Factor of the LO Splitter Stages
1071081091010 1011
10−1
100
101
102
103
frequency [GHz]
K, Rollett Stability Factor
no Rstab
Rstab = 5 kΩ
Rstab = 500 Ω
Rstab = 50 Ω
Figure 5.9: LO Splitter Supply-related Stability Factor as Function of Shunting Resistor
substrate coupling
A standard specification for a multi-channel receiver isolation is 30 dB.
Isolation Improvement Techniques
1. Differential approach. A fully differential approach for the mixer allows good rejection of
common noise components of the following: supply noise, substrate noise, base shot and
120
2-Channel Receiver
(a) Pout vs. Pin (b) Gain vs. Pin
Figure 5.10: LO Splitter Large Signal Measurements
flicker noises [96]. For a single channel to get the benefits of fully differential operation
the collectors of in- and out- of phase channels have to be tied together. For a 2 channel
receiver, all 4 collectors are tied together to reduce DC pin count.
2. Bond pad shielding. The large area consumed by the pad is a receiver of substrate noise.
So, to isolate the substrate from the pad shielding was placed in-between them – a ground
at bottom metal M1.
3. Substrate potential control. To prevent circuit to circuit cross-talk through the con-
ducting substrate the individual stages could be isolated by controlling the substrate
potential at each circuit boundaries. This was achieved by placing substrate contacts
at each circuit’s periphery (so substrate noise is coupled within a functional block, and
between any different circuits and receiver channels substrate coupling is reduced).
4. Electric wall. Deep trench isolation functions as an electric wall between the active de-
vices and thus helps to reduce crosstalk between them. In this process no deep trench iso-
lation was used, therefore an electric wall was placed between the 2 channels (Fig. 5.12).
These walls help break up the conductive silicon substrate to interrupt leakage paths
and reduce signal and noise coupling between circuits. Other possible device isolation
methods are buried oxide, p+ guard ring, triple well [47]. Substrate leakage at mm-wave
frequencies in [73] is reduced by placing a pattern of small checkered n-well and p-subs
contacts regions between circuit blocks.
5. Higher order supply decoupling. Leakage through power and bias planes can be re-
duced by taking lessons from printed circuit board (PCB) design. Power, bias, and
ground planes must be maximally capacitive, minimally inductive and resistive, and
separate (or at least split) for circuit blocks that must be isolated. Separate power sup-
ply domains should be used for different functional blocks [73]. Each of the LNAs and
121
Receiver Integration
transconductance-stages’ collectors were supplemented with a 2-section RC low pass fil-
ter (R= 5 Ω series, C= 4 pF shunt). Assuming that on-chip supplies’ paths have low
impedance of 1 Ω - each RC section yields 17 dB rejection at 77 GHz, so 4 sections (that
connect any 2 collectors) yield rejection of 68 dB.
5.2.4 Realized 2-Channel RX
The realized 2-channel receiver includes: 17 transistors, 4 baluns, 39 I/O pins for testability.
The schematics is shown on Fig. 5.11, layout – on Fig. 5.12 and a micrograph – on Fig. 5.13.
Since the 2-Channel RX was flip-chipped like 1-Channel RX [90], the same 100 µm pads were
used.
5.2.5 2-Channel RX Measurements
Isolation
Isolation measurement procedure was as follows:
1. Channel 1 IN was left floating.
2. Gunn oscillator signal is applied to Channel 2 IN as in P1dB setup (Fig. 4.73).
3. Channel 1 IFout was probed.
The measured isolation is better than 37 dB (table 5.3).
Conversion Gain vs. IF
Fig. 5.14 shows the conversion gain of the 2 channel receiver measured vs. IF under the
following conditions (per each channel):
LNA stage bias: Vcc = 1.6 V, Ic, LNA = 3.6 mA
Differential transconductance stage bias: Vcc = 1.6 V, Ic, TRC = 7.2 mA
Mixer core stage bias: Vcc = 1.6 V, Ic, core = 14.4 mA
PLO was set to −2 dBm. Since the off-chip IF amplifier (5006 by Brookdeal) 3 dB bandwidth
is limited (0.1 Hz . . . 1 MHz) due to input equivalent dominant 30 pF capacitor, this capacitor
was included in the simulation. Measurements agree reasonably well with the simulation.
Conversion Gain, Linearity, Isolation, NF
Table 5.3 shows the 2-channel RX performance under similar conditions to conversion gain vs.
IF measurement. Here, additionally, the RF and LO frequencies were fixed: fLO = 77 GHz,
fRF = 76.82 GHz (so fIF = 180 MHz).
122
2-Channel Receiver
I33
I55
V44
RF1
IF1+
IF1-
20 Ω
4 pF 4 pF
4 pF4 pF
2 pF
2 pF
6 pF 4 pF
4 pF
0.8 pF
0.8 pF
6 pF
5 Ω
20 Ω5 Ω
1k Ω
1k Ω
100 Ω
100 Ω
λ/4
λ/4
Q1
Q2
Q3
Q4
Q5
Q6
4 pF 4 pF
Q2
I11
20 Ω5 Ω4 pF
5 Ω
5 Ω
4 pF
4 pF
5 Ω
V11
V22
4 pF
4 pF
4 pF
2 kΩ4 pF
4 pF
4 pF
4 pF
I2
I1 V1
V2
LO_in
2 kΩ
4 pF
4 pF
4 pF
4 pF
4 pF 170 µm
6.5 µm
x
300 µm
5 µm
x
110 fF
125 µm
5 µm
x100 µm
5 µm
x
100 fF
120 µm
14 µm
x54 µm
14 µm
x
200 fF
32 µm
14 µm
x
185 µm
5.5 µm
x
70 fF
70 fF
185 µm
5.5 µm
x
32 µm
14 µm
x
npn201_8
npn201_8
npn201_8
Q1
Q2
Q3
I44
V44
RF1
IF2+
IF2-
20 Ω
4 pF 4 pF
4 pF4 pF
2 pF
2 pF
6 pF 4 pF
0.8 pF
0.8 pF
6 pF
5 Ω
20 Ω5 Ω
100 Ω
100 Ω
λ/4
Q1
Q2
Q3
Q4
Q5
Q6
4 pF 4 pF
Q2
I22
20 Ω5 Ω4 pF
5 Ω
5 Ω
4 pF
4 pF
5 Ω
I66
4 pF
1k Ω
1k Ωλ/4
6 pF
6 pF
2 pF
2 pF
2 pF
2 pF
Figure 5.11: Detailed 2-Channel Receiver Schematics
123
Receiver Integration
Figure 5.12: 2-Channel Receiver Layout
Figure 5.13: 2-Channel Receiver Micrograph
124
2-Channel Receiver
100 200 300 400 500
0
2
4
6
8
10
12
14
IF [MHz]
Conversion Gain [dB]
Channel
1
Channel
2
calculated with IF amplifier
Figure 5.14: 2-Channel RX Measured Conversion Gain vs. IF
5.2.6 Benchmarks and Discussion
The realized receivers are benchmarked against the published 77 GHz receivers, both SiGe-
based (table 5.4) as well as their CMOS counterparts (table 5.5).
The realized 1-channel receiver NF is 1.6 dB higher than the published SiGe receiver NF
with comparable linearity [22] and 2.6 dB higher than best published CMOS receiver NF [50].
However, the realized 1- and 2-channels receivers involved also flip-chip LTCC transition, unlike
the other receivers in the both tables which were measured directly on-chip. The transition
directly contributed 2 dB to the overall NF, so the on-chip NF of the realized receiver is among
the top reported results.
The realized receivers’ gain (circa 10 dB) is among the lowest reported in both SiGe and CMOS
due to a low-gain high-linearity design approach.
The realized receivers’ linearity are among the highest reported. The linearity value is 2.6 dB
lower than the best published value [97]. However, the receiver in [97] incorporated no LNA
and consumed more than 5 times (7 dB) DC power.
Table 5.3: 2-Channel RX Measurements
Channel Gain iP1dB Isolation NFSSB
[dB] [dBm] [dB] [dB]
1 12.1 -11.4 >45 16.5
2 10.7 -10.9 >37 14.3
125
Receiver Integration
Table 5.4: Comparison of 77 GHz SiGe HBT-based Receiver Front-Ends
Node ft, fmax
fmax
fcenter NFSSB Gain iP1dB PDC Area Integrationa
Size
[µm] [GHz] [dB] [dB] [dBm] [mW] [mm2]
This
Work
0.25 180, 220 2.9 12.6 10 -10.4 40.3 1.74 (LNA, BALUNs,
Mixer; Flip-Chip)
This
Work
0.25 180, 220 2.9 16.5 12.1 -11.4 132 5.4 2-Ch. RX: (LNAs,
BALUNs, Mixers,
LO-Splitter; Flip-
Chip)
[106] 0.25 180, 220 2.9 10.2b21.7 -35 345 0.5 (LNA, BALUNs,
Mixer, IF-buf.)
[3] 0.13 207, 285 3.7 12 37 <-30 100 2.5 (LNA, Mix., IF-
Amp, Mix., BB-
Amp.)
[46] 0.18 180, 200 2.6 11 31 -30.7 162.5 2.4 I-Q RX: (LNA,
Mix., VGA)
[22] 0.35 200, 275 3.6 11 28 -16 1073 1.1 I-Q RX: (LNA,
BALUNs, Hybrid,
Mix.)
[77] 0.13 210, 280 3.6 11.5 40 <-40 195 1.7 (LNA, Mix., VCO)
[73] 0.13 170, 200 2.6 12 25.6 -24 120 0.4 (LNA, Mix., IF-
Amp.)
[54] 0.13 200, 250 3.2 14 24 -10 132 0.75 (LNA, Mix.)
[97] 0.18 200, 200 2.6 13 24 -7.8 238 1.12 (BALUN, Mix., IF-
Buf.)
[74] 0.13 220, 250 3.2 7.8 24 -21.7 123 0.24 (LNA, Mix., IF-
Amp.)
a1 Channel RX, unless explicitly noted.
bSimulated value.
126
2-Channel Receiver
The realized front-end performance in main categories (such as noise figure, linearity, gain and
DC consumption) resembles most the front-end in [51]. Interestingly, [51] is a front-end in
65 nm CMOS. The front end in [51] also consumes lowest area due to extensive deployment
of inductors (as opposed to longer microstrip transmission lines, some of which are λ/4 in this
design).
Table 5.5: Comparison of 77 GHz CMOS FET-based 1-Channel Receiver Front-Ends
Node NFSSB Gain iP1dB PDC Area Integration
Size
[nm] [dB] [dB] [dBm] [mW] [mm2]
[51] 65 12 13 -16 89 0.24 (LNA, BALUNs,
Mixer, IF-Buf.)
[50] 90 10 8 n.a. 260 0.55 (LNA, BALUNs,
Buffers, Mixer,
IF-Buf.)
[60] 65 11.4 38 <-30 45 0.5 (LNA, Mixer, IF-
Buf.)
[71] 90 15.6 23.1 n.a. 111 1.2 (BALUN, LNA,
Mixer, IF-,
LO-Buf.)
[59] 65 12.2 33.7 -32 16.9 0.52 (LNA, Mixer, LO
BALUN)
127
6 Conclusions
This work presents a systematical analysis and design procedure of an integrated millimeter-
wave high performance, low power multi-channel receiver operating at fmax
3in SiGe for auto-
motive LRR. The low-gain high-linearity LNA design approach applied in this work allowed
paradigm shift from either a high-linearity (and high noise) or a low-noise (and poor linearity)
front-end to a finer trade-off between both performance criteria.
In the case of the mixer the conventional approach of design for high gain was modified, too. A
high gain mixer, one one hand, would facilitate suppressing the IF stages’ noise contributions.
On the other hand, in this application a high gain mixer would overdrive the IF buffer / ADC
converter. The overall front end linearity would be compromised as a result. Thus, mixer
target specs were redefined as low-gain, low-noise and high-linearity. Additionally, the LNA
was re-used as the mixer’s transconductance stage. This decision offered the following benefits:
transconductance stage (TRC) input match improved mixer’s conversion gain, a 50 Ω output
match resonated out the unmatched transistor’s output capacitance. Traditional DC-coupling
between transconductance and mixer core (as in case of Gilbert cell) would result in half of the
TRC transistor DC-current flowing through each core transistor. This would set constraints on
both the current and the TRC and the core sizings, which ideally should be design parameters.
Additionally, TRC and core stacking would mean voltage headroom limitation to both. AC-
coupling came to break out of these trade-offs: the TRC was sized, designed and biased for
low noise and the core for linearity and low noise; and the full headroom was made available
to both mixer stages (excluding the resistive load).
Special attention was paid to the design of the transformer baluns. The resulting balun perfor-
mance allowed relaxing the common-mode rejection requirements from the LNA and the mixer
and yielded an additional performance improvement (by avoiding the additional stacking of
current sources / sinks / resonators).
The forementioned circuit components were integrated into a 2 channel low-IF homodyne re-
ceiver. The LO was distributed by an active buffered in-phase LO power splitter. Several
isolation techniques were deployed. The measured isolation between the two receive channels
exceeded 35 dB. The measured 2-, 1-channel receivers and the mixer have comparable perfor-
mance to the published state-of-the-art results in SiGe technology (despite using the “slowest”
technology among the benchmarks). Important to stress the record-low DC consumption –
132 mW, 40.3 mW and 34.6 mW, respectively, which is circa 1
8of the consumption of the
similarly performing SiGe receiver in [22]. The power consumption is on par with that of a
65 nm CMOS front-end with comparable performance [51]. In the automotive case there is a
very tight budgeting of the available power and with hybrid/electrical cars the available power
129
Conclusions
for the driving assist systems is going to shrink further, so the achieved low DC consumption
is a welcome feature.
For further development of the receiver, the following approaches should be investigated:
Shrinkage of the LNA input match. The area of the LNA was large mostly due to a
series λ/4 line. To reduce the layout size this line either can be bent or a different input
matching topology could be investigated (for example as used in the LO Splitter).
Incorporation of transformer. The transformer was realized as a stand-alone circuit only.
The 2-channel receiver required 4 baluns, so if the rat-race couplers are exchanged by
the transformers considerable area reduction can be achieved.
Alternative approach to LO Splitter. The realized fully active LO Splitter involved
complex custom design. To reduce the risk, to allow better modularity and designability
an alternative approach to LO splitting between the RX channels can be of benefit.
The operation of a double-balanced mixer is retained if LO signal reverses it phase. This
observation implies replacement of the in-phase LO Splitter by an anti-phase LO Splitter.
The anti-phase LO Splitter can be realized by re-using of the same transformer circuit
(if amplification is needed – it can be added either at the transformer input and / or
output by gain stages, such as LNA).
Mixer-only receiver. Since the realized LNA gain is low, deployment of a single LNA
/ several LNA stages was considered in section 5.1.2. The LNA addition improves the
overall receiver noise figure, while impairing the receiver linearity. A different approach
of totally removing the LNA stages while deploying a low-noise high-linearity mixer is a
very interesting alternative that could be studied further.
As next step, the presented high performance receiver can be realized in the BiCMOS technol-
ogy and further integrated with an analog baseband, power management and digital baseband
processing circuit blocks. The digital signal processing of the radar signals may profit by possi-
bility of high level integration in CMOS and considerably lower power consumption compared
to bipolar logic. This opens an opportunity for more flexible digitally intensive modulation
schemes, such as phase-modulated continuous wave (PMCW). As well, this will result in a
competitive, inexpensive, low-power, highly-integrated multichannel commercial solution. It
can be applicable, in addition to automotive long range radar in other demanding industrial
and consumer applications, among which are imaging systems, sensors, communication sys-
tems, such as point-to-point (microwave relay links, two-way radio) and point-to-multipoint
(long-range wireless backhaul links, broadcasting).
130
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